ATE520203T1 - Mehrwertige logikschaltung - Google Patents

Mehrwertige logikschaltung

Info

Publication number
ATE520203T1
ATE520203T1 AT08738033T AT08738033T ATE520203T1 AT E520203 T1 ATE520203 T1 AT E520203T1 AT 08738033 T AT08738033 T AT 08738033T AT 08738033 T AT08738033 T AT 08738033T AT E520203 T1 ATE520203 T1 AT E520203T1
Authority
AT
Austria
Prior art keywords
resistors
logic
push
logic circuit
value logic
Prior art date
Application number
AT08738033T
Other languages
English (en)
Inventor
Viktor Olexenko
Original Assignee
Fuzzy Chip Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuzzy Chip Pte Ltd filed Critical Fuzzy Chip Pte Ltd
Application granted granted Critical
Publication of ATE520203T1 publication Critical patent/ATE520203T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0002—Multistate logic
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)
  • Electronic Switches (AREA)
AT08738033T 2007-05-10 2008-04-30 Mehrwertige logikschaltung ATE520203T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU2007117392/09A RU2331105C1 (ru) 2007-05-10 2007-05-10 Универсальный мостовой инвертирующий сумматор
PCT/IB2008/051671 WO2008135914A2 (en) 2007-05-04 2008-04-30 Multivalued logic circuit

Publications (1)

Publication Number Publication Date
ATE520203T1 true ATE520203T1 (de) 2011-08-15

Family

ID=39746504

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08738033T ATE520203T1 (de) 2007-05-10 2008-04-30 Mehrwertige logikschaltung

Country Status (5)

Country Link
US (2) US7859312B2 (de)
EP (1) EP2171847B8 (de)
AT (1) ATE520203T1 (de)
RU (1) RU2331105C1 (de)
WO (2) WO2008135914A2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2331105C1 (ru) 2007-05-10 2008-08-10 Виктор Викторович Олексенко Универсальный мостовой инвертирующий сумматор
RU2394366C1 (ru) * 2009-05-28 2010-07-10 Сергей Петрович Маслов Пороговый элемент троичной логики и устройства на его основе
WO2012143016A1 (en) * 2011-04-18 2012-10-26 Abo Warda Magdi Al Saeed Ahmed Magdi's logic (ternary logic)
JP5738749B2 (ja) * 2011-12-15 2015-06-24 ルネサスエレクトロニクス株式会社 Ｐｌｌ回路
RU2546082C1 (ru) * 2014-04-30 2015-04-10 Федеральное Государственное Бюджетное Образовательное Учреждение Высшего Профессионального Образования "Донской Государственный Технический Университет" (Дгту) МНОГОЗНАЧНЫЙ СУММАТОР ПО МОДУЛЮ k
WO2017160863A1 (en) 2016-03-15 2017-09-21 Louisiana Tech Research Corporation Method and apparatus for constructing multivalued microprocessor
US10646996B2 (en) * 2017-07-21 2020-05-12 Vicarious Fpc, Inc. Methods for establishing and utilizing sensorimotor programs
CN109857368B (zh) * 2018-12-20 2022-07-26 上海大学 一种位数众多、可分组、可重构的多值电子运算器及方法
RU2724802C1 (ru) * 2019-12-30 2020-06-25 Федеральное государственное бюджетное образовательное учреждение высшего образования "Забайкальский государственный университет" (ФГБОУ ВО "ЗабГУ") Сумматор натуральных чисел

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4229803A (en) 1978-06-02 1980-10-21 Texas Instruments Incorporated I2 L Full adder and ALU
DE2855922A1 (de) * 1978-12-23 1980-07-10 Hoechst Ag Verfahren zur herstellung von zinkfreien alkaliphosphatloesungen
US4577160A (en) * 1983-01-03 1986-03-18 Robert H. Rines Method of and apparatus for low noise current amplification
JPS61153778A (ja) * 1984-12-27 1986-07-12 Toshiba Corp アナログ演算回路
US4814644A (en) * 1985-01-29 1989-03-21 K. Ushiku & Co. Basic circuitry particularly for construction of multivalued logic systems
SU1739476A1 (ru) * 1989-09-19 1992-06-07 Винницкий политехнический институт Усилитель тока
RU2178235C1 (ru) * 2000-09-29 2002-01-10 Олексенко Виктор Викторович Малошумящий широкополосный усилитель тока олексенко-колесникова
RU2176850C1 (ru) 2000-10-20 2001-12-10 Олексенко Виктор Викторович Малошумящий широкополосный усилитель тока
JP4342910B2 (ja) 2003-10-31 2009-10-14 Ｎｅｃエレクトロニクス株式会社 差動増幅回路
US7187208B2 (en) * 2005-01-19 2007-03-06 Phaselink Semiconductor Corporation Complimentary metal oxide silicon low voltage positive emitter coupled logic buffer
US7579872B2 (en) * 2006-05-31 2009-08-25 Fujitsu Limited Low-voltage differential signal driver for high-speed digital transmission
RU2331105C1 (ru) 2007-05-10 2008-08-10 Виктор Викторович Олексенко Универсальный мостовой инвертирующий сумматор
KR100912964B1 (ko) * 2007-09-04 2009-08-20 주식회사 하이닉스반도체 Ｃｍｌ－ｃｍｏｓ 변환기

Also Published As

Publication number Publication date
US20110121861A1 (en) 2011-05-26
WO2008140357A1 (ru) 2008-11-20
US20100164596A1 (en) 2010-07-01
WO2008135914A3 (en) 2008-12-31
EP2171847B8 (de) 2012-02-08
WO2008140357A8 (ru) 2009-09-11
RU2331105C1 (ru) 2008-08-10
US8120384B2 (en) 2012-02-21
US7859312B2 (en) 2010-12-28
EP2171847A2 (de) 2010-04-07
EP2171847B1 (de) 2011-08-10
WO2008135914A2 (en) 2008-11-13

Similar Documents

Publication Publication Date Title
ATE520203T1 (de) Mehrwertige logikschaltung
JP2017505898A5 (de)
CN104133515A (zh) Pmos管衬底选择电路
ATE521123T1 (de) Photovoltaiksystem
ATE524874T1 (de) Wandler mit parallel geschalteten differentialeingabepaaren
ATE524873T1 (de) Verstärkerschaltung
CN110858136B (zh) 具有减少延时的全加器电路
JP2016535487A5 (de)
CN100530965C (zh) 低输入电压的高效能电压电位转换电路
ATE471598T1 (de) Hochspannungsschalter mit niedrigspannungstransistoren
US10256818B2 (en) Level shifter
FI20175422A1 (fi) DC-DC jännitemuunnin ja jännitemuuntimen hallintajärjestelmä
TW200719583A (en) Differential amplifier and semiconductor circuit
TW200629726A (en) A common-mode shifting circuit for CML buffers
JP2006042349A5 (de)
CN104639149B (zh) 三模高速的电平向上转换电路
CN105938379A (zh) 基准电压电路
CN104079172A (zh) 适用于开关电源的高稳定性内部供电电路
CN105322945A (zh) 电流限制电平调整电路
CN100536298C (zh) 一种阱自偏置开关电容电荷泵电路
CN108604816B (zh) 具有改进的平衡的蓄电池布置系统
CN106208773B (zh) 一种变换器拓扑
JPWO2021070246A5 (de)
JP6345984B2 (ja) スピーカ装置
CN207977899U (zh) 可随输入信号变动工作电源的动态电源系统

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties