WO2012143016A1

WO2012143016A1 - Magdi's logic (ternary logic)

Info

Publication number: WO2012143016A1
Application number: PCT/EG2011/000010
Authority: WO
Inventors: Magdi Al Saeed Ahmed ABO WARDA
Original assignee: Abo Warda Magdi Al Saeed Ahmed
Priority date: 2011-04-18
Filing date: 2011-05-05
Publication date: 2012-10-26

Abstract

The logic of a new algebra can be applied electronically and depends on ( 0 ) and ( 1 ), but in three aspects { ( 0 0 ), ( 1 0 ) and ( 1 1 ) } instead of two aspects { ( 0 ) and ( 1 ) } where that logic (the logic of Boolean) depends on the bilateral (false - true) or (On - Off) Or (length - width) as well as the logic used to write from left to right. The New logic based on the triple standby - Off) or aspect ( false - could be false or right - true ) or (on - (Length - height - width) as the new logic supports the writing of right to left, where it is the secret of making supper computer * There were attempts by the Russian University supernatural work of the computer using the triangular logic, but have been unsuccessful so far. You can look at (Ternary Computer ) and I think that my new logic will allow adding a third dimension to the computer, it also will minimize the space needed for any program.

Description

Magdi's logic ( Ternary logic )

1) Technical Field

The new algebra logic will be consider as one of the main basics that are used for designing and installing the computer to become later the basic of designing the logic circuits of the computer.

The variable is called (logic) if it has always one of the following three aspects, the false case (definite false) , unknown case (may be false or true) and the true case (definite true) . We could develop logic laws that are consisted of a group of the logic gates.

The previous logic laws are used to build the digital electronic circuits that are mainly consisted of a group of the logic gates . These gates will be the engineering application of the above mentioned logic operations.

2) Background Art

The Boolean algebra considered to be the main basics used in designing and installing the computer. The theoretical basics of the Boolean algebra also known as "logical algebra" has been put by virtue of the English popular scientist of mathematics - George Boole. This scientist has spread his theories in the middle of the nineteenth century to become later the basic in the design of logic circuits of which the computer is consisted. The variable is called a Boolean one (or logic) if it always holds one of the following aspects. The false aspect (false) and the true one (true). Logic laws could be created which are consisted of a group of the logic gates.

The previous logic laws have been used to build the digital electronic circuits that consist mainly of a group of the logic gates. These gates are the engineering application of the above mentioned logic operations.

There are three main gates based on the three main operations and we call them the same name: (AND) gate, (OR) gate and (NOT) gate. The figure No. (1-4/1) shows the symbols of the main logic gates used in the mentioned systems.

AND

OR

NOT

(Figure 1-4/1)

The derived logic gates:

These gates are derived from the main logic gates which are:

(NAND) gate

It is the (AND) gate connected to (NOT) gate as described in the figure No. (2-4/1). It works the opposite of (AND) gate.

NAND

(Figure 2-4/1)

(NOR) gate

It is the (OR) gate connected to (NOT) gate as described in the figure No. (3-4/1). It works the opposite of (OR) gate.

NOR A B A.B

0 0 1

1 0 0

0 1

1 1 0

(Figure 3^ /1)

(XOR) gate

It is a gate that gives a result of the true aspect if its inputs are not the same while it gives a result of the false aspect if its inputs are the same. Its mathematical symbol is a small circle including a plus sign. Its logic symbol is as the following Figure No. (4-4/1).

XOR

(Figure 4-4/1) Exclusive -(NOR) or equivalence gate

It is the (XOR) gate connected to the (NOT) gate as described in the figure No. (5-4/1). Note that this gate gives a result of the true aspect if its inputs are the same while it gives a result of the false aspect if its inputs are not the same. It works opposite of (XOR) gate.

EQV

(Figure 5-4/1)

(Half adder) gate

When we combine the (XOR) logic gate connected to (AND) logic gate, we get two values: one value is the add result and the other is the carry, it is called adder gate (half adder) as described in the figure No. (6-4/1).

When combining the (XOR) gate connected to (AND) gate

(Figure 6-4/1)

(Full adder) gate

However, the carry requires a third input. When combining two gates of (XOR), two gates of (AND) and one (OR) gate, the combination called the full adder gate that has a third input of the carry as described in the figure No. (7-4/1).

(Figure 7-4/1)

1 1 0 Carry

0 0 1 1

Oil 3

1 0 0 4

The problem or defect of the background art: The binary logic

The statement are used only to provoke whether for positive or negative results during the thinking process.

Definitely, the results are only false or true, right or wrong.

(Which leads to that the intellectual believes when they are right so they don't think of other solutions. They believe that they have made the right decisions so there is no need to re-think). The statement may be only true or false.

The binary thinking is allowed only by the two available colors and it would be shocked if the thinking was not true or false e.g. "not sure".

The binary thinking leads to simplify the problems and situations besides simplifying the polarization cases from the arguments.

It learns the discussion only at the end, the emotional polarization and etc. are the elements that contribute to this way of thinking.

When applying the binary logic on the computer, it is the logic of true or false - the statement must be true or false.

It depends on the logic of reading from the left to the right. Which will not allow to add higher capacities to the computer, e.g. when you add higher capacities for (RAM), the capacity of the computer shall be increased in this area.

It uses more useless spaces.

It depends on the logic of reading from the left to the right that contradicts with the reading logic to solve the equations that require reading from the right to the left.

Many useless equations lead to the increase of heat.

Depending on the binary logic made the computer to be a two dimension. The new of the invention subject

Magdi's logic Ternary logic

The statement are used to provoke whether for positive or negative or unknown results during the thinking process.

The statement can be true or false or unknown (no comment, (can be true or false)

It allow to combine a group of thoughts and language and lead solving the indefinite thoughts and be definite that the solutions are not only false or true but also (not sure) as a solution.

(This leads to the intellectual believes that the solution he toke is not the perfect right so it is necessary to think of other solutions. The thinker does not believe that he has absolutely made the perfect decision. Hence, the thinking to achieve the best solution is a motive to correct the thinking way and certainty).

The ternary thinking allows flexibility of discussion and rational cohesion with different degrees of passion and a portrayal complicated more than the opinion.

It can be learnt the neutralism, science and forgiveness and taking all attitudes leads naturally to this way of thinking.

When applying the ternary logic on the computer, it allows three logic variables (false-unknown-true) - the statement can not be only true or false but also unknown. It depends on the logic of reading from the right to the left. It allow to add higher capacities to the computer, e.g. when you add higher capacities for (RAM), the capacity of the computer shall be increased in this area.

It uses less space.

It depends on the logic of reading from the right to the left that comply with the reading logic to solve the equations that require reading from the right to the left.

Its dependence on the ternary leads the computer to be a three dimension. 3) Disclosure Of Invention

The variable is called (logic) if it has always one of the following three aspects, the false aspect (definite false) , unknown aspect (may be false or true) and the true aspect (definite true) . We could develop logic laws that are consisted of a group of the logic gates.

The previous logic laws are used to build the digital electronic circuits that are mainly consisted of a group of the logic gates. These gates will be the engineering application of the above mentioned logic operations.

There are three main gates based on the three main operations and we call them the same name: modified (AND) gate, modified (OR) gate and modified (NOT) gate which consists of four inputs and two outputs (double) described in the figures No. (1), (2) and (3) or the other which consists of four inputs and two outputs (single) described in The figures No. (15), (16) and (17) that are the symbols of the above mentioned main logic gates .

Representation of values

Like the binary logic , we can represent the values (false - may be false or true - true) digitally by using different signs of the ternary number system that depends on the power of number (3) and computing the column value by the principle of (quantum computing).

(0) = (0 0) To indicate the definite false. (Zero volt) static value

(1) = (1 0) To indicate the probability of may be false or true. (2.5 volt)

Positive value

(2) = (1 1) To indicate the definite true. (5 volt) positive value. The main logic gates of double input and single input The modified (AND) gate (. ,)

We observe the following ;

1) The output is (definite false) ( 0 0 ) on two conditions

a) Both inputs are false

b) One input is unknown and the other is true

2) The output is (unknown) ( 1 0 ) on two conditions a) Both inputs are true

b) One input is unknown and the other is false

3) The output is (definite true) (1 1) on two conditions

a) Both inputs are unknown

b) One input is false and the other is true

As described in the figure No. (1) For the double input and in the figure No. (15) For the single input

The modified (OR) gate (+,)

We observe the following:

1) The output is (definite false) (0 0) on two conditions

c) Both inputs are unknown

d) One input is false

2) The input is (unknown) (10) on two conditions

a) Both inputs are true

b) One input is unknown and the other is true

3) The output will never be (definite true) (1 1)

As described in the figure No. (2) For the double input and in the figure No. (16) For the single input

The modified (NOT) gate (-) The value is inverted from (definite false to definite true) - (definite true to definite false) - it remains (unknown aspect)

As described in the figure No.(3) for the double input and in the figure No.( 17) for the single input.

We observe the following:

If X = False & Y = false

X.,Y = False

X+,Y = False

2) If X = false & Y = unknown

X.,Y = unknown

X+,Y = False

3) If X = false & Y = true

X.,Y = true

X+,Y = False

4) If X = unknown & Y = false

X..Y = unknown

X+,Y = False

5) If X = unknown & Y = unknown

X.,Y = true

X+,Y = false

6) If X = unknown & Y = true X..Y = false

Χ+,Υ = unknown

X = true & Y false

X.,Y = true

X+,Y = false

8) If X = true & Y unknown

X.,Y = false

X+,Y = unknown

9) If X = true & Y true

X.,Y = unknown

X+,Y = unknown

The truth table of the logic gates (AND), (OR) And (NOT) as described in the figure no. (4) For the double input and in the figure no. (18) For the single input.

The derived logic gates

These gates are derived from the main logic gates which are: (NAND) modified gate CD

It is the (AND) gate connected to (NOT) gate as described in the figure (5) for the double input and in the figure no.(19) for the single input.

It works opposite of (AND) gate. (NOR) modified gate (+.)

It is the (OR) gate connected to (NOT) gate as described in the figure (6) for the double input and in the figure no.(20) for the single input.

It works opposite of (OR) gate.

(XOR) modified gate (+.)

It is a gate that gives a result of the true aspect (1 1) if its inputs are not the same while it gives a result of the false aspect (0 0) if its inputs are the same. Its mathematical symbol is a small circle including a plus sign. Its logic symbol is as follows as described in the figure (7) for the double input and in the figure no.(21 ) for the single input.

Exclusive -NOR or Equivalence modified gate (( ) ) or ((x )

It is the (XOR) gate connected to the (NOT) gate as described in the figure (8) for the double input and in the figure no.(22) for the single input.

Note that this gate gives a result (true) (1 1) if its inputs are the same while it gives a result (false) (0 0) if its inputs are not the same.

It works opposite of modified(XOR) gate.

The truth table of the logic modified gates (NAND), (NOR), (XOR) and (EQV) as described In the figure no. (9) For the double input and in the figure no.(23) for the single input. The Main Full Adder Gate

It is a group of the two logic modified gates that consists of (AND) and (OR) as it has four inputs (each input represents the three values of the ternary logic) (0 0), (1 0) and (1 1). We symbolize them by (X), (Y), (XI) and (Yl).

It also has three outputs, two outputs for the result represented by the three values of the ternary logic (0 0), (1 0) and (1 1) we symbolize them by (AD) and (ADl), the third one it has two values only of the ternary logic which are (0 0) and (1 0) symbolize as (C). If the result is (1 0) the subsidiary full adder gate works . it is of a static case and we do not need it if the result is a static value (0 0) or one of its inputs has not positive values (1 0) or (1 1) and both inputs has negative values (0 0) as described in the figure no. (10) for the double input and in the figure no.(24) for the single input.

In case of subtracting , we use (NOT) modified gate before entering the (Y) value.

The Subsidiary Full Adder Gate

It is a group of the two logic modified gates that consists of (AND) and (OR) as it has three inputs (both inputs represent the three values of the ternary logic) (0 0), (1 0) and (1 1) . We symbolize them by (X2) and (Y2) and a third input that its result comes out of the result of the output ( C) of the previous adder. It also has two outputs for the result that has a symbol (AD2) represented by the three values of the ternary logic ( 0 0), (1 0) and (1 1) and the other one has two values only of the values of the ternary logic which are ( 0 0) and (1 0) symbolize as ( CI). If the result is (1 0), the consequent subsidiary full adder gate works . it is of a static case and we do not need it if the result is (0 0) or one of its inputs have not positive values (1 0) or (1 1) and have static values (0 0) as described in the figure No. (11) for the double input and in the figure No.(25) for the single input.

In case of deduction, we use (NOT) modified gate before entering the (Yl) value.

Some rules of the logic equations:

1)

2) X.,Y = Y.,X

X+, Y = Y+, X

3)

IF X = 00 X=10 X = l 1

X.,Y =10 X.,Y = 11 X.,Y = 00

X+,Y = 00 X+,Y = 00 X+,Y = 10

SO Y = 10 Y = 10 Y = 10

IF x = oo X = 10 X = l 1

X.,Y =11 X.,Y = 00 X.,Y =10

X+,Y = 00 X+,Y = 10 X+,Y = 10

SO Y = l 1 Y = l 1 Y = l 1 /A)

IF x = oo X = 10 X = l 1

X.,Y = 00 X.,Y =10 X.,Y =11

SO Y = 00 Y = 00 Y = 00

IF x=oo X = 10 X = ll

X.,Y =10 X.,Y = 11 X.,Y = 00

SO Y = 10 Y = 10 Y = 10

IF x=oo X = 10 X = l 1

X.,Y =11 X.,Y = 00 X.,Y = 10

SO Y = l 1 Y = l 1 Y=ll)

5) X = X.,{(X,Y)+,(X+,Y)}

As described in the figure No. (12) for the double input, and in the figure No. (26) for the single input.

6) X+,Y= X+,{(X®Y).,Y}

As described in the figure No. (13) for the double input and in the figure No. (27) for the single input.

7) X+,X = 00

as described in the figure No. (14) for the binary input and in the figure No. (28) for the single input.

The tables No. (29) and (30) describe the symbols of numbers.

8) X.,X = 11

As described in the figure No. (31)

9)

As described in the figure No. (32)

10) x+,oo = oo

As described in the figure No. (33)

11) x.,oo = x

As described in the figure No. (34)

12) (X.,Y)+,(X+,Y) = 00

As described in the figure No. (35)

13) (X.,Y)+,(X+,Y) = 00

As described in the figure No. (36)

14) (Χ.,Ϋ)+,(Χ+,Ϋ) = 00

As described in the figure No. (37) 15) (Χ.,Υ)+,(Χ+,Υ) = 00

As described in the figure No. (38)

16) (X.,Y)+,(X+,Y) = 00

As described in the figure No. (39)

17) (X+,Y)+,(X+,Y) = 00

As described in the figure No. (40)

18) (X+,Y)+,(X+,Y) = 00

As described in the figure No. (41)

19) (Χ+,Ϋ)+,(Χ+,^"Ϋ) = 00

As described in the figure No. (42)

20) (X .,Y) +, (X +,Y) = 00

As described in the figure No. (43)

21) (X+,Y)+,(X+,Y) = 00

As described in the figure No. (44)

22) (X+,Y)+,(X+,Y) = 00

As described in the figure No. (45)

Note that all logic equations are equal from the rule No. (12) to the rule No. (22).

23) X +, Y ? 11

All rules of the double input are applied on the single input.

Transferring the decimal numbers to the ternary system

When the result is 0 = (00)

When the result is 1 = (10)

When the result is 2 = (11)

81 27

125 125/3= 4 2 remain 1

1

41/3= 13 2 remain 1

1

13/3=4 1 remain 0

1

4/3= 1 1 remain 0

1

1 = 0

1

243 81 27

1 0 0 0 0 0 1 1 1 1 0 0

267

267/3=89 0 remain 0

0

89/3=29 2 remain 1

1

29/3=9 2 remain 1

1

9/3=3 0 remain 0

0

3/3=1 0 remain 0

0

1= 0

1 1 0 0 0

3

3/3=1 0 remain 0

0

1= 0

1

The addition:

81 27 9 3 1

10 10 10 00 Carry

00 10 11 10 00 48

00 11 11 11 10 79

10 10 11 00 10 127

The subtracting:

81 27 9 3 1

00 00 00 00 Carry

10 10 11 10 10 130

OO^l^l^l D 79

00 00 00 00 10

00 00 00 10 Carry 10 10 11 10 11

00 00 00 00 10 10 Add

4) Brief description of the drawing

How the main and subsidiary full adder gate operate :

When we add and the final carry is a static value (00): When we add two values e.g. adding : 45 + 30

30 45

00= 0 remain 10 = 3/30 00 = 0 remain 15 = 3 /45 10= 0 remain 3 = 3/10 00 = 0 remain 5 = 3/15 00= 0 remain 1 = 3/3 11 = 2 remain 1 = 3/5

10 = 10 =

X3 X2 XI X

10 11 00 00 45

Y3 Y2 Yl Y

00 10 10 00 30

When we enter the data (The value symbol), will need automatically a main full adder gate for data processing of X , XI with Y , Yl, and two subsidiary full adder gates, for data processing. One for data processing of X2 , Y2 and the other for data processing of X3 , Y3.

{Because the entered data require that. It will by the higher number of the entered bits (Khana) from X or Y} .

We note that the carries are static ones C, CI, C2 = (00). Here we are interested in the final carry (C3) which is a static value (00) so it will not operate a third subsidiary full adder gate as the carry is static. Moreover, there is no positive symbol for the added subsidiary full adder gate.

C3 C2 CI C

00 00 00 00 Carry

00 10 11 00 00 45 00 10 00 10 00 30

11 11 10 00 75

When we add and the final carry is a positive value (10);

When we add two values e.g. adding of : 60 + 45 = 105

45 60

00= 0 remain 15 = 3/45 00 = 0 remain 20 = 3 /60

00= 0 remain 5 = 3/15 11 = 2 remain 6 = 3/20

11 = 2 remain 1 = 3/5 00 = 0 remain 2 = 3/6

10= 1 11 = 2

X3 X2 XI X

11 00 11 00 60

Y3 Y2 Yl Y

10 11 00 00 45

When we enter the data (The value symbol), we need automatically a main full adder gate for data processing of X , XI with Y , Yl, and two subsidiary full adder gates, for data processing. One for data processing of X2 , Y2 and the other for data processing of X3 , Y3

{Because the entered data require that. It will by the higher number of the entered bits (Khana) from X or Y}

We note that the carries are static ones C, CI and C2 = (00) except (C3). Here, we are interested in the final carry (C3) which is a positive value (1 0), so it will operate a third subsidiary full adder gate as the carry is a positive. However, there is no positive symbol for the added subsidiary full adder gate, and the result is a carry (C4). (C4) is subject to what is applied on (C3) in the above mentioned example as such.

C4 C3^C2 CI C

00 100000 00 Carry 00 0011001100 60 00 0010100000 45

1000101100 105

Within the addition operation, we note that we only need one bit (Khana) to be added the higher number of the entered bits (Khana) from X or Y} in all cases.

The subtracting:

The same method of Boolean logic which is as the following:

The subtracting operation is an addition operation between (X) and (Y). Then we add (1 0) to the total. When we subtract two values e.g. deduction of : 60 - 45 = 15

45 60

00 = 0 remain 15 = 3/45 00 = 0 remain 20 = 3 /60

00 = 0 remain 5 = 3/15 11 = 2 remain 6 = 3/20

11 = 2 remain 1 = 3/5 00 = 0 remain 2 = 3/6

10 = 1 1 2 X3 X2 XI X

1 0 1 1 0 0 0 0 45

Y3 Y2 Yl Y

0 0 1 0 1 0 0 0 30

When we enter the data (The value symbol), a modified (NOT) logic gate will be before all the (Y) symbol values. We need automatically a main full adder gate for data processing of X , XI with Y , Yl and two subsidiary full adder gates for data processing. One for data processing of X2 , Y2 and the other for data processing of X3,Y3.

Then we perform the addition operation. Here , we are interested in the final carry (C3) which is a positive value, so it will operate a third subsidiary full adder gate as the carry is positive. However, there is no positive symbol for the added subsidiary full adder gate and the result will add (1 0) to it then the final result is shown after ignoring the last bit (Khana).

60 - 45 = 15

C3 C2 CI C

10 00 10 00 Carry

00 1 1 00 1 1 00 60

00 10 00 1 1 1 1

00 00 00 10 Carry

10 00 10 10 1 1

00 00 00 00 10 10 Adding

J-0 00 10 1 1 00 15

Within the subtracting operation, we note that the final result will be the same number of bits (Khana) in all cases.

Claims

5) Claims

1) Magdi's logic (Ternary logic).

2) Logic of reading from the right to the left to build the electronic circuits.

3) The logic variables {( definite false) (0 0) (zero volt)}, {(may be false or true)

(1 0) (2.5 volt)} and {( definite true) (1 1) (5 volt)}

4) The modified logic gates of the ternary values (Double and single input)

(AND), (OR), (NOT), (XOR), (NAND), (NOR) and (EQV).

5) The main full adder gate (Double and single input)

6) The subsidiary full adder gate (Double and single input)