ATE478475T1 - Breitbandfrequenz-synthesizer mit eliminierung von parasitären niederfrequenzemissionen - Google Patents

Breitbandfrequenz-synthesizer mit eliminierung von parasitären niederfrequenzemissionen

Info

Publication number
ATE478475T1
ATE478475T1 AT07820882T AT07820882T ATE478475T1 AT E478475 T1 ATE478475 T1 AT E478475T1 AT 07820882 T AT07820882 T AT 07820882T AT 07820882 T AT07820882 T AT 07820882T AT E478475 T1 ATE478475 T1 AT E478475T1
Authority
AT
Austria
Prior art keywords
frequency
factors
output signal
elimination
emissions
Prior art date
Application number
AT07820882T
Other languages
English (en)
Inventor
Arnaud Casagrande
Original Assignee
Swatch Group Res & Dev Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Swatch Group Res & Dev Ltd filed Critical Swatch Group Res & Dev Ltd
Application granted granted Critical
Publication of ATE478475T1 publication Critical patent/ATE478475T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
AT07820882T 2006-10-16 2007-10-03 Breitbandfrequenz-synthesizer mit eliminierung von parasitären niederfrequenzemissionen ATE478475T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06122367A EP1914893A1 (de) 2006-10-16 2006-10-16 Breitbandiger Frequenzsynthesiser mit Niederfrequenzstörsignalunterdrückung
PCT/EP2007/060505 WO2008046741A1 (fr) 2006-10-16 2007-10-03 Synthetiseur de frequence a large bande a suppression d'emissions parasites basses frequences

Publications (1)

Publication Number Publication Date
ATE478475T1 true ATE478475T1 (de) 2010-09-15

Family

ID=37814257

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07820882T ATE478475T1 (de) 2006-10-16 2007-10-03 Breitbandfrequenz-synthesizer mit eliminierung von parasitären niederfrequenzemissionen

Country Status (10)

Country Link
US (1) US7928805B2 (de)
EP (2) EP1914893A1 (de)
JP (1) JP4833340B2 (de)
KR (1) KR101251708B1 (de)
CN (1) CN101529725B (de)
AT (1) ATE478475T1 (de)
DE (1) DE602007008599D1 (de)
HK (1) HK1137865A1 (de)
TW (1) TWI439055B (de)
WO (1) WO2008046741A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101277496B (zh) * 2008-05-12 2012-06-06 中兴通讯股份有限公司 一种双卡双模手机
TWI528725B (zh) 2013-05-06 2016-04-01 國立中山大學 寬頻頻率合成器及其頻率合成方法
JP6439915B2 (ja) 2014-09-12 2018-12-19 セイコーエプソン株式会社 フラクショナルｎ−ｐｌｌ回路、発振器、電子機器及び移動体

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2834923B2 (ja) * 1991-11-26 1998-12-14 三洋電機株式会社 位相ロックループ及びこれを用いたインタフェース回路
CA2267496C (en) * 1998-03-31 2003-03-11 Philsar Electronics Inc. A fractional-n divider using a delta-sigma modulator
CA2233831A1 (en) * 1998-03-31 1999-09-30 Tom Riley Digital-sigma fractional-n synthesizer
JP3556917B2 (ja) * 2001-03-23 2004-08-25 三菱電機株式会社 周波数シンセサイザ
JP3548557B2 (ja) * 2001-10-02 2004-07-28 Ｎｅｃ化合物デバイス株式会社 フラクショナルｎ周波数シンセサイザ
EP1300950A1 (de) 2001-10-05 2003-04-09 Asulab S.A. Dual Modulus Zähler/Teiler mit Phasenauswahl für einen Frequenzsynthesizer
US7231196B2 (en) * 2001-12-12 2007-06-12 Broadcom Corporation Method and apparatus for fractional-N synthesis
KR100468734B1 (ko) 2002-06-11 2005-01-29 삼성전자주식회사 노이즈를 감소시키기 위한 주파수 합성 회로
JP2005033581A (ja) * 2003-07-07 2005-02-03 Mitsubishi Electric Corp フラクショナル−ｎ方式の位相同期ループ形周波数シンセサイザ

Also Published As

Publication number Publication date
TWI439055B (zh) 2014-05-21
JP4833340B2 (ja) 2011-12-07
TW200838149A (en) 2008-09-16
KR101251708B1 (ko) 2013-04-05
US7928805B2 (en) 2011-04-19
DE602007008599D1 (de) 2010-09-30
CN101529725B (zh) 2012-10-03
US20100295624A1 (en) 2010-11-25
WO2008046741A1 (fr) 2008-04-24
KR20090067157A (ko) 2009-06-24
EP2080269A1 (de) 2009-07-22
CN101529725A (zh) 2009-09-09
HK1137865A1 (en) 2010-08-06
EP2080269B1 (de) 2010-08-18
JP2010521075A (ja) 2010-06-17
EP1914893A1 (de) 2008-04-23

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