ATE554530T1 - Hochkonfigurierbare phasenregelschleifestruktur für einen programmierbaren logischen baustein - Google Patents
Hochkonfigurierbare phasenregelschleifestruktur für einen programmierbaren logischen bausteinInfo
- Publication number
- ATE554530T1 ATE554530T1 AT05251420T AT05251420T ATE554530T1 AT E554530 T1 ATE554530 T1 AT E554530T1 AT 05251420 T AT05251420 T AT 05251420T AT 05251420 T AT05251420 T AT 05251420T AT E554530 T1 ATE554530 T1 AT E554530T1
- Authority
- AT
- Austria
- Prior art keywords
- programmable
- clock
- locked loop
- logical unit
- loop structure
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
- H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/797,836 US7098707B2 (en) | 2004-03-09 | 2004-03-09 | Highly configurable PLL architecture for programmable logic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE554530T1 true ATE554530T1 (de) | 2012-05-15 |
Family
ID=34827644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT05251420T ATE554530T1 (de) | 2004-03-09 | 2005-03-09 | Hochkonfigurierbare phasenregelschleifestruktur für einen programmierbaren logischen baustein |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US7098707B2 (de) |
| EP (1) | EP1575170B1 (de) |
| JP (1) | JP2005269635A (de) |
| CN (2) | CN101860366A (de) |
| AT (1) | ATE554530T1 (de) |
Families Citing this family (78)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7242229B1 (en) | 2001-05-06 | 2007-07-10 | Altera Corporation | Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode |
| US7200769B1 (en) | 2001-08-29 | 2007-04-03 | Altera Corporation | Self-compensating delay chain for multiple-date-rate interfaces |
| US7425841B2 (en) | 2004-02-14 | 2008-09-16 | Tabula Inc. | Configurable circuits, IC's, and systems |
| US7167025B1 (en) | 2004-02-14 | 2007-01-23 | Herman Schmit | Non-sequentially configurable IC |
| US20050186920A1 (en) * | 2004-02-19 | 2005-08-25 | Texas Instruments Incorporated | Apparatus for and method of noise suppression and dithering to improve resolution quality in a digital RF processor |
| US7234069B1 (en) | 2004-03-12 | 2007-06-19 | Altera Corporation | Precise phase shifting using a DLL controlled, multi-stage delay chain |
| US7126399B1 (en) | 2004-05-27 | 2006-10-24 | Altera Corporation | Memory interface phase-shift circuitry to support multiple frequency ranges |
| US7224181B1 (en) * | 2004-11-08 | 2007-05-29 | Herman Schmit | Clock distribution in a configurable IC |
| US7330050B2 (en) * | 2004-11-08 | 2008-02-12 | Tabula, Inc. | Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements |
| US7317331B2 (en) | 2004-11-08 | 2008-01-08 | Tabula, Inc. | Reconfigurable IC that has sections running at different reconfiguration rates |
| US7342415B2 (en) | 2004-11-08 | 2008-03-11 | Tabula, Inc. | Configurable IC with interconnect circuits that also perform storage operations |
| US7268586B1 (en) | 2004-11-08 | 2007-09-11 | Tabula, Inc. | Method and apparatus for accessing stored data in a reconfigurable IC |
| US7276933B1 (en) | 2004-11-08 | 2007-10-02 | Tabula, Inc. | Reconfigurable IC that has sections running at different looperness |
| US20060109940A1 (en) * | 2004-11-22 | 2006-05-25 | Troy Beukema | Timing bias compensation for a data receiver with decision-feedback equalizer |
| US7236009B1 (en) | 2004-12-01 | 2007-06-26 | Andre Rohe | Operational time extension |
| US7199607B2 (en) * | 2004-12-22 | 2007-04-03 | Infineon Technologies Ag | Pin multiplexing |
| US7826579B2 (en) * | 2005-02-11 | 2010-11-02 | International Business Machines Corporation | Method and apparatus for generating synchronization signals for synchronizing multiple chips in a system |
| US7230869B1 (en) | 2005-03-15 | 2007-06-12 | Jason Redgrave | Method and apparatus for accessing contents of memory cells |
| US7826519B1 (en) * | 2005-05-23 | 2010-11-02 | Marvell International, Ltd | Method and apparatus for providing coherent phase noise in transceivers or similar systems |
| TWI300653B (en) * | 2005-06-22 | 2008-09-01 | Ind Tech Res Inst | Clock generator and phase locked loop and clock generation method using the same |
| US7414429B1 (en) | 2005-07-19 | 2008-08-19 | Altera Corporation | Integration of high-speed serial interface circuitry into programmable logic device architectures |
| US7304498B2 (en) * | 2005-07-20 | 2007-12-04 | Altera Corporation | Clock circuitry for programmable logic devices |
| US8189729B2 (en) * | 2005-08-03 | 2012-05-29 | Altera Corporation | Wide range and dynamically reconfigurable clock data recovery architecture |
| US7812659B1 (en) | 2005-08-03 | 2010-10-12 | Altera Corporation | Clock signal circuitry for multi-channel data signaling |
| CN1953332B (zh) * | 2005-10-17 | 2011-01-12 | 联芯科技有限公司 | 时钟发生器和使用该时钟发生器的通信终端 |
| US7372297B1 (en) | 2005-11-07 | 2008-05-13 | Tabula Inc. | Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources |
| US7461362B1 (en) | 2005-12-01 | 2008-12-02 | Tabula, Inc. | Replacing circuit design elements with their equivalents |
| US7679401B1 (en) | 2005-12-01 | 2010-03-16 | Tabula, Inc. | User registers implemented with routing circuits in a configurable IC |
| US7489162B1 (en) | 2005-12-01 | 2009-02-10 | Tabula, Inc. | Users registers in a reconfigurable IC |
| US7539278B2 (en) * | 2005-12-02 | 2009-05-26 | Altera Corporation | Programmable transceivers that are able to operate over wide frequency ranges |
| GB2435725A (en) * | 2006-03-03 | 2007-09-05 | Toumaz Technology Ltd | Frequency generation circuit |
| US7529992B1 (en) | 2006-03-27 | 2009-05-05 | Tabula, Inc. | Configurable integrated circuit with error correcting circuitry |
| US7669097B1 (en) | 2006-03-27 | 2010-02-23 | Tabula, Inc. | Configurable IC with error detection and correction circuitry |
| TW200805373A (en) * | 2006-05-19 | 2008-01-16 | Samsung Electronics Co Ltd | A multi-port semiconductor device and method thereof |
| JP4807222B2 (ja) * | 2006-10-27 | 2011-11-02 | パナソニック株式会社 | Lvds受信方法および受信装置 |
| JP2008147499A (ja) * | 2006-12-12 | 2008-06-26 | Fujitsu Ltd | プリント基板 |
| US7495517B1 (en) | 2006-12-14 | 2009-02-24 | Altera Corporation | Techniques for dynamically adjusting the frequency range of phase-locked loops |
| US7619451B1 (en) * | 2007-02-03 | 2009-11-17 | Altera Corporation | Techniques for compensating delays in clock signals on integrated circuits |
| WO2008115243A2 (en) | 2007-03-20 | 2008-09-25 | Tabula, Inc. | Configurable ic having a routing fabric with storage elements |
| US8112468B1 (en) | 2007-03-22 | 2012-02-07 | Tabula, Inc. | Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC |
| US7814301B2 (en) * | 2007-04-11 | 2010-10-12 | Hewlett-Packard Development Company, L.P. | Clock architecture for multi-processor systems |
| US7821312B1 (en) | 2007-04-18 | 2010-10-26 | Altera Corporation | Techniques for selecting phases of clock signals |
| US7532029B1 (en) | 2007-04-18 | 2009-05-12 | Altera Corporation | Techniques for reconfiguring programmable circuit blocks |
| US8344755B2 (en) | 2007-09-06 | 2013-01-01 | Tabula, Inc. | Configuration context switcher |
| US7940132B2 (en) * | 2007-09-27 | 2011-05-10 | Freescale Semiconductor, Inc. | Clock system and applications thereof |
| US8863067B1 (en) | 2008-02-06 | 2014-10-14 | Tabula, Inc. | Sequential delay analysis by placement engines |
| US8130044B2 (en) * | 2008-06-19 | 2012-03-06 | Altera Corporation | Phase-locked loop circuitry with multiple voltage-controlled oscillators |
| US8166435B2 (en) | 2008-06-26 | 2012-04-24 | Tabula, Inc. | Timing operations in an IC with configurable circuits |
| US7928782B2 (en) * | 2009-01-28 | 2011-04-19 | Micron Technology, Inc. | Digital locked loops and methods with configurable operating parameters |
| US8228102B1 (en) | 2010-03-03 | 2012-07-24 | Altera Corporation | Phase-locked loop architecture and clock distribution system |
| US8406258B1 (en) * | 2010-04-01 | 2013-03-26 | Altera Corporation | Apparatus and methods for low-jitter transceiver clocking |
| US8996906B1 (en) | 2010-05-13 | 2015-03-31 | Tabula, Inc. | Clock management block |
| US8279761B2 (en) * | 2010-05-28 | 2012-10-02 | Altera Corporation | Input/output interface for periodic signals |
| US8686776B2 (en) * | 2012-07-24 | 2014-04-01 | International Business Machines Corporation | Phase rotator based on voltage referencing |
| HK1217546A1 (zh) | 2012-09-07 | 2017-01-13 | 弗吉尼亚大学专利基金会以弗吉尼亚大学许可&合资集团名义经营 | 低功率時鐘源 |
| CN103077694B (zh) * | 2012-12-20 | 2014-12-24 | 广州视源电子科技股份有限公司 | 用于去除lvds信号的展频的系统及方法 |
| US9000801B1 (en) | 2013-02-27 | 2015-04-07 | Tabula, Inc. | Implementation of related clocks |
| US9450589B2 (en) | 2013-06-28 | 2016-09-20 | Intel Corporation | Clock generation system with dynamic distribution bypass mode |
| US9225322B2 (en) | 2013-12-17 | 2015-12-29 | Micron Technology, Inc. | Apparatuses and methods for providing clock signals |
| US9413364B2 (en) * | 2014-07-09 | 2016-08-09 | Intel Corporation | Apparatus and method for clock synchronization for inter-die synchronized data transfer |
| US9819345B2 (en) * | 2014-10-02 | 2017-11-14 | Altera Corporation | Scalable 2.5D interface architecture |
| US20160105274A1 (en) * | 2014-10-14 | 2016-04-14 | Gain Ics Llc | Wireless network throughput system and method |
| CN104518789A (zh) * | 2014-12-30 | 2015-04-15 | 西安奇维科技股份有限公司 | 一种高精度数字频率脉冲输出的方法 |
| CN106294224B (zh) * | 2015-05-13 | 2019-10-25 | 瑞昱半导体股份有限公司 | 存储器系统及其存储器实体接口电路 |
| CN106356021B (zh) * | 2015-07-14 | 2020-02-14 | 西安诺瓦星云科技股份有限公司 | 降低led显示屏电磁干扰的方法和led显示控制卡 |
| JP6917168B2 (ja) * | 2016-04-01 | 2021-08-11 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| US11255909B2 (en) | 2016-05-30 | 2022-02-22 | Dspace Digital Signal Processing And Control Engineering Gmbh | Method for synchronizing a checking apparatus, and a checking apparatus and a composite system comprising at least two checking apparatuses |
| DE102016006361A1 (de) | 2016-05-30 | 2017-11-30 | Dspace Digital Signal Processing And Control Engineering Gmbh | Überprüfungsvorrichtung |
| US10305495B2 (en) * | 2016-10-06 | 2019-05-28 | Analog Devices, Inc. | Phase control of clock signal based on feedback |
| CN106444964A (zh) * | 2016-10-08 | 2017-02-22 | 郑州云海信息技术有限公司 | 一种用于fpga的时钟系统及服务器 |
| CN107222207A (zh) * | 2017-06-05 | 2017-09-29 | 中国电子科技集团公司第四十研究所 | 一种1Hz‑1GHz时钟产生电路及方法 |
| US10832716B2 (en) * | 2018-12-19 | 2020-11-10 | Marvell Asia Pte, Ltd. | Zone self servo writing with synchronized parallel clocks |
| CN111371455B (zh) * | 2019-12-31 | 2024-04-12 | 京微齐力(北京)科技有限公司 | 一种用于pll输出频率动态切换的系统 |
| CN112084733B (zh) * | 2020-08-14 | 2024-06-21 | 深圳天狼芯半导体有限公司 | 芯片的时钟树布图方法及装置 |
| MY204260A (en) * | 2020-12-18 | 2024-08-19 | Skyechip Sdn Bhd | A clocking system and a method of clock synchronization |
| CN112799329B (zh) * | 2021-01-15 | 2022-03-04 | 珠海一微半导体股份有限公司 | 分时钟访问sram的控制系统及异构soc芯片 |
| US12353238B2 (en) * | 2021-09-24 | 2025-07-08 | Intel Corporation | Flexible instruction set architecture supporting varying frequencies |
| CN116015279A (zh) * | 2023-01-17 | 2023-04-25 | 深圳市紫光同创电子有限公司 | 可编程逻辑器件的时钟配置方法、装置、设备及介质 |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3473160A (en) | 1966-10-10 | 1969-10-14 | Stanford Research Inst | Electronically controlled microelectronic cellular logic array |
| US4789996A (en) * | 1988-01-28 | 1988-12-06 | Siemens Transmission Systems, Inc. | Center frequency high resolution digital phase-lock loop circuit |
| US5212723A (en) * | 1991-08-08 | 1993-05-18 | Macrovision Corp. | Burst phase correction system for video descrambling |
| US5689195A (en) | 1995-05-17 | 1997-11-18 | Altera Corporation | Programmable logic array integrated circuit devices |
| US5539351A (en) * | 1994-11-03 | 1996-07-23 | Gilsdorf; Ben | Circuit and method for reducing a gate volage of a transmission gate within a charge pump circuit |
| US5550515A (en) * | 1995-01-27 | 1996-08-27 | Opti, Inc. | Multiphase clock synthesizer having a plurality of phase shifted inputs to a plurality of phase comparators in a phase locked loop |
| US5909126A (en) | 1995-05-17 | 1999-06-01 | Altera Corporation | Programmable logic array integrated circuit devices with interleaved logic array blocks |
| JPH10124167A (ja) | 1996-10-17 | 1998-05-15 | Miyagi Oki Denki Kk | システムクロック切り換え装置 |
| US6081141A (en) * | 1997-11-26 | 2000-06-27 | Intel Corporation | Hierarchical clock frequency domains for a semiconductor device |
| US5986512A (en) * | 1997-12-12 | 1999-11-16 | Telefonaktiebolaget L M Ericsson (Publ) | Σ-Δ modulator-controlled phase-locked-loop circuit |
| TW406219B (en) * | 1998-08-26 | 2000-09-21 | Via Tech Inc | PLL clock generation circuit that is capable of programming frequency and skew |
| US6114915A (en) | 1998-11-05 | 2000-09-05 | Altera Corporation | Programmable wide-range frequency synthesizer |
| US6215326B1 (en) | 1998-11-18 | 2001-04-10 | Altera Corporation | Programmable logic device architecture with super-regions having logic regions and a memory region |
| JP4077979B2 (ja) | 1999-05-27 | 2008-04-23 | 株式会社日立製作所 | 半導体集積回路装置 |
| US6580288B1 (en) * | 1999-09-09 | 2003-06-17 | International Business Machines Corporation | Multi-property microprocessor with no additional logic overhead to shared pins |
| US6392462B2 (en) | 2000-04-04 | 2002-05-21 | Matsushita Electric Industrial Co., Ltd. | Multiphase clock generator and selector circuit |
| US6665762B2 (en) * | 2001-01-03 | 2003-12-16 | Force Computers, Inc. | Computer having a plurality of plug-in cards |
| JP3532861B2 (ja) * | 2001-02-06 | 2004-05-31 | 松下電器産業株式会社 | Pll回路 |
| US6856180B1 (en) | 2001-05-06 | 2005-02-15 | Altera Corporation | Programmable loop bandwidth in phase locked loop (PLL) circuit |
| US6686805B2 (en) | 2001-05-25 | 2004-02-03 | Infineon Technologies Ag | Ultra low jitter clock generation device and method for storage drive and radio frequency systems |
| US6720810B1 (en) * | 2002-06-14 | 2004-04-13 | Xilinx, Inc. | Dual-edge-correcting clock synchronization circuit |
| US6864752B2 (en) * | 2002-11-01 | 2005-03-08 | Broadcom Corporation | Configurable voltage controlled oscillator system and method |
| US7242740B2 (en) * | 2003-04-16 | 2007-07-10 | Zarlink Semiconductor Inc. | Digital phase-locked loop with master-slave modes |
| JP4064338B2 (ja) * | 2003-12-10 | 2008-03-19 | 松下電器産業株式会社 | デルタシグマ型分数分周pllシンセサイザ |
-
2004
- 2004-03-09 US US10/797,836 patent/US7098707B2/en not_active Expired - Lifetime
-
2005
- 2005-03-08 JP JP2005064686A patent/JP2005269635A/ja active Pending
- 2005-03-09 CN CN201010164031A patent/CN101860366A/zh active Pending
- 2005-03-09 AT AT05251420T patent/ATE554530T1/de active
- 2005-03-09 CN CN2005100627413A patent/CN1667957B/zh not_active Expired - Fee Related
- 2005-03-09 EP EP05251420A patent/EP1575170B1/de not_active Expired - Lifetime
-
2006
- 2006-07-13 US US11/486,565 patent/US7276943B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1667957B (zh) | 2010-12-08 |
| EP1575170B1 (de) | 2012-04-18 |
| CN1667957A (zh) | 2005-09-14 |
| US20060250168A1 (en) | 2006-11-09 |
| JP2005269635A (ja) | 2005-09-29 |
| CN101860366A (zh) | 2010-10-13 |
| US7276943B2 (en) | 2007-10-02 |
| EP1575170A1 (de) | 2005-09-14 |
| US20050200390A1 (en) | 2005-09-15 |
| US7098707B2 (en) | 2006-08-29 |
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