ATE35067T1 - Kleinflaechiger duennfilmtransistor. - Google Patents

Kleinflaechiger duennfilmtransistor.

Info

Publication number
ATE35067T1
ATE35067T1 AT84113428T AT84113428T ATE35067T1 AT E35067 T1 ATE35067 T1 AT E35067T1 AT 84113428 T AT84113428 T AT 84113428T AT 84113428 T AT84113428 T AT 84113428T AT E35067 T1 ATE35067 T1 AT E35067T1
Authority
AT
Austria
Prior art keywords
layer
coplanar surface
thin film
small area
source
Prior art date
Application number
AT84113428T
Other languages
English (en)
Inventor
Meera Vijan
Original Assignee
Energy Conversion Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Energy Conversion Devices Inc filed Critical Energy Conversion Devices Inc
Application granted granted Critical
Publication of ATE35067T1 publication Critical patent/ATE35067T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/694—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks or redeposited masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask

Landscapes

  • Thin Film Transistor (AREA)
  • Drying Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
AT84113428T 1983-11-08 1984-11-07 Kleinflaechiger duennfilmtransistor. ATE35067T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/549,991 US4543320A (en) 1983-11-08 1983-11-08 Method of making a high performance, small area thin film transistor
EP84113428A EP0141425B1 (de) 1983-11-08 1984-11-07 Kleinflächiger Dünnfilmtransistor

Publications (1)

Publication Number Publication Date
ATE35067T1 true ATE35067T1 (de) 1988-06-15

Family

ID=24195275

Family Applications (1)

Application Number Title Priority Date Filing Date
AT84113428T ATE35067T1 (de) 1983-11-08 1984-11-07 Kleinflaechiger duennfilmtransistor.

Country Status (6)

Country Link
US (1) US4543320A (de)
EP (1) EP0141425B1 (de)
JP (1) JPS60116135A (de)
AT (1) ATE35067T1 (de)
CA (1) CA1228180A (de)
DE (1) DE3472036D1 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60186066A (ja) * 1984-03-05 1985-09-21 Semiconductor Energy Lab Co Ltd 絶縁ゲイト型電界効果半導体装置およびその作製方法
US4620207A (en) * 1984-12-19 1986-10-28 Eaton Corporation Edge channel FET
US4701996A (en) * 1984-12-19 1987-10-27 Calviello Joseph A Method for fabricating edge channel FET
US4642665A (en) * 1984-12-19 1987-02-10 Eaton Corporation Vertically layered MOMOM tunnel device
FR2577715B1 (fr) * 1985-02-19 1987-03-20 Thomson Csf Procede de realisation de deux structures mos a dielectriques juxtaposes differents et dopages differents et matrice a transfert de trame obtenue par ce procede
FR2586859B1 (fr) * 1985-08-27 1987-11-20 Thomson Csf Procede de fabrication d'un transistor de commande pour ecran plat de visualisation et element de commande realise selon ce procede
US4826754A (en) * 1987-04-27 1989-05-02 Microelectronics Center Of North Carolina Method for anisotropically hardening a protective coating for integrated circuit manufacture
US5064748A (en) * 1987-04-27 1991-11-12 Mcnc Method for anisotropically hardening a protective coating for integrated circuit manufacture
JPH0283941A (ja) * 1988-09-21 1990-03-26 Fuji Xerox Co Ltd 薄膜トランジスタの製造方法
US5130263A (en) * 1990-04-17 1992-07-14 General Electric Company Method for photolithographically forming a selfaligned mask using back-side exposure and a non-specular reflecting layer
US5356485A (en) * 1992-04-29 1994-10-18 The United States Of America As Represented By The Secretary Of Commerce Intermetallic thermocouples
TW435820U (en) * 1993-01-18 2001-05-16 Semiconductor Energy Lab MIS semiconductor device
US5452166A (en) * 1993-10-01 1995-09-19 Applied Magnetics Corporation Thin film magnetic recording head for minimizing undershoots and a method for manufacturing the same
JP2003508807A (ja) * 1999-08-31 2003-03-04 イー−インク コーポレイション 電子的に駆動されるディスプレイ用トランジスタ
EP1498957A1 (de) * 2003-07-14 2005-01-19 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Feldeffekttransistor und Verfahren zum Herstellen eines Feldeffekttransistors
US7629633B2 (en) * 2004-05-20 2009-12-08 Isaac Wing Tak Chan Vertical thin film transistor with short-channel effect suppression
US20050258427A1 (en) * 2004-05-20 2005-11-24 Chan Isaac W T Vertical thin film transistor electronics
US20070190133A1 (en) * 2004-10-27 2007-08-16 Bunick Frank J Dosage forms having a microreliefed surface and methods and apparatus for their production
US20070281022A1 (en) * 2004-10-27 2007-12-06 Bunick Frank J Dosage forms having a microreliefed surface and methods and apparatus for their production
US20060088587A1 (en) * 2004-10-27 2006-04-27 Bunick Frank J Dosage forms having a microreliefed surface and methods and apparatus for their production
US20060088586A1 (en) * 2004-10-27 2006-04-27 Bunick Frank J Dosage forms having a microreliefed surface and methods and apparatus for their production
US20060088593A1 (en) * 2004-10-27 2006-04-27 Bunick Frank J Dosage forms having a microreliefed surface and methods and apparatus for their production
US8383159B2 (en) * 2004-10-27 2013-02-26 Mcneil-Ppc, Inc. Dosage forms having a microreliefed surface and methods and apparatus for their production
US20060087051A1 (en) * 2004-10-27 2006-04-27 Bunick Frank J Dosage forms having a microreliefed surface and methods and apparatus for their production
KR20140021914A (ko) * 2012-08-13 2014-02-21 삼성전기주식회사 인쇄회로기판 제조 방법
US9472649B1 (en) 2015-12-09 2016-10-18 The United States Of America As Represented By The Secretary Of The Air Force Fabrication method for multi-zoned and short channel thin film transistors
JP2017139295A (ja) * 2016-02-02 2017-08-10 東芝メモリ株式会社 基板処理装置、基板処理方法、および基板処理液
CN105932066A (zh) 2016-06-07 2016-09-07 深圳市华星光电技术有限公司 金属氧化物薄膜晶体管及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3669661A (en) * 1970-03-06 1972-06-13 Westinghouse Electric Corp Method of producing thin film transistors
DE2117199C3 (de) * 1971-04-08 1974-08-22 Philips Patentverwaltung Gmbh, 2000 Hamburg Verfahren zur Herstellung geätzter Muster in dünnen Schichten mit definierten Kantenprofilen
GB2052853A (en) * 1979-06-29 1981-01-28 Ibm Vertical fet on an insulating substrate
DE3051063C2 (de) * 1979-12-13 1991-04-11 Energy Conversion Devices, Inc., Troy, Mich., Us

Also Published As

Publication number Publication date
DE3472036D1 (en) 1988-07-14
EP0141425A1 (de) 1985-05-15
EP0141425B1 (de) 1988-06-08
CA1228180A (en) 1987-10-13
US4543320A (en) 1985-09-24
JPS60116135A (ja) 1985-06-22

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties