ATE158423T1 - Speicherzugriffsausnahmebehandlung bei vorausgelesenen befehlswörtern in dem befehlsfliessband eines rechners mit virtuellem speicher - Google Patents

Speicherzugriffsausnahmebehandlung bei vorausgelesenen befehlswörtern in dem befehlsfliessband eines rechners mit virtuellem speicher

Info

Publication number
ATE158423T1
ATE158423T1 AT90301002T AT90301002T ATE158423T1 AT E158423 T1 ATE158423 T1 AT E158423T1 AT 90301002 T AT90301002 T AT 90301002T AT 90301002 T AT90301002 T AT 90301002T AT E158423 T1 ATE158423 T1 AT E158423T1
Authority
AT
Austria
Prior art keywords
instruction
pipeline
fault information
memory access
memory
Prior art date
Application number
AT90301002T
Other languages
English (en)
Inventor
Ricky C Hetherington
David A Webb Jr
David B Fite
Francis X Mckeen
Mark A Firstenberg
John E Murray
Dwight P Manley
Ronald M Salett
Tryggve Fossum
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE158423T1 publication Critical patent/ATE158423T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766Error or fault reporting or storing
    • G06F11/0772Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
AT90301002T 1989-02-03 1990-01-31 Speicherzugriffsausnahmebehandlung bei vorausgelesenen befehlswörtern in dem befehlsfliessband eines rechners mit virtuellem speicher ATE158423T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/306,866 US4985825A (en) 1989-02-03 1989-02-03 System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer

Publications (1)

Publication Number Publication Date
ATE158423T1 true ATE158423T1 (de) 1997-10-15

Family

ID=23187213

Family Applications (1)

Application Number Title Priority Date Filing Date
AT90301002T ATE158423T1 (de) 1989-02-03 1990-01-31 Speicherzugriffsausnahmebehandlung bei vorausgelesenen befehlswörtern in dem befehlsfliessband eines rechners mit virtuellem speicher

Country Status (7)

Country Link
US (1) US4985825A (de)
EP (1) EP0381470B1 (de)
JP (1) JPH02234248A (de)
AT (1) ATE158423T1 (de)
AU (1) AU631420B2 (de)
CA (1) CA1323701C (de)
DE (1) DE69031433T2 (de)

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Also Published As

Publication number Publication date
DE69031433T2 (de) 1998-04-16
EP0381470B1 (de) 1997-09-17
JPH02234248A (ja) 1990-09-17
EP0381470A3 (de) 1992-11-19
EP0381470A2 (de) 1990-08-08
AU631420B2 (en) 1992-11-26
CA1323701C (en) 1993-10-26
DE69031433D1 (de) 1997-10-23
AU5394390A (en) 1991-12-19
JPH0526219B2 (de) 1993-04-15
US4985825A (en) 1991-01-15

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