GB2302190A - Data cache - Google Patents

Data cache

Info

Publication number
GB2302190A
GB2302190A GB9621867A GB9621867A GB2302190A GB 2302190 A GB2302190 A GB 2302190A GB 9621867 A GB9621867 A GB 9621867A GB 9621867 A GB9621867 A GB 9621867A GB 2302190 A GB2302190 A GB 2302190A
Authority
GB
United Kingdom
Prior art keywords
stage
addresses
address calculation
cache maintenance
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9621867A
Other versions
GB9621867D0 (en
GB2302190B (en
Inventor
Hugh Sherwood Field-Richards
Simon Robert Wiseman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UK Secretary of State for Defence
Original Assignee
UK Secretary of State for Defence
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB9409148A external-priority patent/GB9409148D0/en
Application filed by UK Secretary of State for Defence filed Critical UK Secretary of State for Defence
Priority to GB9621867A priority Critical patent/GB2302190B/en
Publication of GB9621867D0 publication Critical patent/GB9621867D0/en
Publication of GB2302190A publication Critical patent/GB2302190A/en
Application granted granted Critical
Publication of GB2302190B publication Critical patent/GB2302190B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0853—Cache with multiport tag or data arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/451—Stack data

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)

Abstract

A Data Cache (22) for a stack based computer (10) comprises an address calculation stage (25), a cache maintenance stage (26) and an arithmetic logic unit stage (27). The computer (10) comprises external memory (21) and a pipelined processor (20). An instruction from an instruction fetch stage (24) is passed to the address calculation stage (25). The address calculation stage (25) translates addresses relative to the top of stack into an absolute address. The cache maintenance stage receives the absolute addresses and determines if data corresponding to the addresses is available in a temporary register in the ALU stage (25). If necessary, the cache maintenance stage (26) injects read from or write to memory instructions into the pipeline (28).
GB9621867A 1994-05-09 1995-04-11 Data cache Expired - Fee Related GB2302190B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9621867A GB2302190B (en) 1994-05-09 1995-04-11 Data cache

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB9409148A GB9409148D0 (en) 1994-05-09 1994-05-09 Data cache
PCT/GB1995/000827 WO1995030954A1 (en) 1994-05-09 1995-04-11 Data cache
GB9621867A GB2302190B (en) 1994-05-09 1995-04-11 Data cache

Publications (3)

Publication Number Publication Date
GB9621867D0 GB9621867D0 (en) 1996-12-11
GB2302190A true GB2302190A (en) 1997-01-08
GB2302190B GB2302190B (en) 1999-01-06

Family

ID=26304844

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9621867A Expired - Fee Related GB2302190B (en) 1994-05-09 1995-04-11 Data cache

Country Status (1)

Country Link
GB (1) GB2302190B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2325541A (en) * 1997-04-14 1998-11-25 Ibm Layering cache and architectural-specific functions
GB2325542A (en) * 1997-04-14 1998-11-25 Ibm Layering cache and architectural-specific functions to expedite multiple designs
US6061755A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Method of layering cache and architectural specific functions to promote operation symmetry
GB2576572A (en) * 2018-08-24 2020-02-26 Advanced Risc Mach Ltd Processing of temporary-register-using instruction

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0134620A2 (en) * 1983-07-11 1985-03-20 Prime Computer, Inc. Data processing apparatus and method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6324428A (en) * 1986-07-17 1988-02-01 Mitsubishi Electric Corp Cache memory
US4833601A (en) * 1987-05-28 1989-05-23 Bull Hn Information Systems Inc. Cache resiliency in processing a variety of address faults

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0134620A2 (en) * 1983-07-11 1985-03-20 Prime Computer, Inc. Data processing apparatus and method

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
14th Annual International Symposium on Computer Architecture, 2-5 June 1987, pages 309-319 *
Computer Society International Conference (COMPCON), IEEE, 26 Feb - 2 Mar 1990, pages 36-43,254-258 *
IEEE Micro, Vol 7 No 4, August 1987, M Johnson, pages 28-41 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2325541A (en) * 1997-04-14 1998-11-25 Ibm Layering cache and architectural-specific functions
GB2325542A (en) * 1997-04-14 1998-11-25 Ibm Layering cache and architectural-specific functions to expedite multiple designs
US6032226A (en) * 1997-04-14 2000-02-29 International Business Machines Corporation Method and apparatus for layering cache and architectural specific functions to expedite multiple design
US6061762A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Apparatus and method for separately layering cache and architectural specific functions in different operational controllers
US6061755A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Method of layering cache and architectural specific functions to promote operation symmetry
GB2325542B (en) * 1997-04-14 2002-04-03 Ibm Layering cache and architectural specific functions to expedite multiple designs
GB2325541B (en) * 1997-04-14 2002-04-17 Ibm Layering cache and architectural specific functions
GB2576572A (en) * 2018-08-24 2020-02-26 Advanced Risc Mach Ltd Processing of temporary-register-using instruction
GB2576572B (en) * 2018-08-24 2020-12-30 Advanced Risc Mach Ltd Processing of temporary-register-using instruction
US11036511B2 (en) 2018-08-24 2021-06-15 Arm Limited Processing of a temporary-register-using instruction including determining whether to process a register move micro-operation for transferring data from a first register file to a second register file based on whether a temporary variable is still available in the second register file

Also Published As

Publication number Publication date
GB9621867D0 (en) 1996-12-11
GB2302190B (en) 1999-01-06

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20020411