GB9621867D0 - Data cache - Google Patents
Data cacheInfo
- Publication number
- GB9621867D0 GB9621867D0 GBGB9621867.2A GB9621867A GB9621867D0 GB 9621867 D0 GB9621867 D0 GB 9621867D0 GB 9621867 A GB9621867 A GB 9621867A GB 9621867 D0 GB9621867 D0 GB 9621867D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- data cache
- cache
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
- G06F9/3875—Pipelining a single stage, e.g. superpipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0853—Cache with multiport tag or data arrays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/45—Caching of specific data in cache memory
- G06F2212/451—Stack data
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9621867A GB2302190B (en) | 1994-05-09 | 1995-04-11 | Data cache |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9409148A GB9409148D0 (en) | 1994-05-09 | 1994-05-09 | Data cache |
PCT/GB1995/000827 WO1995030954A1 (en) | 1994-05-09 | 1995-04-11 | Data cache |
GB9621867A GB2302190B (en) | 1994-05-09 | 1995-04-11 | Data cache |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9621867D0 true GB9621867D0 (en) | 1996-12-11 |
GB2302190A GB2302190A (en) | 1997-01-08 |
GB2302190B GB2302190B (en) | 1999-01-06 |
Family
ID=26304844
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9621867A Expired - Fee Related GB2302190B (en) | 1994-05-09 | 1995-04-11 | Data cache |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2302190B (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6032226A (en) * | 1997-04-14 | 2000-02-29 | International Business Machines Corporation | Method and apparatus for layering cache and architectural specific functions to expedite multiple design |
US6061755A (en) * | 1997-04-14 | 2000-05-09 | International Business Machines Corporation | Method of layering cache and architectural specific functions to promote operation symmetry |
US6061762A (en) * | 1997-04-14 | 2000-05-09 | International Business Machines Corporation | Apparatus and method for separately layering cache and architectural specific functions in different operational controllers |
GB2576572B (en) | 2018-08-24 | 2020-12-30 | Advanced Risc Mach Ltd | Processing of temporary-register-using instruction |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1985000453A1 (en) * | 1983-07-11 | 1985-01-31 | Prime Computer, Inc. | Data processing system |
JPS6324428A (en) * | 1986-07-17 | 1988-02-01 | Mitsubishi Electric Corp | Cache memory |
US4833601A (en) * | 1987-05-28 | 1989-05-23 | Bull Hn Information Systems Inc. | Cache resiliency in processing a variety of address faults |
-
1995
- 1995-04-11 GB GB9621867A patent/GB2302190B/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
GB2302190A (en) | 1997-01-08 |
GB2302190B (en) | 1999-01-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20020411 |