GB2302190B - Data cache - Google Patents

Data cache

Info

Publication number
GB2302190B
GB2302190B GB9621867A GB9621867A GB2302190B GB 2302190 B GB2302190 B GB 2302190B GB 9621867 A GB9621867 A GB 9621867A GB 9621867 A GB9621867 A GB 9621867A GB 2302190 B GB2302190 B GB 2302190B
Authority
GB
Grant status
Grant
Patent type
Prior art keywords
data cache
cache
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9621867A
Other versions
GB9621867D0 (en )
GB2302190A (en )
Inventor
Hugh Sherwood Field-Richards
Simon Robert Wiseman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Kingdom Secretary of State for Defence
Original Assignee
United Kingdom Secretary of State for Defence
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3875Pipelining a single stage, e.g. superpipelining
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824Operand accessing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0853Cache with multiport tag or data arrays
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855Overlapped cache accessing, e.g. pipeline
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45Caching of specific data in cache memory
    • G06F2212/451Stack data
GB9621867A 1994-05-09 1995-04-11 Data cache Expired - Fee Related GB2302190B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB9409148A GB9409148D0 (en) 1994-05-09 1994-05-09 Data cache
GB9621867A GB2302190B (en) 1994-05-09 1995-04-11 Data cache
PCT/GB1995/000827 WO1995030954A1 (en) 1994-05-09 1995-04-11 Data cache

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9621867A GB2302190B (en) 1994-05-09 1995-04-11 Data cache

Publications (3)

Publication Number Publication Date
GB9621867D0 GB9621867D0 (en) 1996-12-11
GB2302190A true GB2302190A (en) 1997-01-08
GB2302190B true GB2302190B (en) 1999-01-06

Family

ID=26304844

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9621867A Expired - Fee Related GB2302190B (en) 1994-05-09 1995-04-11 Data cache

Country Status (1)

Country Link
GB (1) GB2302190B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6061755A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Method of layering cache and architectural specific functions to promote operation symmetry
US6032226A (en) * 1997-04-14 2000-02-29 International Business Machines Corporation Method and apparatus for layering cache and architectural specific functions to expedite multiple design
US6061762A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Apparatus and method for separately layering cache and architectural specific functions in different operational controllers

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0134620A2 (en) * 1983-07-11 1985-03-20 Prime Computer, Inc. Data processing apparatus and method
US4833601A (en) * 1987-05-28 1989-05-23 Bull Hn Information Systems Inc. Cache resiliency in processing a variety of address faults
US4901228A (en) * 1986-07-17 1990-02-13 Mitsubishi Denki K.K. Pipelined cache system using back up address registers for providing error recovery while continuing pipeline processing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0134620A2 (en) * 1983-07-11 1985-03-20 Prime Computer, Inc. Data processing apparatus and method
US4901228A (en) * 1986-07-17 1990-02-13 Mitsubishi Denki K.K. Pipelined cache system using back up address registers for providing error recovery while continuing pipeline processing
US4833601A (en) * 1987-05-28 1989-05-23 Bull Hn Information Systems Inc. Cache resiliency in processing a variety of address faults

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
14th Annual International Symposium on Computer Architecture, 2-5 June 1987, pages 309-319 *
Computer Society International Conference (COMPCON), IEEE, 26 Feb - 2 Mar 1990, pages 36-43,254-258 *
IEEE Micro, Vol 7 No 4, August 1987, M Johnson, pages 28-41 *

Also Published As

Publication number Publication date Type
GB9621867D0 (en) 1996-12-11 grant
GB2302190A (en) 1997-01-08 application

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20020411