BR9800961A - Método e aparelho para detecção, baseada em regiões, de interfência entre operações de memória reordenadas em um processador - Google Patents

Método e aparelho para detecção, baseada em regiões, de interfência entre operações de memória reordenadas em um processador

Info

Publication number
BR9800961A
BR9800961A BR9800961-3A BR9800961A BR9800961A BR 9800961 A BR9800961 A BR 9800961A BR 9800961 A BR9800961 A BR 9800961A BR 9800961 A BR9800961 A BR 9800961A
Authority
BR
Brazil
Prior art keywords
operations
memory
loading
regions
order
Prior art date
Application number
BR9800961-3A
Other languages
English (en)
Inventor
Jaime Humberto Moreno
Mayan Moudgill
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR9800961A publication Critical patent/BR9800961A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

Patente de Invenção:<B><MU>"MéTODO E APARELHO PARA DETECçãO, BASEADA EM REGIõES, DE INTERFERêNCIA ENTRE OPERAçõES DE MEMóRIA REORDENADAS EM UM PROCESSADOR"<MV><D>. Um sistema de processamento por computador armazena sequências de instruções em memória, para execução por uma unidade de processador. Uma instrução de carregamento fora de ordem pode ser criada, seja estática ou dinamicamente, movendo-se uma instrução de carregamento de sua posição original em uma sequência de instruções para uma posição mais à frente na dita sequência de instruções. Essa instrução de carregamento fora de ordem identifica uma localização na memória a partir da qual ler um dado. A presente invenção consiste em aparelho que mapeia o espaço para endereços de memória do sistema de computador em regiões, e detecta a execução incorreta de uma operação de carregamento realizada à frente de uma operação de armazenamento sequencialmente precedente (na ordem do programa). Mais especificamente, o aparelho detecta operações de carregamento fora de ordem, usa uma tabela de mapeamento baseada em regiões para se manter a par das regiões de memória acessadas pelas operações de carregamento fora de ordem detecta a execução de operações de armazenamento em regiões acessadas por operações de carregamento fora de ordem, e ordena ao processador para executar uma sequência de recuperação quando é detectada interferência entre operações reordenadas. A invenção é aplicável ao reordenamento estático e dinâmico de operações de memória.
BR9800961-3A 1997-03-25 1998-03-25 Método e aparelho para detecção, baseada em regiões, de interfência entre operações de memória reordenadas em um processador BR9800961A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/827,016 US5918005A (en) 1997-03-25 1997-03-25 Apparatus region-based detection of interference among reordered memory operations in a processor

Publications (1)

Publication Number Publication Date
BR9800961A true BR9800961A (pt) 1999-10-19

Family

ID=25248112

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9800961-3A BR9800961A (pt) 1997-03-25 1998-03-25 Método e aparelho para detecção, baseada em regiões, de interfência entre operações de memória reordenadas em um processador

Country Status (6)

Country Link
US (1) US5918005A (pt)
JP (1) JP2938426B2 (pt)
BR (1) BR9800961A (pt)
GB (1) GB2324181B (pt)
HK (1) HK1016291A1 (pt)
SG (1) SG71088A1 (pt)

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Also Published As

Publication number Publication date
JP2938426B2 (ja) 1999-08-23
GB2324181A (en) 1998-10-14
SG71088A1 (en) 2000-03-21
HK1016291A1 (en) 1999-10-29
US5918005A (en) 1999-06-29
GB9803608D0 (en) 1998-04-15
JPH10269080A (ja) 1998-10-09
GB2324181B (en) 2001-11-21

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Legal Events

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B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 8A E 9A ANUIDADES.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 1926 DE 04/12/2007.