JPS62203521U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of one embodiment of a digital filter circuit according to the present invention, FIG. 2 is a timing chart explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram of another embodiment of the present invention. FIG. 4 is a circuit diagram of a conventional digital filter circuit, and FIG. 5 is a timing chart for explaining the operation of the circuit shown in FIG. In the drawing, 1 is a first flip-flop circuit; 2 is a first flip-flop circuit;
is the second flip-flop circuit, 3 is the first AND circuit, 4 is the second AND circuit, 5 is the third flip-flop circuit, 6 is the first flip-flop circuit, 7 is the second flip-flop circuit, and 8 is the third flip-flop circuit. 1 is the NOR circuit, 9 is the second NOR circuit, 10, 11
12 is an input signal, 13 is a clock pulse, and 14 is a positive output.

Claims (1)

[Scope of utility model registration request] a first flip-flop circuit that receives a digital input signal using a clock pulse; a second flip-flop circuit that receives an output of the first flip-flop circuit using the clock pulse;
a first logic gate circuit that outputs an AND signal of the positive outputs of the first and second flip-flop circuits;
a second logic gate circuit that outputs an AND signal of the inverted outputs of the first and second flip-flop circuits; and a third flip-flop circuit that is set and reset by the outputs of the first and second logic gate circuits. A digital filter circuit characterized by comprising a circuit.