JPS62201532U - - Google Patents
Info
- Publication number
- JPS62201532U JPS62201532U JP8852786U JP8852786U JPS62201532U JP S62201532 U JPS62201532 U JP S62201532U JP 8852786 U JP8852786 U JP 8852786U JP 8852786 U JP8852786 U JP 8852786U JP S62201532 U JPS62201532 U JP S62201532U
- Authority
- JP
- Japan
- Prior art keywords
- flop
- flip
- input
- nand gate
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図は本考案の実施例の動作を説明するタイミング
チヤート、第３図は従来の入力回路の一例を示す
回路図、第４図は第３図示の従来回路の動作を説
明するためのタイミングチヤートである。
１，２，３……ＮＡＮＤゲート、４……第２フ
リツプフロツプ、５……インバータ、ＩＮ……入
力信号、……第２フリツプフロツプ４のセツト
信号（端子）、……第２のフリツプフロツプ４
のリセツト端子、Ａ……信号。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a timing chart for explaining the operation of the embodiment of the present invention, FIG. 3 is a circuit diagram showing an example of a conventional input circuit, and FIG. 4 is a timing chart for explaining the operation of the conventional circuit shown in FIG. be. 1, 2, 3...NAND gate, 4...Second flip-flop, 5...Inverter, IN...Input signal,...Set signal (terminal) of second flip-flop 4,...Second flip-flop 4
Reset terminal, A...signal.
Claims (1)
のフリツプフロツプを構成し、そのセツト入力に
接続された入力信号と前記第１のフリツプフロツ
プの出力とを第３のＮＡＮＤゲートの入力となし
、該第３のＮＡＮＤゲートの出力を第２のフリツ
プフロツプのセツト入力となし、該第２のフリツ
プフロツプの出力を前記第１のフリツプフロツプ
のリセツト信号とする入力回路において、前記第
１のフリツプフロツプのリセツト入力側となる第
２のＮＡＮＤゲートの出力端子をインバータを介
して前記第３のＮＡＮＤゲートの入力端子に接続
したことを特徴とする入力回路。 the first by the first and second NAND gates;
The input signal connected to the set input of the flip-flop and the output of the first flip-flop are input to a third NAND gate, and the output of the third NAND gate is connected to the set input of the second flip-flop. In an input circuit in which the output of the second flip-flop is used as a reset signal for the first flip-flop, the output terminal of the second NAND gate, which is the reset input side of the first flip-flop, is connected via an inverter. An input circuit connected to an input terminal of the third NAND gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8852786U JPH0430815Y2 (en) | 1986-06-12 | 1986-06-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8852786U JPH0430815Y2 (en) | 1986-06-12 | 1986-06-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62201532U true JPS62201532U (en) | 1987-12-22 |
| JPH0430815Y2 JPH0430815Y2 (en) | 1992-07-24 |
Family
ID=30946699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8852786U Expired JPH0430815Y2 (en) | 1986-06-12 | 1986-06-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0430815Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995028037A1 (en) * | 1994-04-08 | 1995-10-19 | Mars Technology Institute Co., Ltd. | Gate for connecting digital logic circuits |
-
1986
- 1986-06-12 JP JP8852786U patent/JPH0430815Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0430815Y2 (en) | 1992-07-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS62201532U (en) | ||
| JPS643329U (en) | ||
| JPS6155296U (en) | ||
| JPH0328596U (en) | ||
| JPS6223349U (en) | ||
| JPS61109228U (en) | ||
| JPS59189336U (en) | input circuit | |
| JPS62203519U (en) | ||
| JPS6399421U (en) | ||
| JPS61103969U (en) | ||
| JPS6367819U (en) | ||
| JPS62159027U (en) | ||
| JPS62192419U (en) | ||
| JPH01122629U (en) | ||
| JPS6335154U (en) | ||
| JPS62203521U (en) | ||
| JPS6332398U (en) | ||
| JPS6181221U (en) | ||
| JPS63146772U (en) | ||
| JPS6339754U (en) | ||
| JPS60111124U (en) | Pulse generator output control circuit | |
| JPS5952753U (en) | signal transmission circuit | |
| JPS61121014U (en) | ||
| JPS5893046U (en) | semiconductor logic circuit | |
| JPS6175638U (en) |