JPS643329U

JPS643329U -

Info

Publication number: JPS643329U
Application number: JP9838587U
Authority: JP
Priority date: 1987-06-25
Filing date: 1987-06-25
Publication date: 1989-01-10

Description

[Brief explanation of the drawing]

第１図及び第２図はそれぞれ本考案の第１及び
第２の実施例を示す回路図、第３図は従来のＲＳ
フリツプフロツプ回路の一例を示す回路図である
。１，２，２ａ……ＯＲゲート、３……ＡＮＤゲー
ト、４……Ｄフリツプフロツプ、５，６……イン
バータ、７ａ，７ｂ……ＡＮＤゲート、８ａ，８
ｂ……ＮＯＲゲート。 1 and 2 are circuit diagrams showing the first and second embodiments of the present invention, respectively, and FIG. 3 is a conventional RS
1 is a circuit diagram showing an example of a flip-flop circuit. FIG. 1, 2, 2a...OR gate, 3...AND gate, 4...D flip-flop, 5, 6...inverter, 7a, 7b...AND gate, 8a, 8
b...NOR gate.

Claims

[Claims for Utility Model Registration] (1) A first OR gate to which a plurality of set signals are input, a second OR gate to which a plurality of reset signals and an output signal of the first OR gate are input; an AND gate that inputs a clock signal and an output signal of the second OR gate, and a D flip-flop that inputs the output signal of the first OR gate to its D terminal and inputs the output signal of the AND gate to its clock terminal. An RS flip-flop circuit comprising: (2) Input a plurality of reset signals to a first OR gate, input a plurality of set signals and the first output signal to a second OR gate, and invert the output signal of the first OR gate. Claim No. (1) for Utility Model Registration to be input to the D terminal of the D flip-flop
The RS flip-flop circuit described in .