JPS61128841U - - Google Patents
Info
- Publication number
- JPS61128841U JPS61128841U JP1167285U JP1167285U JPS61128841U JP S61128841 U JPS61128841 U JP S61128841U JP 1167285 U JP1167285 U JP 1167285U JP 1167285 U JP1167285 U JP 1167285U JP S61128841 U JPS61128841 U JP S61128841U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- input
- flip
- output
- flops
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Pulse Circuits (AREA)
- Dc Digital Transmission (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は上記実施例の各部信号の一例を示すタイ
ムチヤート、第３図は従来の並列―直列変換回路
の一例を示すブロツク図、第４図は上記従来例の
各部信号を示すタイムチヤートである。
図において、１，２：入力用フリツプフロツプ
、３，４：ＮＯＲゲート、５：データ遅延回路、
６：オア回路、７：出力用フリツプフロツプ、８
：クロツク遅延回路。
FIG. 1 is a block diagram showing an embodiment of the present invention.
Fig. 2 is a time chart showing an example of the signals of each part of the above embodiment, Fig. 3 is a block diagram showing an example of a conventional parallel-to-serial conversion circuit, and Fig. 4 is a time chart showing the signals of each part of the above conventional example. be. In the figure, 1, 2: input flip-flop, 3, 4: NOR gate, 5: data delay circuit,
6: OR circuit, 7: Flip-flop for output, 8
: Clock delay circuit.
Claims (1)
入力信号を読込む複数の入力用フリツプフロツプ
と、 前記入力クロツクを一定時間遅延させた遅延ク
ロツクによつて前記入力用フリツプフロツプをリ
セツトするクロツク遅延回路と、 前記複数の入力用フリツプフロツプの出力をそ
れぞれ所定時間遅延させるための１つ以上のデー
タ遅延回路と、 前記複数の入力用フリツプフロツプの直接の出
力または各出力を前記データ遅延回路で遅延させ
た信号を合成出力するオア回路と、 前記入力クロツクの周波数ｆ０の整数倍の周波
数ｎｆ０の出力クロツクによつて前記オア回路の
出力信号を読込んで出力する出力用フリツプフロ
ツプとを備えたことを特徴とする並列―直列変換
回路。[Claims for Utility Model Registration] A plurality of input flip-flops that read respective input signals using an input clock having a frequency f0 , and a delay clock that delays the input clock by a certain period of time. a clock delay circuit for resetting, one or more data delay circuits for delaying the outputs of the plurality of input flip-flops by a predetermined time, and direct outputs or each output of the plurality of input flip-flops to the data delay circuit; and an output flip-flop that reads and outputs the output signal of the OR circuit using an output clock having a frequency nf0 that is an integral multiple of the frequency f0 of the input clock. A parallel-to-serial conversion circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1167285U JPS61128841U (en) | 1985-01-30 | 1985-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1167285U JPS61128841U (en) | 1985-01-30 | 1985-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61128841U true JPS61128841U (en) | 1986-08-12 |
Family
ID=30494008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1167285U Pending JPS61128841U (en) | 1985-01-30 | 1985-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61128841U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0260325A (en) * | 1988-08-26 | 1990-02-28 | Hitachi Ltd | Paralel serial converting circuit |
| JPH0447811A (en) * | 1990-06-15 | 1992-02-18 | Fujitsu Ltd | Pulse summing-up counter circuit |
-
1985
- 1985-01-30 JP JP1167285U patent/JPS61128841U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0260325A (en) * | 1988-08-26 | 1990-02-28 | Hitachi Ltd | Paralel serial converting circuit |
| JPH0447811A (en) * | 1990-06-15 | 1992-02-18 | Fujitsu Ltd | Pulse summing-up counter circuit |
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