JPS635529U

JPS635529U -

Info

Publication number: JPS635529U
Application number: JP9617486U
Authority: JP
Priority date: 1986-06-23
Filing date: 1986-06-23
Publication date: 1988-01-14

Description

[Brief explanation of drawings]

第１図は本考案の第１の実施例のブロツク図、
第２図は第１の実施例の動作を示すタイミング・
チヤート、第３図は本考案の第２の実施例のブロ
ツク図、第４図は第２の実施例の動作を示すタイ
ミングチヤート、第５図ａ，ｂ，ｃは本考案の応
用例を示す図、第６図は従来のシリアル・インタ
ーフエースのブロツク図である。１……マイクロコンピユータ、２，１１……シ
フト・レジスタ、３，１２，１６，１９……３ス
テート出力バツフア、４，８，１３……ＯＲゲー
ト、５，１４……３ビツト・カウンタ、６……分
周回路、７，１５……ＲＳフリツプ・フロツプ、
９……ＡＮＤゲート、１０……立下りエツジ検出
回路、１７，２０……セレクタ、１８……Ｄフリ
ツプ・フロツプ。 FIG. 1 is a block diagram of the first embodiment of the present invention;
FIG. 2 shows timing diagrams showing the operation of the first embodiment.
Figure 3 is a block diagram of the second embodiment of the present invention, Figure 4 is a timing chart showing the operation of the second embodiment, and Figures 5 a, b, and c show application examples of the present invention. FIG. 6 is a block diagram of a conventional serial interface. 1... Microcomputer, 2, 11... Shift register, 3, 12, 16, 19... 3-state output buffer, 4, 8, 13... OR gate, 5, 14... 3-bit counter, 6 ...Frequency divider circuit, 7,15...RS flip-flop,
9...AND gate, 10...Falling edge detection circuit, 17, 20...Selector, 18...D flip-flop.

Claims

[Scope of utility model registration request]

In the serial interface of the input/output circuit built into a one-chip microcomputer, there are two sets of serial input terminals, serial output terminals, and serial clock terminals, and input clocks from each of the serial clock terminals or from the internal circuit. two shift registers that shift data from the serial input terminal in synchronization with the output clock of the clock and output the data to the serial output terminal, respectively, and detect a falling edge of the serial data from one of the serial input terminals. and a falling edge detection circuit for starting one of the shift registers.