JPS62139133U - - Google Patents
Info
- Publication number
- JPS62139133U JPS62139133U JP2486086U JP2486086U JPS62139133U JP S62139133 U JPS62139133 U JP S62139133U JP 2486086 U JP2486086 U JP 2486086U JP 2486086 U JP2486086 U JP 2486086U JP S62139133 U JPS62139133 U JP S62139133U
- Authority
- JP
- Japan
- Prior art keywords
- gates
- flip
- signal
- input side
- side terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Pulse Circuits (AREA)
Description
第１図は本考案の一実施例に係るタイミング信
号発生回路の回路図、第２図は同回路のタイムチ
ヤート図、第３図は従来のタイミング信号発生回
路の回路図、第４図は同回路のタイムチヤート図
である。
２：クロツク信号入力端子、３：出力端子、１
１：第一入力端子、１２：第二入力端子、１３：
第三入力端子、１４，１５，１６：第一ＯＲゲー
ト、１７：第二ＯＲゲート、１８：第二フリツプ
フロツプ、１９，２０：第一フリツプフロツプ。
Fig. 1 is a circuit diagram of a timing signal generation circuit according to an embodiment of the present invention, Fig. 2 is a time chart of the same circuit, Fig. 3 is a circuit diagram of a conventional timing signal generation circuit, and Fig. 4 is the same. It is a time chart diagram of the circuit. 2: Clock signal input terminal, 3: Output terminal, 1
1: first input terminal, 12: second input terminal, 13:
Third input terminal, 14, 15, 16: first OR gate, 17: second OR gate, 18: second flip-flop, 19, 20: first flip-flop.
Claims (1)
複数の第一ＯＲゲートと、これら第一ＯＲゲート
のうちの一と対をなしその出力信号および所定の
クロツク信号を入力するとともに、出力側が他の
第一ＯＲゲートのうちの一の入力側他端子に接続
結合された一または複数の第一フリツプフロツプ
と、上記複数の第一ＯＲゲートの各出力側端子に
入力側端子が接続結合された第二ＯＲゲートと、
この第二ＯＲゲートの出力信号および所定のクロ
ツク信号を入力して最終出力信号を出力する第二
フリツプフロツプとを具備したことを特徴とする
タイミング信号発生回路。 A plurality of first OR gates each receiving a different input signal at one terminal on the input side, paired with one of these first OR gates and inputting its output signal and a predetermined clock signal; one or more first flip-flops connected to the other input side terminal of one of the first OR gates; and a second flip-flop whose input side terminal is connected to each output side terminal of the plurality of first OR gates. OR gate and
A timing signal generation circuit comprising a second flip-flop which receives the output signal of the second OR gate and a predetermined clock signal and outputs a final output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2486086U JPS62139133U (en) | 1986-02-21 | 1986-02-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2486086U JPS62139133U (en) | 1986-02-21 | 1986-02-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62139133U true JPS62139133U (en) | 1987-09-02 |
Family
ID=30824469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2486086U Pending JPS62139133U (en) | 1986-02-21 | 1986-02-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62139133U (en) |
-
1986
- 1986-02-21 JP JP2486086U patent/JPS62139133U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS62139133U (en) | ||
| JPS643329U (en) | ||
| JPH0439740U (en) | ||
| JPS62201532U (en) | ||
| JPS6181221U (en) | ||
| JPS61128841U (en) | ||
| JPH0221824U (en) | ||
| JPS635529U (en) | ||
| JPS62159027U (en) | ||
| JPS63131229U (en) | ||
| JPS63129333U (en) | ||
| JPS6332398U (en) | ||
| JPH0223117U (en) | ||
| JPS60127033U (en) | Logic circuit output circuit | |
| JPH01147441U (en) | ||
| JPH021928U (en) | ||
| JPS62203521U (en) | ||
| JPS61149431U (en) | ||
| JPH01103097U (en) | ||
| JPS63146772U (en) | ||
| JPS61143345U (en) | ||
| JPS62103324U (en) | ||
| JPH0416700U (en) | ||
| JPS61195127U (en) | ||
| JPS60163837U (en) | Synchronous up-down counter circuit |