JPS6416740U - - Google Patents
Info
- Publication number
- JPS6416740U JPS6416740U JP11159787U JP11159787U JPS6416740U JP S6416740 U JPS6416740 U JP S6416740U JP 11159787 U JP11159787 U JP 11159787U JP 11159787 U JP11159787 U JP 11159787U JP S6416740 U JPS6416740 U JP S6416740U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- under test
- output
- inverting
- pulse signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案の一実施例のブロツク回路図、
第２図はその実施例の各部信号のタイミングチヤ
ート、第３図は従来のカウンタバツフア回路の回
路図、第４図はその従来回路の各部信号のタイミ
ングチヤートである。
１…制御信号入力端、２…クロツク入力端、３
，４…インバータ、５，６…ＮＡＮＤ回路、７…
負論理ＲＳフリツプフロツプ、８，１５…ＡＮＤ
回路、９…制御信号、１０…クロツク、１１…Ｓ
入力、１２…Ｒ入力、１３…Ｑ出力、１４…ＡＮ
Ｄ回路８の出力、２０…ＡＮＤ回路１５の出力。
FIG. 1 is a block circuit diagram of an embodiment of the present invention.
FIG. 2 is a timing chart of various signals of the embodiment, FIG. 3 is a circuit diagram of a conventional counter buffer circuit, and FIG. 4 is a timing chart of various signals of the conventional circuit. 1...Control signal input terminal, 2...Clock input terminal, 3
, 4... Inverter, 5, 6... NAND circuit, 7...
Negative logic RS flip-flop, 8, 15...AND
Circuit, 9...Control signal, 10...Clock, 11...S
Input, 12...R input, 13...Q output, 14...AN
Output of D circuit 8, 20...Output of AND circuit 15.
Claims (1)
む制御信号と、前記被測定パルス信号をインバー
タにより反転した信号とを入力とする第２のＮＡ
ＮＤ回路と； 前記制御信号をインバータにより反転した信号
と、前記被測定パルス信号をインバータにより反
転した信号とを入力する第２のＮＡＮＤ回路と； 前記第１のＮＡＮＤ回路の出力をセツト端子に
受け、前記第２のＮＡＮＤ回路の出力をリセツト
端子に受ける負論理ＲＳフリツプフロツプと； 前記被測定パルス信号と前記負論理ＲＳフリツ
プフロツプのＱ出力信号とを入力とするＡＮＤ回
路とを有することを特徴とするカウンタバツフア
回路。[Claims for Utility Model Registration] A second NA whose inputs are a control signal that controls a pulse signal under test and sends it to a counter, and a signal obtained by inverting the pulse signal under test using an inverter.
an ND circuit; a second NAND circuit inputting a signal obtained by inverting the control signal by an inverter and a signal obtained by inverting the pulse signal under test; a set terminal receiving the output of the first NAND circuit; , a negative logic RS flip-flop that receives the output of the second NAND circuit at its reset terminal; and an AND circuit that receives the pulse signal under test and the Q output signal of the negative logic RS flip-flop as inputs. counter buffer circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11159787U JPS6416740U (en) | 1987-07-21 | 1987-07-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11159787U JPS6416740U (en) | 1987-07-21 | 1987-07-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6416740U true JPS6416740U (en) | 1989-01-27 |
Family
ID=31349783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11159787U Pending JPS6416740U (en) | 1987-07-21 | 1987-07-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6416740U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5325786A (en) * | 1976-08-21 | 1978-03-09 | Matsushita Electric Works Ltd | Electrode system liquid level controlled relay |
-
1987
- 1987-07-21 JP JP11159787U patent/JPS6416740U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5325786A (en) * | 1976-08-21 | 1978-03-09 | Matsushita Electric Works Ltd | Electrode system liquid level controlled relay |
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