JPH0369931U

JPH0369931U -

Info

Publication number: JPH0369931U
Application number: JP12973889U
Authority: JP
Priority date: 1989-11-08
Filing date: 1989-11-08
Publication date: 1991-07-12

Description

[Brief explanation of drawings]

第１図はこの考案の第１実施例の構成を示すブ
ロツク図。第２図はこの考案の第２実施例の構成
を示すブロツク図。第３図はこの考案の第３実施
例の構成を示すブロツク図。第４図はこの考案の
第４実施例の構成を示すブロツク図。第５図はこ
の考案の第１実施例および第３実施例の作用の説
明に供するタイミング図。第６図はこの考案の第
２実施例および第４実施例の作用の説明に供する
タイミング図。４１，４２，４４，４５，４１Ａ，４２Ａ，４
４Ｂおよび４５Ｂ……Ｄフリツプフロツプ、４３
および４３Ａ……アンドゲート、４６および４６
Ｂ……オアゲート。 FIG. 1 is a block diagram showing the configuration of a first embodiment of this invention. FIG. 2 is a block diagram showing the configuration of a second embodiment of this invention. FIG. 3 is a block diagram showing the configuration of a third embodiment of this invention. FIG. 4 is a block diagram showing the configuration of a fourth embodiment of this invention. FIG. 5 is a timing chart for explaining the operation of the first and third embodiments of this invention. FIG. 6 is a timing chart for explaining the operation of the second and fourth embodiments of this invention. 41, 42, 44, 45, 41A, 42A, 4
4B and 45B...D flip-flop, 43
and 43A...and gate, 46 and 46
B...or gate.

Claims

[Claims for Utility Model Registration] 1st D that reads the 1st input signal using a clock signal
a first circuit comprising a flip-flop, a second D flip-flop that reads the first input signal with a signal obtained by inverting the clock signal, and an AND gate whose inputs are the output of the first D flip-flop and the output of the second D flip-flop; a 3D flip-flop that reads a second input signal with a clock signal; a 4D flip-flop that reads the second input signal with the inverted signal; and an OR gate whose inputs are the output of the 3D flip-flop and the output of the fourth D flip-flop. and a second circuit continuously connected to the first circuit.
A noise reduction circuit characterized by comprising a circuit and.