JPS62198724U - - Google Patents
Info
- Publication number
- JPS62198724U JPS62198724U JP8672286U JP8672286U JPS62198724U JP S62198724 U JPS62198724 U JP S62198724U JP 8672286 U JP8672286 U JP 8672286U JP 8672286 U JP8672286 U JP 8672286U JP S62198724 U JPS62198724 U JP S62198724U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- gate
- gate pulse
- generates
- response
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Pulse Circuits (AREA)
Description
第１図は本考案の信号生成回路の回路図、第２
図及び第３図はそのタイミングチヤート、第４図
は従来の信号生成回路の回路図、第５図はそのタ
イミングチヤートである。
１……遅延型フリツプフロツプ、１１……検出
回路、２１……モノマルチバイブレータ、４１…
…遅延型フリツプフロツプ。
Figure 1 is a circuit diagram of the signal generation circuit of the present invention, Figure 2
3 and 3 are timing charts thereof, FIG. 4 is a circuit diagram of a conventional signal generation circuit, and FIG. 5 is a timing chart thereof. 1... Delay type flip-flop, 11... Detection circuit, 21... Mono multivibrator, 41...
...Delayed flip-flop.
Claims (1)
出回路の出力に対応して所定の幅のゲートパルス
を生成するゲートパルス生成回路と、該ゲートパ
ルスに対応して所定周期のクロツクをゲートする
ゲート回路と、該ゲート回路より出力されるクロ
ツクのタイミングにおける該入力信号のレベルに
対応した信号を発生する発生回路とを備えること
を特徴とする信号発生回路。 A detection circuit that detects an edge of an input signal, a gate pulse generation circuit that generates a gate pulse of a predetermined width in response to the output of the detection circuit, and a gate that gates a clock of a predetermined period in response to the gate pulse. 1. A signal generating circuit comprising: a circuit; and a generating circuit that generates a signal corresponding to the level of the input signal at the timing of a clock output from the gate circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8672286U JPS62198724U (en) | 1986-06-06 | 1986-06-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8672286U JPS62198724U (en) | 1986-06-06 | 1986-06-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62198724U true JPS62198724U (en) | 1987-12-17 |
Family
ID=30943294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8672286U Pending JPS62198724U (en) | 1986-06-06 | 1986-06-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62198724U (en) |
-
1986
- 1986-06-06 JP JP8672286U patent/JPS62198724U/ja active Pending
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