WO2024247464A1 - 回路基板、イメージセンサ及びイメージセンサの製造方法 - Google Patents

回路基板、イメージセンサ及びイメージセンサの製造方法 Download PDF

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Publication number
WO2024247464A1
WO2024247464A1 PCT/JP2024/012173 JP2024012173W WO2024247464A1 WO 2024247464 A1 WO2024247464 A1 WO 2024247464A1 JP 2024012173 W JP2024012173 W JP 2024012173W WO 2024247464 A1 WO2024247464 A1 WO 2024247464A1
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Prior art keywords
logic circuit
output
circuit
pin
signal
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Ceased
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PCT/JP2024/012173
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English (en)
French (fr)
Japanese (ja)
Inventor
博昭 重田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to CN202480015744.2A priority Critical patent/CN121264033A/zh
Priority to US19/154,398 priority patent/US20260113553A1/en
Priority to DE112024002420.3T priority patent/DE112024002420T5/de
Priority to JP2024560307A priority patent/JP7651078B1/ja
Publication of WO2024247464A1 publication Critical patent/WO2024247464A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/024—Details of scanning heads ; Means for illuminating the original
    • H04N1/028—Details of scanning heads ; Means for illuminating the original for picture information pick-up
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/701—Line sensors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

Definitions

  • This disclosure relates to a circuit board, an image sensor, and a method for manufacturing an image sensor.
  • Image sensors read images using sensor ICs (Integrated Circuits) arranged in the longitudinal direction.
  • the signal processing section includes a number of signal processing ICs such as FPGAs (Field Programmable Gate Arrays) and AFEs (Analog Front Ends). Since the number of signal processing ICs that can be mounted on one circuit board is limited, they are mounted on multiple circuit boards. The multiple circuit boards are synchronized with each other and process the image signals read out from each sensor IC.
  • the multiple circuit boards that make up the signal processing unit may have different types of mounted components and different lengths of boards depending on the function, arrangement order, etc. In such cases, component management and mounting can become complicated, leading to increased costs and mounting errors.
  • a method has been used in which components are enabled and disabled or wiring is switched using switches to reduce the number of board types (for example, Patent Document 1).
  • Patent Document 1 The semiconductor integrated circuit described in Patent Document 1 is equipped with a keeper circuit that holds the output logic of the three logic operation circuits and three inverters connected to the output terminals of the logic operation circuits, so that when the output of any one of the first logic operation circuits is at a low level, the output of the other first logic operation circuits is forcibly set to a high level. It is explained that this makes it possible to set only one of the output terminals to a high level.
  • the image sensor must read out one line of an image using a single synchronization signal, and multiple boards synchronize to acquire the sensor signal and output an image signal. For this reason, at least two types of boards are required: one that outputs the source clock and synchronization signal, and one that receives it. Also, to ensure that the longitudinal length of the image read at one time conforms to the specifications of the image reading device, multiple types of boards with different numbers of longitudinal pixels capable of signal processing are required.
  • Patent Document 1 The semiconductor integrated circuit described in Patent Document 1 includes a logic circuit that selects one of three terminals and outputs it based on eight input signals Q1 to Q8.
  • the logic circuit exemplified in Patent Document 1 is insufficient because the number of outputs is small relative to the number of inputs.
  • This disclosure has been made in consideration of the above-mentioned circumstances, and aims to provide a circuit board, an image sensor, and a method for manufacturing an image sensor that can function as multiple types of boards with different components or wiring.
  • the circuit board of the present disclosure comprises a switch including four or more selection pins, a logic circuit that outputs an ON signal from one output terminal selected from four or more independent output terminals when an ON signal is input from only one predetermined selection pin among the selection pins and an OFF signal is input from all other selection pins, and an electrical component that switches between enabled and disabled based on the output of the logic circuit.
  • electrical components are enabled or disabled by the output of a logic circuit based on the input from a selection pin of a switch, allowing a circuit board to function as multiple types of boards with different components or wiring.
  • FIG. 2 is a cross-sectional view showing inter-substrate wiring of the image sensor according to the first embodiment of the present disclosure.
  • Top view of a series of substrates for image processing of image sensors Top view of the image processing circuit board for the image sensor
  • Overall circuit diagram of logic circuit Circuit diagram of the first logic circuit FIG. 2 is a diagram showing a truth table of a first logic circuit. A diagram showing the truth table of the first and fifth pins of the second logic circuit. A diagram showing the truth table of the second and sixth pins of the second logic circuit. A diagram showing the truth table for the third and seventh pins of the second logic circuit. A diagram showing the truth table of the 4th pin and the 8th pin of the second logic circuit.
  • FIG. 3 is a truth table of the third logic circuit.
  • FIG. 4 is a truth table of the fourth logic circuit. Diagram showing input and output of logic circuit Circuit diagram of a logic circuit according to a second embodiment
  • FIG. 11 is a cross-sectional view showing inter-substrate wiring of another example of an
  • the image sensor 1 is any line sensor in which sensor ICs are arranged in a straight line, and is, for example, a contact image sensor (CIS) in which a sensor IC, a light source, and a lens array are integrated together.
  • CIS contact image sensor
  • FIG. 1 is a cross-sectional view illustrating the inter-substrate wiring of an image sensor 1 according to this embodiment.
  • the longitudinal direction of the image sensor 1 is shown as the X-axis direction, the lateral direction as the Y-axis direction, and the height direction perpendicular to the longitudinal and lateral directions as the Z-axis direction.
  • the longitudinal direction and lateral direction in the image sensor 1 according to this embodiment correspond to the main scanning direction and sub-scanning direction in the image sensor 1, respectively.
  • the image sensor 1 includes a frame 70 that holds the optical components and the signal processing boards 21, 22, and a cover 80 that covers the entire frame 70.
  • Fixed to the cover 80 are various connectors including, for example, a connector 51 that supplies power to each board and a connector 52 that outputs a signal to control the lighting, a cooling fan 53, and boards 40, 41 that control the image sensor 1.
  • the frame 70 and cover 80 are made of, for example, aluminum.
  • the boards 21 and 22 fixed to the frame 70 are boards having an A/D (Analog to Digital) conversion circuit that converts the analog signal output by the sensor IC into a digital signal.
  • One or more boards 21 and one or more boards 22 are arranged in the main scanning direction. In order to set the length of the image sensor 1 in the main scanning direction to a predetermined length, the lengths of the boards 21 and 22 in the main scanning direction are different from each other, and the length of the board 22 is longer than the length of the board 21.
  • Boards 10a to 10h (hereinafter sometimes collectively referred to as board 10) are fixed to each of boards 21 and 22 via spacers. Boards 10a to 10h are boards that add the necessary image processing to the digital signals output by boards 21 and 22, and each of boards 10a to 10h inputs and outputs a source clock, a synchronization signal, or a control signal.
  • Boards 10a to 10h have the same size, components, and wiring, and their functions are switched by physical switches.
  • the number of boards 10 is arbitrary, but there must be at least two, one that transmits a synchronization signal based on the source clock and one that receives it.
  • two or more types of boards with different numbers of pixels in the main scanning direction capable of signal processing are arranged.
  • the physical switch is an 8-channel DIP switch, and there are eight boards 10, boards 10a to 10h. Details of boards 10a to 10h will be described later.
  • Substrate 30 is fixed to each of substrates 10a-10h via spacer 31. Substrate 30 supplies power to each of substrates 10a-10h and transmits and receives communication signals.
  • the frame 70 of the image sensor 1 may further include a light source that irradiates light onto the object to be read and a control board for the light source.
  • the light source is, for example, an LED (Light Emitting Diode).
  • the board 40 which is fixed to the cover 80, is connected to the boards 10a to 10h by wiring, and converts the image signals processed by the boards 10a to 10h into a predetermined standard and outputs it to the outside.
  • the standard of the signal output to the outside is arbitrary, and examples include CameraLink (registered trademark), CoaXPress (registered trademark), GigEVision (registered trademark), and USB3Vision (registered trademark).
  • the board 41 fixed to the cover 80 is a board that has a microcomputer that centrally manages the entire image sensor 1, is connected to the board 30 by wiring, and transmits and receives control signals between the boards 10 and 30 and the outside.
  • image sensor 1 receives light irradiated from a light source that is transmitted through or reflected from the object to be read, and outputs an analog signal.
  • the A/D conversion circuits on boards 21 and 22 convert the analog signal input from the sensor IC into a digital signal.
  • the converted digital signal undergoes signal processing, including rearrangement of image data, on boards 10a to 10h, and is transmitted to board 40 via wiring.
  • Board 40 converts the received image signal into a predetermined standard and outputs it to the outside.
  • board 40 receives a control signal input from the outside and outputs it to the microcomputer of board 41. Based on the received control signal, the microcomputer of board 41 transmits a control signal to boards 10a-10h through wiring and board 30, thereby controlling boards 10a-10h.
  • the boards 10a-10h of the image sensor 1 according to this embodiment are characterized by being one type of circuit board.
  • Fig. 2 is a top view of a series of image processing boards 10a-10h arranged in the main scanning direction with adjacent boards connected to each other
  • Fig. 3 is a top view of one board 10.
  • Boards 10a-10h are all of the same type of circuit board, with the same components mounted on them and the same wiring, and components can be enabled or disabled by switching switches 107.
  • board 10 is equipped with a main clock 101, a buffer 102 that conditions the source clock signal output from main clock 101, a connector 103 for a cable that electrically connects the boards, a buffer 104 that conditions the signal input from the previous board, a buffer 105 that conditions the signal to be sent to the previous board, and a signal processing IC.
  • the signal processing IC is, for example, an FPGA (Field Programmable Gate Array).
  • the board 10 is equipped with a switch 107 that selects the state of the electrical components of the board 10, including whether they are enabled or disabled, and a logic circuit 108 that performs a logical operation on the output of the switch 107 and outputs the result.
  • a switch 107 that selects the state of the electrical components of the board 10, including whether they are enabled or disabled
  • a logic circuit 108 that performs a logical operation on the output of the switch 107 and outputs the result.
  • four or more output terminals of the logic circuit 108 are connected to the main clock 101 and the enable terminals of each of the buffers 102, 104, and 105 via wiring 109.
  • the connector 103 of the board 10 is connected to the connector 103 of an adjacent board 10 by a cable 110.
  • the switch 107 and the logic circuit 108 will be described in detail with reference to Figures 4 to 10.
  • the switch 107 is a physical switch having four or more channels, for example an eight-channel DIP switch (referred to as DIP-SW in the figures).
  • DIP-SW eight-channel DIP switch
  • One terminal of the switch 107 is connected to GND, and the other terminal, which is a selection pin, is pulled up.
  • the first pin P1 to the eighth pin P8 which are selection pins, are at a low level when the switch 107 is ON (shorted), and are at a high level when the switch 107 is OFF (open).
  • the logic circuit 108 is a circuit that outputs an ON signal from one of the four or more independent output terminals selected by a logical operation when an ON signal is input from only one of the four or more selection pins of the switch 107 and an OFF signal is input from all the other pins.
  • the switch 107 has eight channels. That is, when a Low-level ON signal is input from only one of the first pin P 1 to the eighth pin P 8 of the switch 107 and a High-level OFF signal is input from all the other pins, the logic circuit 108 outputs a Low-level ON signal from one of the output terminals S 1 to S 8 selected by a logical operation.
  • the Low or High output of the logic circuit 108 is input as an enable signal to the enable terminals of the buffers 102, 104, and 105 to control whether the buffers are enabled or disabled.
  • the logic circuit 108 when the first pin P1 of the switch 107 is set to low, the logic circuit 108 performs a logical operation in which only the output terminal S1 of the logic circuit 108 is set to low. In this case, by turning on only the first channel of the switch 107, the ON signal output from the output terminal S1 of the logic circuit 108 is input to the buffer 102, which enables the buffer 102 and outputs the clock signal of the main clock 101 into the circuit.
  • the output terminal S1 of the logic circuit 108 goes High, so that the buffer 102 is disabled and the clock signal is not output to the circuit. This allows the board that outputs the clock signal to be reliably selected using the switch 107. Also, when multiple channels of the switch 107 are turned ON by mistake, the output of the logic circuit 108 goes High, so it is possible to avoid the problem of signal collision due to erroneous operation.
  • logic circuit 108 may be input to the enable terminal of main clock 101 to control clock oscillation or stopping. Also, the output of logic circuit 108 may be input to the enable terminals of buffers 104 and 105 to control signal transmission between boards.
  • Figure 4 is a diagram showing the overall configuration of the logic circuit 108
  • Figure 5 is a diagram showing the configuration of a first logic circuit 1081, which is a part of the logic circuit 108.
  • the logic circuit 108 includes a first logic circuit 1081, a second logic circuit 1082, a third logic circuit 1083, and a fourth logic circuit 1084.
  • Figure 6 is a truth table of the first logic circuit 1081
  • Figures 7A to 7D are truth tables of the second logic circuit 1082
  • Figure 8 is a truth table of the third logic circuit 1083
  • Figure 9 is a truth table of the fourth logic circuit 1084.
  • Figure 10 is a diagram showing the input and output of the logic circuit 108.
  • the first pin P1 to the eighth pin P8 which are selection pins for each channel of the switch 107, are connected to the inputs of the first logic circuit 1081. As shown in Fig. 5, the first pin P1 and the fifth pin P5 , the second pin P2 and the sixth pin P6 , the third pin P3 and the seventh pin P7 , and the fourth pin P4 and the eighth pin P8, which are separated from each other, are connected to the four AND circuits 1101 in the first stage of the first logic circuit 1081 .
  • AND circuit 1101 The output of AND circuit 1101 is inverted by NOT circuit 1102 and input to AND circuit 1103 and NOR circuit 1104.
  • the output of AND circuit 1103 is input to NOR circuit 1105, and the output of NOR circuit 1105 is inverted by NOT circuit 1106 and input to NOR circuit 1108.
  • the output of the NOR circuit 1104 is input to an AND circuit 1107, the output of which is input to a NOR circuit 1108.
  • the output of the NOR circuit 1108 is inverted by a NOT circuit 1109 and then input to a NOR circuit 1110, the output of which is inverted by a NOT circuit 1111 and output from the output terminal SL1 of the first logic circuit 1081.
  • a truth table of the first logic circuit 1081 having such a configuration is shown in Fig. 6.
  • the four digits on the vertical axis correspond to the values of the third pin P3 , the seventh pin P7 , the fourth pin P4 , and the eighth pin P8 of the switch 107.
  • the four digits on the horizontal axis correspond to the values of the first pin P1 , the fifth pin P5 , the second pin P2 , and the sixth pin P6 of the switch 107.
  • a value of 0 is a low value and a value of 1 is a high value.
  • the value of the output terminal S L1 of the first logic circuit is Low in 12 cases: when at least one of the first pin P1 and the fifth pin P5 is Low, when at least one of the second pin P2 and the sixth pin P6 is Low, when at least one of the third pin P3 and the seventh pin P7 is Low, and when at least one of the fourth pin P4 and the eighth pin P8 is Low. In all other cases, the value of the output terminal S L1 of the first logic circuit is High.
  • the second logic circuit 1082 includes four exclusive OR (XOR) circuits 1201, and the first pin P1 and the fifth pin P5 , the second pin P2 and the sixth pin P6 , the third pin P3 and the seventh pin P7 , and the fourth pin P4 and the eighth pin P8 are connected to the inputs of the exclusive OR circuits 1201.
  • the output of the exclusive OR circuits 1201 is inverted by a NOT circuit 1202 and output to the third logic circuit 1083.
  • the output of the second logic circuit 1082 is High when the values of the first pin P1 and the fifth pin P5 , the second pin P2 and the sixth pin P6 , the third pin P3 and the seventh pin P7 , and the fourth pin P4 and the eighth pin P8 are the same, and is Low when they are different from each other.
  • the third logic circuit 1083 has four negative OR (NOR) circuits 1301, and the output of the first logic circuit 1081 and the output of the second logic circuit 1082 are input to the input of each NOR circuit 1301.
  • the output of the NOR circuit 1301 is inverted by a NOT circuit 1302 and output to the fourth logic circuit 1084.
  • the fourth logic circuit 1084 includes eight negative OR (NOR) circuits 1401, and the output of the third logic circuit 1083 and the first pin P1 to the eighth pin P8 are connected to the inputs of each NOR circuit 1401.
  • the output of the NOR circuit 1401 is inverted by a NOT circuit 1402 and then output.
  • the output of the fourth logic circuit 1084 i.e., the output of the logic circuit 108
  • the output of the fourth logic circuit 1084 is High
  • the output of the fourth logic circuit 1084 is High
  • FIG. 10 shows inputs and outputs of the logic circuit 108 having the above-described configuration.
  • the logic circuit 108 when a low-level ON signal is input only from the first pin P1 by turning on only the first channel of the switch 107, a low-level ON signal is output from the output terminal S1 .
  • a low-level ON signal is input only from the fifth pin P5, only from the second pin P2, only from the sixth pin P6 , only from the third pin P3 , only from the seventh pin P7 , only from the fourth pin P4, and only from the eighth pin P8 , a low-level ON signal is output from the output terminals S5 , S2 , S6 , S3 , S7 , S4 , and S8, respectively.
  • logic circuit 108 which operates in this manner, can control the enable/disable of electrical components, including main clock 101, on boards 10a to 10h. Furthermore, if logic circuit 108 was not included and switch 107 was connected directly to the enable terminals of each electrical component, a malfunction could occur if multiple of the eight channels of switch 107 were accidentally turned on; however, by using logic circuit 108, such malfunctions can be avoided.
  • logic circuit 108 shown in Figures 4 to 9 are merely examples, and replacements are possible.
  • the combination of a negative OR (NOR) circuit and a NOT circuit may be replaced with a logical OR (OR) circuit.
  • the combination of a logical AND circuit and a NOT circuit may be replaced with a negative AND (NAND) circuit.
  • the combination of an exclusive OR (XOR) circuit and a NOT circuit may be replaced with an exclusive NOT OR (NXOR) circuit.
  • the substrates 21 and 22 having A/D conversion circuits are fixed to the frame 70 to which the sensor IC shown in FIG. 1 is fixed along the arrangement direction of the sensor IC, i.e., the main scanning direction.
  • the substrates 10a to 10h are fixed to each of the substrates 21 and 22 via the spacers 25 (substrate fixing step).
  • the switches 107 of each of the boards 10a to 10h shown in FIG. 2 are operated. Specifically, only one predetermined selection pin of the switch 107 of each of the boards 10a to 10h is turned ON, and the other selection pins are turned OFF. This causes an ON signal to be output from one output selected from eight independent outputs of the logic circuit 108, and the corresponding electrical component is switched to an enabled state (switch setting step).
  • board 30 is fixed to boards 10a to 10h via spacers 31. After that, wiring is used to connect boards 40, 41, connectors 51, 52, and FAN 53 fixed to the cover, and boards 10, 30 fixed to the frame 70. After that, cover 80 is fixed to the frame 70.
  • the image sensor 1 uses the board 10 having the same components and wiring as a board for processing an image signal acquired from a sensor IC.
  • the board 10 is mounted with a switch 107 and a logic circuit 108 that performs a logical operation on an input signal from the switch 107 and outputs the result.
  • the logic circuit 108 performs a logical operation to output a low level from one of the output terminals S 1 to S 8 that are independent of each other when only one of the first pin P 1 to the eighth pin P 8 of the switch 107 becomes low.
  • the output of the logic circuit 108 is input to the enable terminals of the buffers 102, 104, and 105 to control whether the buffers are enabled or disabled. This makes it possible to realize a long image sensor by using one type of circuit board instead of multiple types of circuit boards for image processing. In addition, since one type of circuit board is used, the manufacturing process can be simplified.
  • the image sensor 1 according to the second embodiment of the present disclosure is a line sensor in which sensor ICs are arranged in a straight line, and has a similar configuration to the image sensor 1 according to the first embodiment.
  • the configuration of the logic circuit 128 mounted on the substrate 10 is different from that of the first embodiment.
  • the image sensor 1 according to the second embodiment will be described in detail with reference to the drawings.
  • the logic circuit 128 includes a total AND circuit 1281, which is a multi-stage AND circuit, between the logic circuit 108 and a specific electrical component. That is, as shown in FIG. 11, the logic circuit 128 includes a total AND circuit 1281 that outputs the logical product of output signals from all output terminals other than one output terminal selected from the output terminals S 1 to S 8 of the fourth logic circuit 1084. In FIG. 11, the logical sum of output signals from the output terminals S 2 to S 8 other than the output terminal S 1 is sequentially obtained.
  • the logic circuit 128 outputs Low from the output terminal S A when any of the values of the output terminals S 2 to S 8 is Low, and outputs High from the output terminal S A when the values of the output terminals S 2 to S 8 are all High.
  • the output S A of the logic circuit 128 is input as an enable signal to an enable terminal of a specific electrical component, thereby enabling or disabling the specific electrical component.
  • the specific electrical component is, for example, the main clock 101, which controls the oscillation or stop of the clock based on the output S A.
  • one output terminal selected from the output terminals S 1 to S 8 of the fourth logic circuit 1084 is directly connected to the buffers 102 , 104 , and 105 , which are other electric components, and is controlled to be valid or invalid.
  • the logic circuit 128 that outputs an enable signal includes the full AND circuit 1281 that outputs the logical product of output signals from all output terminals other than one output terminal selected from the output terminals S 1 to S 8 of the fourth logic circuit 1084.
  • the signal from the output terminal S A of the full logic circuit 1281 is also used as an enable signal, so that it is possible to reliably switch between enabled and disabled states of the electrical components.
  • the switch 107 when the switch 107 has four channels, this can be achieved by fixing the fifth pin P5 , sixth pin P6 , seventh pin P7 , and eighth pin P8 of the first logic circuit 1081 all to High (pull-up).
  • this can be achieved by fixing the sixth pin P6 , seventh pin P7 , and eighth pin P8 of the first logic circuit 1081 to High
  • when the switch 107 has six channels this can be achieved by fixing the seventh pin P7 and eighth pin P8 of the first logic circuit 1081 to High
  • this when the switch 107 has seven channels, this can be achieved by fixing the eighth pin P8 of the first logic circuit 1081 to High.
  • the output terminals S5 , S6, S7 , and S8 of the fourth logic circuit 1084 corresponding to the pins fixed to High among the fifth pin P5, the sixth pin P6 , the seventh pin P7 , and the eighth pin P8 of the first logic circuit 1081 will be High, and these output terminals will be fixed to High (pulled up).
  • logic circuit 108 has been described as an example of a logic circuit that outputs an enable signal, but any other logic circuit may be used as long as it is a logic circuit that performs a logical operation in which, in response to four or more ON or OFF input signals, an ON or OFF signal is output from one output terminal selected from four or more independent output terminals.
  • the boards 10a to 10h are configured from one type of circuit board, and the function of the board 10 is switched by the switch 107 and the logic circuits 108, 128, but this is not limited to the above.
  • the board 10 may include the functions of the board 30.
  • the board 11 (11a to h) including the functions of the boards 10 and 30 may be configured from one type of circuit board, and the function of the board 11 may be switched by the switch 107 and the logic circuits 108, 128.
  • FIG. 12 is a diagram showing another example of an image sensor 2. This makes it possible to further reduce the number of board types.
  • a circuit board comprising:
  • the switch is a physical switch including eight select pins, the logic circuit includes a first logic circuit that outputs an ON signal when an ON signal is input from at least one of a predetermined one of the selection pins and another selection pin separated from the one selection pin; 2.
  • the logic circuit further includes a second logic circuit that calculates an exclusive OR of an input from the one selection pin and an input from the other selection pin, a third logic circuit that calculates an OR of an output from the first logic circuit and an output from the second logic circuit, and a fourth logic circuit that calculates an OR of an input from each of the eight selection pins and an output from the third logic circuit.
  • the logic circuit includes a full AND circuit that outputs a logical product of outputs from all output terminals other than the one selected output terminal, at least one of the electrical components is switched between enabled and disabled based on an output of the full AND circuit; 4.
  • the circuit board according to claim 1 The circuit board according to claim 1 .
  • a substrate fixing step of fixing a plurality of substrates for image processing each substrate having a switch including four or more selection pins, a logic circuit that performs a logical operation on an input from the selection pins, and an electrical component that switches between enabled and disabled based on an output from the logic circuit, along an arrangement direction of the sensor ICs, to a frame on which the sensor ICs are fixed; a switch setting step of setting only one of the selection pins to ON and setting all the other selection pins to OFF, thereby outputting a signal for enabling the electrical component from one output terminal selected from four or more output terminals independent of each other of the logic circuit.
  • a method for manufacturing an image sensor A method for manufacturing an image sensor.

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PCT/JP2024/012173 2023-06-02 2024-03-27 回路基板、イメージセンサ及びイメージセンサの製造方法 Ceased WO2024247464A1 (ja)

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CN202480015744.2A CN121264033A (zh) 2023-06-02 2024-03-27 电路基板、图像传感器以及图像传感器的制造方法
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