JPWO2024247464A1 - - Google Patents

Info

Publication number
JPWO2024247464A1
JPWO2024247464A1 JP2024560307A JP2024560307A JPWO2024247464A1 JP WO2024247464 A1 JPWO2024247464 A1 JP WO2024247464A1 JP 2024560307 A JP2024560307 A JP 2024560307A JP 2024560307 A JP2024560307 A JP 2024560307A JP WO2024247464 A1 JPWO2024247464 A1 JP WO2024247464A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2024560307A
Other languages
Japanese (ja)
Other versions
JP7651078B1 (ja
JPWO2024247464A5 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2024247464A1 publication Critical patent/JPWO2024247464A1/ja
Application granted granted Critical
Publication of JP7651078B1 publication Critical patent/JP7651078B1/ja
Publication of JPWO2024247464A5 publication Critical patent/JPWO2024247464A5/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/79Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/024Details of scanning heads ; Means for illuminating the original
    • H04N1/028Details of scanning heads ; Means for illuminating the original for picture information pick-up
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50Constructional details
    • H04N23/54Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/701Line sensors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Facsimile Heads (AREA)
JP2024560307A 2023-06-02 2024-03-27 回路基板、イメージセンサ及びイメージセンサの製造方法 Active JP7651078B1 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2023091875 2023-06-02
JP2023091875 2023-06-02
PCT/JP2024/012173 WO2024247464A1 (ja) 2023-06-02 2024-03-27 回路基板、イメージセンサ及びイメージセンサの製造方法

Publications (3)

Publication Number Publication Date
JPWO2024247464A1 true JPWO2024247464A1 (https=) 2024-12-05
JP7651078B1 JP7651078B1 (ja) 2025-03-25
JPWO2024247464A5 JPWO2024247464A5 (https=) 2025-05-13

Family

ID=93657107

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024560307A Active JP7651078B1 (ja) 2023-06-02 2024-03-27 回路基板、イメージセンサ及びイメージセンサの製造方法

Country Status (5)

Country Link
US (1) US20260113553A1 (https=)
JP (1) JP7651078B1 (https=)
CN (1) CN121264033A (https=)
DE (1) DE112024002420T5 (https=)
WO (1) WO2024247464A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024112603A (ja) * 2023-02-08 2024-08-21 三菱電機株式会社 半導体装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55167595U (https=) * 1979-05-18 1980-12-02
JP3008267B2 (ja) * 1997-01-30 2000-02-14 ローム株式会社 イメージセンサチップおよびイメージセンサ
JP3533357B2 (ja) 2000-02-29 2004-05-31 株式会社東芝 論理演算機能を備えた半導体集積回路
KR20110118874A (ko) * 2010-04-26 2011-11-02 삼성전자주식회사 반도체 장치, 이를 포함하는 반도체 시스템, 및 상기 반도체 장치의 동작 방법
KR102424352B1 (ko) * 2017-06-19 2022-07-25 삼성전자주식회사 루프 대역폭을 균일하게 유지시키기 위해 디지털 이득을 조절하는 디지털 위상 고정 루프 회로
CN113841103A (zh) * 2019-05-24 2021-12-24 索尼半导体解决方案公司 电路系统
KR20220165734A (ko) * 2020-04-09 2022-12-15 소니 세미컨덕터 솔루션즈 가부시키가이샤 신호 처리 장치, 센싱 모듈
JP7753044B2 (ja) * 2021-10-20 2025-10-14 キヤノン株式会社 光電変換装置
JP2023091875A (ja) 2021-12-21 2023-07-03 ボッシュ株式会社 異常検出装置、異常検出方法

Also Published As

Publication number Publication date
JP7651078B1 (ja) 2025-03-25
CN121264033A (zh) 2026-01-02
DE112024002420T5 (de) 2026-04-23
US20260113553A1 (en) 2026-04-23
WO2024247464A1 (ja) 2024-12-05

Similar Documents

Publication Publication Date Title
JPWO2024247464A1 (https=)
BR102023008688A2 (https=)
BR202022009269U2 (https=)
BR202022005961U2 (https=)
BR202022001779U2 (https=)
BR202022000931U2 (https=)
CN307046522S (https=)
CN307045349S (https=)
BY13149U (https=)
BY13148U (https=)
BY13147U (https=)
BY13146U (https=)
BY13144U (https=)
BY13143U (https=)
BY13142U (https=)
CN307050236S (https=)
CN307048987S (https=)
CN307048387S (https=)
CN307048165S (https=)
CN307048029S (https=)
CN307048027S (https=)
CN307047340S (https=)
CN307047042S (https=)
BY13141U (https=)
BY13157U (https=)

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20241010

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20241010

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20241010

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20241203

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250129

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20250212

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20250312

R150 Certificate of patent or registration of utility model

Ref document number: 7651078

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150