WO2024219142A1 - 抵抗変化材料、スイッチ素子用材料、スイッチ層、スイッチ素子及び記憶装置 - Google Patents

抵抗変化材料、スイッチ素子用材料、スイッチ層、スイッチ素子及び記憶装置 Download PDF

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WO2024219142A1
WO2024219142A1 PCT/JP2024/010661 JP2024010661W WO2024219142A1 WO 2024219142 A1 WO2024219142 A1 WO 2024219142A1 JP 2024010661 W JP2024010661 W JP 2024010661W WO 2024219142 A1 WO2024219142 A1 WO 2024219142A1
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switch
electrode
current density
variable resistance
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English (en)
French (fr)
Japanese (ja)
Inventor
祐司 須藤
イ シュアン
航介 柄木田
佳雅 松下
史雄 佐藤
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Tohoku University NUC
Nippon Electric Glass Co Ltd
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Tohoku University NUC
Nippon Electric Glass Co Ltd
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Priority to CN202480012998.9A priority Critical patent/CN120712910A/zh
Priority to JP2025515102A priority patent/JPWO2024219142A1/ja
Priority to KR1020257024264A priority patent/KR20250126100A/ko
Publication of WO2024219142A1 publication Critical patent/WO2024219142A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Definitions

  • the present invention relates to a variable resistance material, a material for a switch element, a switch layer, a switch element, and a memory device.
  • Next-generation non-volatile memory devices are attracting attention as a replacement for NAND-type flash memory.
  • resistance change and phase change memory devices have been proposed as next-generation non-volatile memory devices, and development is underway to increase capacity and speed.
  • Cross-point type memory devices are attracting attention as a next-generation non-volatile memory device structure (Patent Documents 1 and 2).
  • Cross-point type memory devices include word lines, bit lines that are orthogonal to the word lines in a planar view, and memory elements and switch elements that are arranged at the intersections of the two in a planar view.
  • transistors and diodes have been used as switch elements, but as memory devices become smaller, have larger capacities, and are more highly integrated, the use of Ovonic switch elements (Ovonic Threshold Switch: OTS elements), whose resistance changes depending on the applied voltage, is attracting attention.
  • Ovonic Threshold Switch OTS elements
  • OTS elements are required to show a large change in resistance with respect to the applied voltage (i.e., to have excellent OTS characteristics).
  • the present invention aims to provide a variable resistance material, a material for a switching element, a switching layer, a switching element, and a memory device that have excellent OTS characteristics.
  • the resistance change material of embodiment 1 is a resistance change material containing Te, and is characterized in that the OFF current density is 3.1 x 102 A/ cm2 or less, where the OFF current density is the current density when a voltage half the threshold voltage is applied.
  • the threshold voltage means the voltage value at which the electrical resistance value changes suddenly from a high resistance state to a low resistance state.
  • the OFF current density means the value obtained by dividing the current value (OFF current value) that flows when a voltage half the threshold voltage is applied by the contact area with the electrode.
  • the ON current density is preferably 1 ⁇ 10 6 A/cm 2 or more, where the ON current density is the current density when a voltage equal to or greater than the threshold voltage is applied.
  • the ON current density refers to the value obtained by dividing the value of the current (ON current) that flows when a voltage equal to or greater than the threshold voltage is applied by the contact area with the electrode.
  • variable resistance material of embodiment 3 is the same as embodiment 1 or 2, and preferably has a carrier mobility of 5 ⁇ 10 ⁇ 3 cm 2 /Vs or less.
  • variable resistance material of Aspect 4 in any one of Aspects 1 to 3, when a current density when a voltage equal to or higher than a threshold voltage is applied is defined as an ON current density, the ON/OFF current ratio obtained by dividing the ON current density by the OFF current density is preferably 1 ⁇ 104 or more.
  • variable resistance material of aspect 5 is any one of aspects 1 to 4, and preferably has a threshold voltage in the range of 0.5V to 10V.
  • variable resistance material of embodiment 6 is any one of embodiments 1 to 5, and preferably contains, in atomic percent, 0.1% to 50% Ge and 40% to 90% Te.
  • variable resistance material of embodiment 7, in any one of embodiments 1 to 6, preferably contains, in atomic percent, 1% to 59% of Si+Al+Ga+Sn+Bi+Cu+Ag+Zn+Y+In+Ca+Mg.
  • variable resistance material of embodiment 8 is any one of embodiments 1 to 7, and preferably contains, in atomic percent, 0% to less than 5% Sb.
  • variable resistance material of aspect 9 is preferably any one of aspects 1 to 7, and is substantially free of Sb, Se, and As.
  • variable resistance material of aspect 10 is any one of aspects 1 to 9, and preferably has an oxygen content of less than 1 atomic %.
  • variable resistance material of aspect 11 is preferably a thin film in any one of aspects 1 to 10.
  • the switching element material of aspect 12 is characterized in that it is made of a variable resistance material of any one of aspects 1 to 11.
  • the switch layer of aspect 13 is characterized in that it is made of a variable resistance material of any one of aspects 1 to 11.
  • the switch element of aspect 14 is characterized by having a switch layer of aspect 13 and a first electrode disposed on the switch layer.
  • a switch element of Aspect 15 includes a switch layer, a first electrode disposed on the switch layer, and a second electrode disposed opposite the first electrode across the switch layer, and is characterized in that the switch layer is made of a variable resistance material containing Te and having an OFF current density of 3.1 ⁇ 10 2 A/cm 2 or less, when the OFF current density is defined as the current density when a voltage that is 1 ⁇ 2 of a threshold voltage is applied.
  • the switch element of aspect 16 is preferably the same as aspect 15, in that the first electrode is disposed on the outer peripheral surface of the switch layer, and the second electrode is disposed on the inner peripheral surface of the switch layer.
  • the first electrode and the second electrode are preferably at least one selected from tungsten, titanium, copper, platinum, tungsten nitride, and titanium nitride.
  • the ionicity r ⁇ ' and hybridization r ⁇ -1 of the switching layer satisfy the following values. r ⁇ ′ ⁇ 0.05 r ⁇ ⁇ 1 ⁇ 2.0
  • the switching element of aspect 19 is preferably any one of aspects 15 to 18, where a is the carrier activation energy when a voltage of 0.15 V is applied to the switching layer, and b is the carrier activation energy when a voltage of 0.30 V is applied to the switching layer, such that a/b ⁇ 1.
  • the storage device of aspect 20 preferably includes a switch element of any one of aspects 15 to 19.
  • the storage device of aspect 21 preferably includes a switch element of any one of aspects 15 to 19 and a storage element.
  • a memory device of aspect 22 is a memory device including a laminate in which a switch element and a memory element are laminated, the switch element includes a switch layer and a first electrode disposed on the switch layer, the switch layer is made of a resistance change material having an OFF current density of 3.1 ⁇ 10 2 A/cm 2 or less when a current density when a voltage that is 1 ⁇ 2 of a threshold voltage is applied is defined as the OFF current density, and the memory element is any one of a resistance change memory element, a magnetoresistive memory element, a phase change memory element, and a ferroelectric memory element.
  • the present invention provides a variable resistance material, a material for a switch element, a switch layer, a switch element, and a memory device that have excellent OTS characteristics.
  • FIG. 1 is a schematic cross-sectional view of a switch element according to one embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of a memory element according to one embodiment of the present invention.
  • FIG. 3 is a schematic three-dimensional view of the storage device according to the first embodiment of the present invention.
  • FIG. 4 is a schematic enlarged three-dimensional view of the storage device according to the first embodiment of the present invention.
  • FIG. 5 is a schematic three-dimensional view of a modified example of the storage device according to the first embodiment of the present invention.
  • FIG. 6 is a schematic three-dimensional view of a storage device according to a second embodiment of the present invention.
  • FIG. 7 is a schematic three-dimensional view of a modified example of the storage device according to the second embodiment of the present invention.
  • FIG. 8 is a graph plotting the ionicity r ⁇ ' and hybridization r ⁇ -1 of the switch layer.
  • % means “atomic %” unless otherwise specified.
  • x+y+z+ means the total content of each component.
  • each component does not necessarily have to be contained as an essential component, and there may be components that are not contained (content 0%).
  • the resistance change material of the present invention is a resistance change material containing Te, and is characterized in that, when the current density when a voltage that is 1/2 the threshold voltage is applied is defined as the OFF current density, the OFF current density is 3.1 x 102 A/ cm2 or less.
  • the inventors have found that excellent OTS characteristics can be obtained in a variable resistance material whose OFF current density satisfies a predetermined value.
  • the OTS characteristic means a characteristic in which the resistance value changes with the application of voltage in a chalcogenide-based thin film.
  • the details are as follows.
  • a variable resistance material exhibits high resistance in the initial state (OFF state). When a voltage is applied to this state, the high resistance state is maintained until the threshold voltage is exceeded, and when the threshold voltage is exceeded, the material suddenly switches to a low resistance state (ON state). When the applied voltage is reduced from the ON state, the material returns to the OFF state.
  • a variable resistance material having excellent OTS characteristics has a large difference in resistance between the high resistance state and the low resistance state.
  • the ON/OFF current ratio means the value obtained by dividing the ON current density by the OFF current density.
  • the upper limit of the OFF current density is 3.1 ⁇ 10 2 A/cm 2 or less, preferably 3 ⁇ 10 2 A/cm 2 or less, 2.8 ⁇ 10 2 A/cm 2 or less, and particularly preferably 2.6 ⁇ 10 2 A/cm 2 or less.
  • the lower limit of the OFF current density is not particularly limited, but may be 5 ⁇ 10 ⁇ 3 A/cm 2 or more, 6 ⁇ 10 ⁇ 3 A/cm 2 or more, or 1 ⁇ 10 ⁇ 2 A/cm 2 or more.
  • the lower limit of the ON current density is preferably 1 ⁇ 10 6 A/cm 2 or more, 2 ⁇ 10 6 A/cm 2 or more, 3.1 ⁇ 10 6 A/cm 2 or more, 3.2 ⁇ 10 6 A/cm 2 or more, 3.5 ⁇ 10 6 A/cm 2 or more, 4.1 ⁇ 10 6 A/cm 2 or more, 4.2 ⁇ 10 6 A/cm 2 or more, 4.3 ⁇ 10 6 A/cm 2 or more, 4.4 ⁇ 10 6 A/cm 2 or more, particularly preferably 4.5 ⁇ 10 6 A/cm 2 or more.
  • the ON/OFF current ratio can be further increased.
  • the upper limit of the ON current density is not particularly limited, but may be, for example, 1 ⁇ 10 9 A/cm 2 or less, 1 ⁇ 10 8 A/cm 2 or less, or 1 ⁇ 10 7 A/cm 2 or less.
  • the lower limit of the ON/OFF current ratio is preferably 1 ⁇ 10 4 or more, 1.2 ⁇ 10 4 or more, 1.5 ⁇ 10 4 or more, 1.8 ⁇ 10 4 or more, 5 ⁇ 10 4 or more, 1 ⁇ 10 5 or more, 1.5 ⁇ 10 5 or more, 3.1 ⁇ 10 5 or more, 3.9 ⁇ 10 5 or more, 5 ⁇ 10 5 or more, 6.3 ⁇ 10 5 or more, and particularly preferably 1 ⁇ 10 6 or more.
  • the lower limit of log 10 x is preferably 4 or more, 4.1 or more, 4.2 or more, 4.3 or more, 4.7 or more, 5 or more, 5.2 or more, 5.5 or more, 5.6 or more, 5.7 or more, 5.8 or more, and particularly preferably 6 or more.
  • Such a large ON/OFF current ratio increases the difference between the current density in the low resistance state and the current density in the high resistance state (ON/OFF current ratio). That is, an excellent OTS effect can be obtained.
  • the upper limit of the ON/OFF current ratio is not particularly limited, but can be, for example, 2 ⁇ 10 10 or less, 1 ⁇ 10 9 or less, 1 ⁇ 10 8 or less, and particularly 1 ⁇ 10 7 or less.
  • the upper limit of the log 10 x value is 10.3 or less, 9 or less, 8 or less, and particularly 7 or less.
  • the resistance change material of the present invention preferably has a threshold voltage in the range of 0.5V to 10V. More specifically, the upper limit of the threshold voltage is preferably 10V or less, 8V or less, 6V or less, and particularly 5V or less. By having the threshold voltage within the above range, it is possible to drive a switching element or the like with less energy.
  • the lower limit of the threshold voltage is not particularly limited, but may be 0.5V or more, 0.8V or more, 1V or more, 1.2V or more, and particularly 1.5V or more.
  • the OFF current density, ON current density, ON/OFF current ratio, and threshold voltage can be determined as follows. First, a voltage of 0V to 10V is applied to the switch element, and the current value flowing through the switch element and the threshold voltage are measured. The voltage applied at this time is not limited to DC voltage, AC voltage, pulse voltage, etc., but it is preferable to measure with a pulse voltage from the viewpoint of preventing heat accumulation in the switch element.
  • the threshold voltage can be the voltage value at which the electrical resistance value changes suddenly from a high resistance state to a low resistance state.
  • the OFF current density can be the value obtained by dividing the current value (OFF current value) flowing when a voltage of 1/2 the threshold voltage is applied by the contact area with the first electrode or the second electrode.
  • the ON current density can be the value obtained by dividing the current value (ON current value) flowing when a voltage equal to or higher than the threshold voltage is applied by the contact area with the first electrode or the second electrode.
  • the ON/OFF current ratio can be determined by dividing the ON current value by the OFF current value. If the contact area between the switch element and the first electrode is the same as the contact area between the switch element and the second electrode, the current density can be calculated using the contact area of the first electrode or the second electrode, as described above. If the contact area between the switch element and the first electrode is different from the contact area between the switch element and the second electrode, the current density can be calculated using the smaller contact area.
  • variable resistance material of the present invention preferably has an upper limit of carrier mobility of 5 ⁇ 10 ⁇ 3 cm 2 /Vs or less, 4.5 ⁇ 10 ⁇ 3 cm 2 /Vs or less, 4 ⁇ 10 ⁇ 3 cm 2 /Vs or less, 3.5 ⁇ 10 ⁇ 3 cm 2 /Vs or less, particularly 3 ⁇ 10 ⁇ 3 cm 2 /Vs or less.
  • carrier mobility satisfies the above value
  • the OFF current density is likely to decrease. Therefore, the ON/OFF current ratio is likely to be increased.
  • the lower limit of the carrier mobility is not particularly limited, but may be, for example, 1 ⁇ 10 ⁇ 8 cm 2 /Vs or more, 1 ⁇ 10 ⁇ 7 cm 2 /Vs or more, or 1 ⁇ 10 ⁇ 6 cm 2 /Vs or more.
  • the carrier mobility can be measured using a resistivity/Hall measurement system.
  • the resistance change material of the present invention contains Te.
  • Te constitutes the resistance change material and is an essential component for obtaining OTS characteristics.
  • the content of Te is preferably 40% to 90%. More specifically, the lower limit of the content of Te is preferably 40% or more, 42% or more, 47% or more, 50% or more, more than 50%, 51% or more, 53% or more, 55% or more, 60% or more, 61% or more, 65% or more, 67% or more, 70% or more, and particularly 71% or more.
  • the upper limit of the content of Te is preferably 90% or less, 89% or less, 85% or less, 82.5% or less, 80% or less, 75% or less, and particularly 72.5% or less.
  • the amorphous state tends to become unstable. Also, it becomes difficult to obtain OTS characteristics. If the content of Te is too high, the amorphous state tends to become unstable. In addition, the carrier mobility becomes too large, which can easily lead to a large OFF current density.
  • the resistance change material of the present invention may contain components other than Te.
  • the material may contain, in atomic percent, 0.1% to 50% Ge and 40% to 90% Te. It may also contain components other than Ge and Te.
  • the Ge is a component that stabilizes the amorphous state of the resistance change material.
  • the Ge content is preferably 0.1% to 50%. More specifically, the lower limit of the Ge content is preferably 0.1% or more, 1% or more, 3% or more, 5% or more, 7% or more, 10% or more, 11% or more, and particularly preferably 13% or more.
  • the upper limit of the Ge content is preferably 50% or less, 40% or less, 30% or less, and particularly preferably 20% or less. If the Ge content is too low, the amorphous state tends to become unstable. If the Ge content is too high, it becomes difficult to obtain OTS characteristics. In addition, the manufacturing cost tends to increase.
  • the lower limit of the Ge+Te content (combined amount of Ge and Te) is preferably 41% or more, 45% or more, 50% or more, 60% or more, 65% or more, 70% or more, 75% or more, and especially 80% or more.
  • the upper limit of the Ge+Te content is preferably 99% or less, 98% or less, 97% or less, and especially 95% or less. If the Ge+Te content is too low, the amorphous state tends to become unstable. Also, it becomes difficult to obtain OTS characteristics. If the Ge+Te content is too high, it becomes difficult to obtain OTS characteristics.
  • the resistance change material of the present invention preferably has a Si+Al+Ga+Sn+Bi+Cu+Ag+Zn+Y+In+Ca+Mg content (the total amount of Si, Al, Ga, Sn, Bi, Cu, Ag, Zn, Y, In, Ca, and Mg) of 1% to 59%.
  • the lower limit of the Si+Al+Ga+Sn+Bi+Cu+Ag+Zn+Y+In+Ca+Mg content is preferably 1% or more, particularly 2% or more.
  • the upper limit of the content of Si+Al+Ga+Sn+Bi+Cu+Ag+Zn+Y+In+Ca+Mg is preferably 59% or less, 58% or less, 55% or less, 50% or less, 45% or less, 40% or less, 35% or less, 30% or less, 25% or less, 20% or less, 15% or less, 14% or less, 13% or less, 10% or less, and particularly 9% or less.
  • the above content may be rephrased as containing one or more components selected from Si, Al, Ga, Sn, Bi, Cu, Ag, Zn, Y, In, Ca, and Mg. If the content of these components is too small, it is difficult to obtain the above effects. If the content of these components is too large, the amorphous state is likely to become unstable. In addition, it is difficult to obtain OTS characteristics.
  • the lower limit of the content of each of the components Si, Al, Ga, Sn, Bi, Cu, Ag, Zn, Y, In, Ca, and Mg is preferably 0% or more, more than 0%, 0.1% or more, 0.5% or more, 1% or more, and particularly preferably 2% or more.
  • the upper limit of the content of each of the components Si, Al, Ga, Sn, Bi, Cu, Ag, Zn, Y, In, Ca, and Mg is preferably 59% or less, 58% or less, 55% or less, 50% or less, 45% or less, 40% or less, 35% or less, 30% or less, 25% or less, 20% or less, 15% or less, 14% or less, 13% or less, 10% or less, and particularly preferably 9% or less.
  • Ga and Ag are components that tend to reduce carrier mobility and lower the OFF current density, and therefore particularly contribute to improving the ON/OFF current ratio. They are also components that tend to particularly stabilize the amorphous state.
  • the lower limit of the Ga+Ag content (total amount of Ga and Ag) is preferably 0% or more, more than 0%, 0.1% or more, 0.5% or more, 1% or more, 2% or more, 3% or more, and especially 5% or more
  • the upper limit of the Ga+Ag content is preferably 59% or less, 58% or less, 55% or less, 50% or less, 45% or less, 40% or less, 35% or less, 30% or less, 25% or less, 20% or less, 15% or less, 14% or less, 13% or less, 10% or less, and especially 9% or less. If the Ga+Ag content is too high, the amorphous state tends to become unstable.
  • the lower limit of Ga/(Ga+Ag) is preferably 0.1 or more, and particularly 0.2 or more, and the upper limit of Ga/(Ga+Ag) is preferably 1.2 or less, less than 1.2, and particularly 1.1 or less.
  • Ga/(Ga+Ag) is the value obtained by dividing the Ga content by the combined amount of Ga and Ag.
  • the lower limit of Ag/(Ga+Ag) is 0.1 or more, and especially 0.2 or more
  • the upper limit of Ag/(Ga+Ag) is 1.2 or less, less than 1.2, and especially 1.1 or less.
  • Ag/(Ga+Ag) is the value obtained by dividing the Ag content by the combined amount of Ga and Ag.
  • Sb is an ingredient that easily destabilizes the amorphous state at high temperatures. For this reason, it is preferable that the Sb content be between 0% and less than 5%. More specifically, the upper limit of the Sb content is less than 5%, 4% or less, 3% or less, or 2% or less, and it is particularly preferable that Sb is not substantially contained. In this specification, “substantially not contained” means that it is not intentionally contained in the raw materials, and does not exclude the presence of impurity levels. Objectively, it refers to a content of each ingredient of less than 0.1%.
  • Se is a component that tends to stabilize the amorphous state of the resistance change material.
  • the upper limit of the Se content is preferably 58% or less, 55% or less, and especially 50% or less.
  • the lower limit of the Se content is preferably 0% or more, 1% or more, 5% or more, 10% or more, and especially 20% or more. If the Se content is too high, the amorphous state tends to become unstable. Se is also a toxic component. Therefore, from the viewpoint of reducing the burden on the environment, it is preferable that the upper limit of the Se content is 40% or less, 30% or less, 20% or less, 10% or less, and especially that substantially no Se is contained.
  • the As content is preferably 0% to 30%. More specifically, the upper limit of the As content is preferably 30% or less, 25% or less, 20% or less, 10% or less, 5% or less, 3% or less, and it is particularly preferable that As is substantially not contained.
  • variable resistance material of the present invention preferably does not substantially contain Sb, Se, or As. This makes it easier to further reduce the environmental impact.
  • the upper limit of the content of B+C+N+F+Cl+Br+I (the total amount of B, C, N, F, Cl, Br and I) is 50% or less, 45% or less, 40% or less, 35% or less, 30% or less, 25% or less, 20% or less, 15% or less, 14% or less, 12% or less, 10% or less, 8% or less, 6% or less, and especially 5% or less.
  • the upper limit of the content of each of the components B, C, N, F, Cl, Br, and I is preferably 50% or less, 45% or less, 40% or less, 35% or less, 30% or less, 25% or less, 20% or less, 15% or less, 14% or less, 12% or less, 10% or less, 8% or less, 6% or less, and particularly 5% or less.
  • the total amount of B, C, N, F, Cl, Br, and I may be contained in an amount of 0% or more, 1% or more, and particularly 2% or more.
  • the content of P+Cr+Mn+Ti+Fe (total amount of P, Cr, Mn, Ti, and Fe) is preferably 0% to 10%. More specifically, the upper limit of the content of P+Cr+Mn+Ti+Fe is preferably 10% or less, 5% or less, 1% or less, less than 1%, 0.1% or less, and in particular, it is preferable that they are not substantially contained. If the content of these components is too high, the amorphous state tends to become unstable.
  • the content of each of the components P, Cr, Mn, Ti, and Fe is preferably 0% to 10%.
  • the material does not substantially contain Cd, Tl, or Pb.
  • the lower limit of the oxygen content is preferably 1 ⁇ 10 ⁇ 6 % or more, 1 ⁇ 10 ⁇ 5 % or more, 5 ⁇ 10 ⁇ 5 % or more, 1 ⁇ 10 ⁇ 4 % or more, and particularly preferably 2 ⁇ 10 ⁇ 4 % or more, in atomic %.
  • the resistance change material of the present invention preferably has a crystallization temperature Tx of 150°C or higher, 160°C or higher, and particularly 170°C or higher.
  • Tx crystallization temperature
  • the crystallization temperature Tx may be, for example, 500°C or lower, 450°C or lower, and particularly 400°C or lower.
  • the number of cycles can be increased when used as a switching element. That is, the ON/OFF current ratio can be maintained even if ON and OFF are repeated.
  • the lower limit of the number of cycles is preferably 5 ⁇ 10 2 times or more, 1 ⁇ 10 3 times or more, and particularly 1 ⁇ 10 4 times or more. If the number of cycles is too small, it becomes difficult to use it as a switching element.
  • the upper limit of the number of cycles is not particularly limited, but may be, for example, 1 ⁇ 10 10 times or less, 1 ⁇ 10 9 times or less, 1 ⁇ 10 8 times or less, or 1 ⁇ 10 7 times or less.
  • the resistance change material of the present invention is preferably used as a thin film (resistance change film).
  • the thin film (resistance change film) is particularly suitable for use as a switch layer or switch memory layer, which will be described later.
  • the resistance change material is not limited to a thin film.
  • the film thickness of the thin film is preferably 1 nm to 300 nm. More specifically, the lower limit of the film thickness of the resistance change film is preferably 1 nm or more, 2 nm or more, 5 nm or more, 10 nm or more, 30 nm or more, and especially more than 50 nm, and the upper limit of the film thickness of the resistance change film is preferably 300 nm or less, 200 nm or less, and especially 100 nm or less. If the film thickness is too small, the current value (OFF current) in the high resistance state tends to be high. If the film thickness is too large, the threshold voltage is likely to be large.
  • the material for the switch element of the present invention is preferably made of the resistance change material of the present invention described above.
  • the switch layer of the present invention is preferably made of the resistance change material of the present invention described above.
  • the resistance change material of the present invention has excellent OTS characteristics, and therefore can be suitably used as a material for the switch layer and switch element.
  • variable resistance material of the present invention can be produced, for example, as follows. First, the raw materials are mixed to obtain the desired composition. Next, the mixed raw materials are placed in a quartz glass ampoule that has been heated and evacuated to a vacuum, and the ampoule is sealed with an oxygen burner while evacuating to a vacuum. Next, the sealed quartz glass ampoule is kept at approximately 650°C to 1000°C for 6 to 12 hours. After that, it is rapidly cooled to room temperature to obtain a bulk variable resistance material.
  • a thin film (resistance change film) having the above-mentioned composition can be formed by physical vapor deposition (PVD) using the obtained resistance change material as a target.
  • the method for producing the thin film is not particularly limited, and sputtering, vacuum deposition, and ion plating can be used as PVD methods.
  • CVD Chemical Vapor Deposition
  • ALD Advanced Layer Deposition
  • FIG. 1 is a schematic cross-sectional view of a switch element according to an embodiment of the present invention.
  • the switch element 10 includes a first electrode 1, a second electrode 2, and a switch layer 3 disposed on the main surface of the first electrode 1.
  • the second electrode 2 is disposed in a position facing the first electrode 1.
  • the switch layer 3 is disposed between the first electrode 1 and the second electrode 2.
  • the switch element 10 of this embodiment includes a switch layer 3 and a first electrode 1 disposed on the switch layer 3.
  • the switch element 10 of this embodiment preferably includes a second electrode 2 disposed in a position facing the first electrode 1 across the switch layer 3.
  • the switch layer 3 contains Te and is made of a variable resistance material having an OFF current density of 3.1 ⁇ 10 2 A/cm 2 or less, where the OFF current density is the current density when a voltage of 1 ⁇ 2 of the threshold voltage is applied.
  • the switch element 10 of this embodiment can be suitably used in a cross-point type memory device or a BiCS (Bit-Cost Scalable) type memory device, which will be described later.
  • a BiCS type memory device it is preferable that the switch element 10 of this embodiment has the first electrode 1 disposed on the outer peripheral surface of the switch layer 3, and the second electrode 2 disposed on the inner peripheral surface of the switch layer 3.
  • the first electrode 1 and the second electrode 2 can be made of an inorganic material.
  • the inorganic material can be a metal material or a ceramic material.
  • the first electrode 1 and the second electrode 2 are preferably made of at least one material selected from tungsten, titanium, copper, platinum, tungsten nitride, and titanium nitride. Tungsten, titanium, copper, and platinum are preferred as metal materials. Furthermore, tungsten nitride and titanium nitride are preferred as ceramic materials.
  • the upper limits of the areas of the first electrode 1 and the second electrode 2 are, for example, 1,000,000 nm2 or less, 562,500 nm2 or less, 250,000 nm2 or less, 62,500 nm2 or less, 10,000 nm2 or less, 6,400 nm2 or less, 2,500 nm2 or less, and particularly preferably 1,600 nm2 or less.
  • the lower limits of the areas of the first electrode 1 and the second electrode 2 are not particularly limited, but may be 1 nm2 or more, particularly 2 nm2 or more, respectively, from the viewpoint of manufacturing costs.
  • the upper limit of the contact area between the first electrode 1 and the switch layer 3 or the contact area between the second electrode 2 and the switch layer 3 is preferably 1,000,000 nm 2 or less, 562,500 nm 2 or less, 250,000 nm 2 or less, 62,500 nm 2 or less, 10,000 nm 2 or less, 6,400 nm 2 or less, 2,500 nm 2 or less, and particularly preferably 1,600 nm 2 or less. This is advantageous for increasing the capacity of the memory device.
  • the lower limit of the contact area between the first electrode 1 and the switch layer 3 or the contact area between the second electrode 2 and the switch layer 3 is not particularly limited, but may be 1 nm 2 or more, particularly 2 nm 2 or more, from the viewpoint of manufacturing costs.
  • the contact area between the electrode and the switch layer 3 may be such that at least one of the contact area between the first electrode 1 and the switch layer 3 or the contact area between the second electrode 2 and the switch layer 3 satisfies the above value, and it is more preferable that both contact areas satisfy the above value.
  • the switch layer 3 is disposed in contact with at least one electrode.
  • the switch layer 3 is preferably disposed on the first electrode 1.
  • the first electrode 1 is preferably disposed on the switch layer 3. It is also preferable to have a second electrode 2 disposed in a position facing the first electrode 1 with the switch layer 3 in between.
  • the thickness of the switch layer 3 can be designed appropriately according to the desired threshold voltage.
  • the upper limit of the thickness of the switch layer 3 is, for example, preferably 300 nm or less, 200 nm or less, and particularly preferably 100 nm or less. If the thickness is too large, the threshold voltage is likely to be too high.
  • the lower limit of the thickness of the switch layer 3 is, for example, preferably 1 nm or more, 2 nm or more, 5 nm or more, 10 nm or more, 30 nm or more, and particularly preferably more than 50 nm.
  • the ionicity r ⁇ ' and hybridization r ⁇ -1 of the switch layer 3 satisfy the desired values. More specifically, it is preferable that the ionicity r ⁇ ' of the switch layer 3 is 0.05 or more.
  • the upper limit of the ionicity r ⁇ ' is not particularly limited, but can be, for example, 0.30 or less, 0.25 or less, and particularly 0.20 or less.
  • the hybridization r ⁇ -1 of the switch layer 3 is 2.0 or less, and particularly 1.9 or less.
  • the lower limit of the hybridization r ⁇ -1 is not particularly limited, but is, for example, 1.0 or more, 1.1 or more, 1.2 or more, and particularly 1.3 or more.
  • a voltage is applied to the switch element 10 at different temperatures, and the current value at that time is measured.
  • the range of the temperature and applied voltage at this time is not limited, but the temperature can be, for example, 30° C. to 80° C., and the applied voltage can be 0 V to 0.30 V.
  • the carrier activation energy can be calculated using the following formula (3) from the current value at an arbitrary voltage value and the temperature at the time of measurement.
  • I is a current
  • Ea is a carrier activation energy
  • k is a Boltzmann constant
  • T an absolute temperature
  • C is a constant.
  • the switch element 10 of this embodiment preferably exhibits a tendency for its threshold voltage to increase with heating.
  • the threshold voltage of the switch element 10 at 80°C is preferably 1.05 times or more, and particularly 1.1 times or more, the threshold voltage at room temperature of 25°C.
  • the Schottky barrier height of the switch element 10 at 80° C. is 1.01 times or more, particularly 1.02 times or more, of the Schottky barrier height at 30° C.
  • the Schottky barrier height ⁇ B can be calculated by the following formula (4).
  • I s is the saturation current
  • A is the contact area
  • a * is the Richardson constant
  • q is the elementary charge
  • k is the Boltzmann constant
  • T is the absolute temperature.
  • ⁇ Memory element> 2 is a schematic cross-sectional view of a memory element according to an embodiment of the present invention.
  • the memory element 21 includes a first electrode 11, a second electrode 12, and a switch memory layer 4 disposed on the main surface of the first electrode 11.
  • the second electrode 12 is disposed in a position facing the first electrode 11.
  • the switch memory layer 4 is disposed between the first electrode 11 and the second electrode 12.
  • the memory element 21 of this embodiment includes the switch memory layer 4, the first electrode 11 disposed on one main surface of the switch memory layer 4, and the second electrode 12 disposed on the other main surface of the switch memory layer 4.
  • the switch memory layer 4 is made of a resistance change film.
  • the first electrode 11 and the second electrode 12 may be made of an inorganic material.
  • the inorganic material that may be used include metal materials and ceramic materials.
  • the metal material that may be used include tungsten, titanium, copper, and platinum.
  • the ceramic material that may be used include tungsten nitride and titanium nitride.
  • the thickness of the first electrode 11 and the second electrode 12 can be designed as appropriate.
  • the thickness of the first electrode 11 and the second electrode 12 is 200 nm or less, 100 nm or less, 80 nm or less, 60 nm or less, and particularly 50 nm or less, respectively.
  • the lower limit of the thickness of the first electrode 11 and the second electrode 12 is, for example, 1 nm or more, and particularly 2 nm or more.
  • the memory element 21 is a resistance change memory element, and includes a switch memory layer 4 that has a memory function and a switch element function. For example, by applying a voltage equal to or higher than a predetermined voltage to the switch memory layer 4, it can be changed to a low resistance state LR1 and information can be recorded. In addition, by decreasing the applied voltage from the low resistance state LR1, it becomes a high resistance state HR1 in which information is recorded, and further, by applying a read voltage without performing an erase operation, it changes to a low resistance state LR2. On the other hand, when a read voltage is applied in a high resistance state in which no information is recorded or an erase operation has been performed, it becomes a high resistance state HR2.
  • information can be recorded by associating 1 and 0 with LR2 and HR2, respectively.
  • the operation method is not limited to the above-mentioned method. For example, if the applied voltage is set to 0 after recording information and a read voltage is applied, it becomes LR2. On the other hand, if a read voltage is applied after performing an erase operation, it becomes HR2, and information can be recorded by associating 1 and 0 with each.
  • the upper limit of the area of the first electrode 11 and the second electrode 12 is, for example, 1,000,000 nm2 or less, 562,500 nm2 or less, 250,000 nm2 or less, 62,500 nm2 or less, 10,000 nm2 or less, 6,400 nm2 or less, 2,500 nm2 or less, and particularly preferably 1,600 nm2 or less.
  • the lower limit of the area of the first electrode 11 and the second electrode 12 is not particularly limited, but may be 1 nm2 or more, particularly 2 nm2 or more, from the viewpoint of manufacturing costs.
  • the upper limit of the contact area between the first electrode 11 and the switch memory layer 4 or the contact area between the second electrode 12 and the switch memory layer 4 is preferably 1,000,000 nm 2 or less, 562,500 nm 2 or less, 250,000 nm 2 or less, 62,500 nm 2 or less, 10,000 nm 2 or less, 6,400 nm 2 or less, 2,500 nm 2 or less, and particularly preferably 1,600 nm 2 or less. This is likely to be advantageous for increasing the capacity of the memory device.
  • the lower limit of the contact area between the first electrode 11 and the switch memory layer 4 and/or the contact area between the second electrode 12 and the switch memory layer 4 is not particularly limited, but may be, for example, 1 nm 2 or more, particularly 2 nm 2 or more, from the viewpoint of manufacturing costs.
  • the contact area between the electrodes and the switch memory layer 4 needs to be such that at least one of the contact area between the first electrode 11 and the switch memory layer 4 or the contact area between the second electrode 12 and the switch memory layer 4 satisfies the above value, and it is more preferable that both contact areas satisfy the above value.
  • the storage device of the present embodiment preferably includes a switch element, and more preferably includes a switch element and a memory element.
  • the storage device of the present invention is preferably made of a laminate in which the switch element and the memory element are laminated.
  • the storage device of the present embodiment is a storage device including a laminate in which the switch element and the memory element are laminated, the switch element includes a switch layer and a first electrode disposed on the switch layer, the switch layer is made of a resistance change material having an OFF current density of 3.1 ⁇ 10 2 A/cm 2 or less when the current density when a voltage of 1 ⁇ 2 of the threshold voltage is applied is taken as the OFF current density, and the memory element is preferably made of any one of a resistance change memory element, a magnetoresistance memory element, a phase change memory element, and a ferroelectric memory element.
  • FIG. 3 is a schematic three-dimensional view of a memory device according to a first embodiment of the present invention
  • FIG. 4 is a schematic three-dimensional view of an enlarged memory device according to the first embodiment of the present invention.
  • the memory device 100 includes a switch element 10, a memory element 20, a word line 30, and a bit line 40.
  • the bit line 40 is orthogonal to the word line 30 in a planar view.
  • the switch element 10 and the memory element 20 are disposed at the intersection of the word line 30 and the bit line 40 in a planar view.
  • the memory device 100 of this embodiment is a so-called cross-point type memory device.
  • FIG. 5 is a schematic three-dimensional diagram of a modified example of the memory device according to the first embodiment of the present invention.
  • the memory device 200 includes a switch element 10, a memory element 20, a word line 30, and a bit line 40.
  • the bit line 40 is disposed in a through hole provided in the word line 30.
  • the memory element 20 and the switch element 10 are disposed on the outer periphery of the bit line 40.
  • the switch element 10 has a first electrode 1 disposed on the outer periphery of the switch layer 3, and a second electrode 2 disposed on the inner periphery facing the first electrode 1 with the switch layer 3 in between.
  • the memory device 200 of this modified example is a so-called BiCS type memory device.
  • the memory device of the present invention is not limited to a cross-point type memory device, and may be various types of memory devices.
  • the memory element 20 can be any memory element, such as a resistive memory element, a magnetoresistive memory element, a phase change memory element, or a ferroelectric memory element. Preferred embodiments of each memory element are described below.
  • the resistance change memory element includes a resistance change layer. More specifically, the resistance change memory element preferably includes a stacked body in which a resistance change layer is sandwiched between an upper electrode and a lower electrode.
  • the resistance change layer is preferably made of a metal oxide material, a metal nitride material, or a chalcogenide material.
  • the metal oxide material is preferably at least one selected from, for example, NiO x , NbO x , TiO x , TaO x , HfO x , ZrO x , MoO x , WO x , and Pr 1-x Ca x MnO 3 (PCMO).
  • the metal nitride material is preferably at least one selected from, for example, SiN x , AlN x , ZrN x , NiN x , CuN x , and CrN x .
  • the chalcogenide material is preferably at least one selected from the group consisting of Ge-Te, Sb-Te, Ge-Sb-Te, Si-Sb-Te, Ge-Ga-Te, In-Sb-Te, Ge-Se-As, and Ge-Se-As-Te.
  • the resistance change layer may be made of carbon nanotubes.
  • the upper electrode and/or the lower electrode are preferably made of at least one selected from tungsten, titanium, copper, platinum, tungsten nitride, and titanium nitride.
  • Tungsten, titanium, copper, and platinum are preferred as metal materials.
  • Tungsten nitride and titanium nitride are preferred as ceramic materials.
  • the magnetoresistive memory element includes a laminate (TMR element) in which an insulating layer is sandwiched between ferromagnetic layers.
  • the insulating layer is made of an insulator, and is preferably made of at least one material selected from, for example, MgO, CaO, SrO, and Al 2 O 3.
  • the insulating layer preferably has a thickness of 0.1 nm to 3 nm.
  • the ferromagnetic layer is made of a ferromagnetic material, and is preferably made of at least one material selected from, for example, CoFeB, FeB, NiFe, MnIr, Fe, CoPt, CoNi, Co, Ni, Pt, Ni, and Mn.
  • the ferroelectric memory element includes a ferroelectric layer. More specifically, the ferroelectric memory element preferably includes a laminate in which a ferroelectric layer is sandwiched between an upper electrode and a lower electrode.
  • the ferroelectric layer is preferably made of a ferroelectric material containing hafnium oxide, for example, hafnium oxide to which at least one selected from Si, Zr, Ge, Gd, La, Y, or Yb is added.
  • the ferroelectric layer may also be made of at least one selected from lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), and bismuth ferrite (BFO).
  • PZT lead zirconate titanate
  • SBT strontium bismuthate tantalate
  • BFO bismuth ferrite
  • the phase change memory element is a memory layer made of a phase change material. More specifically, the phase change memory element preferably includes a laminate in which a phase change layer is sandwiched between an upper electrode and a lower electrode.
  • the phase change layer is preferably made of a chalcogenide material.
  • the chalcogenide material is preferably at least one selected from, for example, Ge-Te, Sb-Te, Ge-Sb-Te, Si-Sb-Te, Ge-Ga-Te, In-Sb-Te, Cu-Ge-Te, Cr-Ge-Te, Mn-Te, Ge-Se-As, and Ge-Se-As-Te.
  • the storage device of the present invention is not limited to a configuration having a switch layer and a memory element separately.
  • the storage device of the present invention may have a configuration having only a switch element.
  • the switch element can function as a switch element and a memory element.
  • the storage device of this embodiment preferably has a resistance change memory element (memory element 21) having the above-mentioned memory function and switch element function.
  • a resistance change memory element having a memory function and a switch element function
  • the storage device of this embodiment may have any switch element.
  • FIG. 6 is a schematic three-dimensional diagram of a memory device according to a second embodiment of the present invention.
  • the memory device 101 includes a memory element 21, a word line 30, and a bit line 40.
  • the bit line 40 is perpendicular to the word line 30 in a planar view.
  • the memory element 21 is disposed at the intersection of the word line 30 and the bit line 40 in a planar view.
  • the memory device 101 of this embodiment is a so-called cross-point type memory device.
  • FIG. 7 is a schematic three-dimensional diagram of a modified example of a memory device according to the second embodiment of the present invention.
  • the memory device 201 includes a memory element 21, a word line 30, and a bit line 40.
  • the bit line 40 is disposed in a through hole provided in the word line 30.
  • the memory element 21 is disposed on the outer periphery of the bit line 40.
  • the memory device 201 of this embodiment is a so-called BiCS type memory device.
  • the memory device is not limited to a cross-point type memory device, and may be various types of memory devices.
  • the examples and comparative examples were prepared as follows. First, a quartz glass ampoule was evacuated while being heated, and then the raw materials were mixed to obtain the composition shown in Table 1 and placed in the quartz glass ampoule. Next, the quartz glass ampoule was sealed with an oxygen burner. Next, the sealed quartz glass ampoule was placed in a melting furnace, and the temperature was raised to 650°C to 1000°C at a rate of 10°C to 40°C/hour, and then held for 6 to 12 hours. During the holding time, the quartz glass ampoule was turned upside down and the molten material was stirred. Finally, the quartz glass ampoule was removed from the melting furnace and rapidly cooled to room temperature to obtain a variable resistance material.
  • the oxygen content of the obtained resistance change material was measured using the inert gas fusion-infrared absorption method. The results are shown in Table 1.
  • a switch element was fabricated using the variable resistance material as a target.
  • a W electrode with a thickness of 50 nm was formed on a Si/SiO 2 substrate.
  • a SiO 2 insulating layer with a thickness of 100 nm was formed on the W electrode.
  • a ⁇ 500 nm hole was formed in the SiO 2 insulating layer and the W electrode layer using a focus ion beam device (JEOL, JIB-4600F).
  • JEOL, JIB-4600F focus ion beam device
  • a variable resistance material with a thickness of 150 nm was formed in the formed hole to form a switch layer.
  • a W electrode with a thickness of 150 nm was further formed on the switch layer to fabricate a switch element.
  • the film was formed by Ar sputtering under a reduced pressure atmosphere.
  • the obtained switch element was used to determine the OFF current density, ON current density, ON/OFF current ratio, and threshold voltage. The results are shown in Table 2.
  • the OFF current density, ON current density, ON/OFF current ratio, and threshold voltage were determined as follows. First, a voltage of 0V to 10V was applied to the switch element, and the current value flowing through the switch element and the threshold voltage were measured. The voltage applied at this time is not limited to DC voltage, AC voltage, pulse voltage, etc., but pulse voltage was used to prevent heat accumulation in the switch element.
  • the threshold voltage was determined as the voltage value at which the electrical resistance value changes suddenly from a high resistance state to a low resistance state.
  • the OFF current density was determined as the current value (OFF current value) flowing when a voltage of 1/2 the threshold voltage was applied divided by the contact area with the electrode.
  • the ON current density was determined as the current value (ON current value) flowing when a voltage equal to or higher than the threshold voltage was applied divided by the contact area with the electrode.
  • the ON/OFF current ratio was determined by dividing the ON current value by the OFF current value.
  • a thin film sample for measuring carrier mobility was prepared by forming a 150 nm thick variable resistance material on a Si/ SiO2 substrate by Ar sputtering.
  • the carrier mobility of the obtained thin film sample was measured at 30°C using a resistivity/Hall measurement system (ResiTest 8308, manufactured by Toyo Corporation). The results are shown in Table 2.
  • FIG. 8 A graph plotting the ionicity r ⁇ ' and hybridization r ⁇ -1 of the switch layer is shown in Fig. 8. As shown in Fig. 8, the ionicity r ⁇ ' of the switch layer in the example was 0.05 or more, and the hybridization r ⁇ -1 was 2.0 or less.
  • the variable resistance materials of Examples 1 to 7 had carrier mobility of 2.6 ⁇ 10 -3 cm 2 /Vs or less and OFF current density of 2.55 ⁇ 10 2 A/cm 2 or less. Furthermore, the logarithmic value log 10 x of the ON/OFF current ratio x was 4.3 to 6.6. On the other hand, the carrier mobility of Comparative Example 1 was large at 5.1 ⁇ 10 -3 cm 2 /Vs and the OFF current density was large at 3.57 ⁇ 10 2 A/cm 2. Furthermore, the logarithmic value log 10 x of the ON/OFF current ratio x was small at 3.9.
  • Table 3 shows the change in carrier activation energy when a voltage is applied to the switching element
  • Table 4 shows the relationship between the absolute temperature of the switching element and the Schottky barrier height.
  • Table 3 shows the change in carrier activation energy when a voltage of 0.15 V is applied to the switching layer is a (eV)
  • the carrier activation energy when a voltage of 0.30 V is applied to the switching layer is b (eV)
  • a/b ⁇ 1 was satisfied.
  • the Schottky barrier height ⁇ B80°C at 80°C was 1.04 times the Schottky barrier height ⁇ B30°C at 30°C.
  • the resistance change material of the present invention can be suitably used for switch elements that can be used in memory devices such as resistance change type, magnetoresistance type, phase change type, and ferroelectric type.

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JP2010519762A (ja) * 2007-02-27 2010-06-03 インターナショナル・ビジネス・マシーンズ・コーポレーション クロスポイントに基づくメモリ・アレイ・アーキテクチャのための整流素子
JP2010287872A (ja) * 2009-02-27 2010-12-24 Sharp Corp 不揮発性半導体記憶装置及びその製造方法
JP2015135917A (ja) * 2014-01-17 2015-07-27 ソニー株式会社 スイッチ素子および記憶装置
JP2018164085A (ja) * 2017-03-27 2018-10-18 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 可変抵抗物質層を含むメモリ素子

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JP2010519762A (ja) * 2007-02-27 2010-06-03 インターナショナル・ビジネス・マシーンズ・コーポレーション クロスポイントに基づくメモリ・アレイ・アーキテクチャのための整流素子
JP2010287872A (ja) * 2009-02-27 2010-12-24 Sharp Corp 不揮発性半導体記憶装置及びその製造方法
JP2015135917A (ja) * 2014-01-17 2015-07-27 ソニー株式会社 スイッチ素子および記憶装置
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