WO2024202681A1 - 基板装置、電子装置、電子機器、電子装置の製造方法及び電子機器の製造方法 - Google Patents

基板装置、電子装置、電子機器、電子装置の製造方法及び電子機器の製造方法 Download PDF

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Publication number
WO2024202681A1
WO2024202681A1 PCT/JP2024/005645 JP2024005645W WO2024202681A1 WO 2024202681 A1 WO2024202681 A1 WO 2024202681A1 JP 2024005645 W JP2024005645 W JP 2024005645W WO 2024202681 A1 WO2024202681 A1 WO 2024202681A1
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Prior art keywords
substrate
wiring
electronic device
dies
wiring layer
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Ceased
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PCT/JP2024/005645
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English (en)
French (fr)
Japanese (ja)
Inventor
浩永 安川
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to CN202480021399.3A priority Critical patent/CN120958975A/zh
Priority to JP2025509915A priority patent/JPWO2024202681A1/ja
Priority to KR1020257032164A priority patent/KR20250165602A/ko
Priority to EP24778826.8A priority patent/EP4693401A1/en
Publication of WO2024202681A1 publication Critical patent/WO2024202681A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/231—Arrangements for cooling characterised by their places of attachment or cooling paths
    • H10W40/242—Arrangements for cooling characterised by their places of attachment or cooling paths comprising thermal conductors between chips and the and the arrangements for cooling, e.g. compliant heat-spreaders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/7295—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors on the rear surface of insulating package substrates, interposers or RDLs, for connection outside of the package, e.g. ball grid array [BGA] bumps

Definitions

  • the technology disclosed herein (hereinafter also referred to as "the technology”) relates to a substrate device, an electronic device, an electronic device, a method for manufacturing an electronic device, and a method for manufacturing an electronic device.
  • substrate devices are known that electrically connect multiple dies via a bridge structure (wiring layer) arranged in a cavity of a wiring substrate (see, for example, Patent Documents 1 and 2).
  • the bridge structure is separate (a separate component) from the wiring substrate and multiple dies.
  • the main objective of this technology is to provide a substrate device that includes a wiring layer that electrically connects multiple dies, and that can improve productivity while suppressing degradation of electrical characteristics.
  • the present technology comprises a wiring board and a wiring layer that is protruding from one surface of the wiring board and electrically connects a plurality of dies;
  • a substrate device is provided.
  • the one surface may be a flat surface.
  • the wiring substrate and each of the plurality of dies may be connected via a first bonding portion, and the wiring layer and each of the plurality of dies may be connected via a second bonding portion.
  • the second joint may be smaller than the first joint.
  • Each of the first and second bonds may be a bump.
  • the first and second joints may be metal joints.
  • a ratio of the pitch of the first joint portions to the pitch of the second joint portions may be greater than or equal to 2.0 and less than or equal to 5.0.
  • the wiring layer may have a shape in a plan view corresponding to a planar arrangement of the at least two dies.
  • the shape in plan view may be a rectangle, an L-shape, a T-shape, a cross shape, a U-shape, a curved shape, or a combination of at least two of these.
  • the substrate device may include a plurality of the wiring layers.
  • the wiring layer may have an insulating film and a wiring disposed inside the insulating film, and the insulating film may be made of a dielectric material.
  • the wiring board has a substrate and wiring disposed inside the substrate, and the substrate may include any one of an organic substrate, a FOWLP or FOPLP, a ceramic substrate, and a glass substrate.
  • the electronic device may further include a heat spreader disposed across the surfaces of the plurality of dies opposite to the wiring substrate.
  • the present invention may further comprise a substrate device including a plurality of dies, a wiring substrate, and a wiring layer protruding from one surface of the wiring substrate and electrically connecting at least two of the plurality of dies, the plurality of dies being electrically connected to each other, the wiring substrate being provided with a ...
  • the technique includes: a substrate device including a wiring substrate and a wiring layer protruding from one surface of the wiring substrate and electrically connecting at least two of the plurality of dies; an electronic device comprising: a circuit board on which the electronic device is mounted; An electronic device comprising: The present technology includes a step of forming a wiring layer in a convex shape on a wiring substrate; connecting each of the plurality of dies to the wiring substrate via a first bonding portion and connecting each of the plurality of dies to the wiring layer via a second bonding portion; Also provided is a method for manufacturing an electronic device, comprising: The forming step may include a sub-step of forming a layer on the wiring board, the layer having wiring formed within a portion of an in-plane direction of a photosensitive dielectric film, and a sub-step of removing another portion of the layer in the in-plane direction of the photosensitive dielectric film by etching.
  • the forming process may include a cycle repeated multiple times, the cycle including a sub-process of stacking a dielectric film on the wiring substrate, a sub-process of etching the dielectric film to form grooves, a sub-process of forming a metal film on the dielectric film in which the grooves have been formed, and a sub-process of grinding the metal film to form wiring.
  • the present technology includes a step of forming a wiring layer in a convex shape on a wiring substrate; a step of connecting each of the plurality of dies to the wiring substrate via a first bonding portion and connecting each of the plurality of dies to the wiring layer via a second bonding portion to generate an electronic device; and a step of mounting the electronic device on a circuit substrate. Also provided is a method for manufacturing an electronic device, including:
  • 1 is a diagram illustrating a schematic cross-sectional configuration of an electronic device according to an embodiment of the present technology.
  • 1 is a diagram illustrating in detail a cross-sectional configuration of a portion of an electronic device according to an embodiment of the present technology.
  • 1 is a diagram illustrating a schematic planar configuration of an electronic device according to an embodiment of the present technology;
  • 1 is a diagram illustrating in detail a planar configuration near a convex wiring layer of an electronic device according to an embodiment of the present disclosure;
  • 1A to 1C are diagrams for explaining a method for forming bumps of different sizes by the ball mounting method (part 1).
  • 11A to 11C are diagrams for explaining a method of forming bumps of different sizes by the ball mounting method (part 2).
  • 1A to 1C are diagrams for explaining a method of forming bumps of different sizes by a paste printing method.
  • 1A to 1C are diagrams for explaining a method of forming bumps of different sizes by plating.
  • 9A and 9B are diagrams each illustrating a planar configuration of an electronic device according to a first example of an embodiment of the present technology, and a planar configuration of an electronic device according to a second example of an embodiment of the present technology.
  • 10A and 10B are diagrams each illustrating a planar configuration of an electronic device according to a third embodiment of the present technology, and a planar configuration of an electronic device according to a fourth embodiment of the present technology, respectively.
  • 11A and 11B are diagrams illustrating schematic planar configurations of an electronic device according to Example 5 and Example 6 of an embodiment of the present technology; 2 is a flowchart for explaining an example of a method for manufacturing the electronic device of FIG. 1 .
  • 13A and 13B are cross-sectional views showing steps of a method for manufacturing the electronic device of FIG. 14A and 14B are cross-sectional views illustrating steps in a method for manufacturing the electronic device of FIG. 15A and 15B are cross-sectional views illustrating steps in a method for manufacturing the electronic device of FIG. 16A and 16B are cross-sectional views showing steps of a method for manufacturing the electronic device of FIG. 17A and 17B are cross-sectional views illustrating steps in a method for manufacturing the electronic device of FIG.
  • FIG. 1 is a diagram illustrating a schematic cross-sectional configuration of an electronic device including an electronic device according to an embodiment of the present technology.
  • 20 is a flowchart illustrating an example of a method for manufacturing the electronic device of FIG. 19.
  • 21A and 21B are cross-sectional views showing the steps of the method for manufacturing the electronic device of FIG. 13 is a diagram illustrating in detail a cross-sectional configuration of a portion of an electronic device according to Example 7 of an embodiment of the present technology.
  • FIG. 13 is a diagram illustrating in detail a cross-sectional configuration of a portion of an electronic device according to Example 8 of an embodiment of the present technology.
  • FIG. 1 is a diagram illustrating a schematic cross-sectional configuration of an electronic device including an electronic device according to an embodiment of the present technology.
  • 20 is a flowchart illustrating an example of a method for manufacturing the electronic device of FIG. 19.
  • FIG. 13 is a diagram illustrating in detail a cross-sectional configuration of a portion of an electronic device according to Example 9 of an embodiment of the present technology.
  • FIG. 13 is a diagram illustrating in detail a cross-sectional configuration of a portion of an electronic device according to a tenth example of an embodiment of the present technology.
  • FIG. 13 is a diagram illustrating in detail a cross-sectional configuration of a portion of an electronic device according to an eleventh example of an embodiment of the present technology.
  • 13 is a diagram illustrating in detail a cross-sectional configuration of a portion of an electronic device according to Example 12 of an embodiment of the present technology.
  • 1 is a block diagram showing functions of an HPC, which is an example of an electronic device including an electronic device according to an embodiment of the present technology.
  • FIG. 30 is a diagram illustrating a configuration example of a node (computing server) in FIG. 28.
  • 1 is a diagram showing a moving object equipped with an electronic device including an electronic device according to an embodiment of the present technology
  • 1 is a diagram illustrating a schematic cross-sectional configuration of a substrate device included in an electronic device according to an embodiment of the present technology.
  • 32A and 32B are cross-sectional and plan views, respectively, of each step of the damascene process.
  • 33A and 33B are cross-sectional and plan views, respectively, of each step of the damascene process.
  • 34A and 34B are cross-sectional and plan views, respectively, of each step of the damascene process.
  • FIG. 1 is a functional block diagram of an example of an electronic device including an electronic device to which the present technology is applied.
  • 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit;
  • the inventor therefore, after extensive research, succeeded in eliminating the above disadvantages by forming a convex wiring layer integrally with the wiring board in the board device, i.e. by having the wiring layer protrude from one surface of the wiring board. Furthermore, in addition to the board device incorporating this new knowledge, the inventor also developed an electronic device including the board device, and an electronic device including the electronic device.
  • FIG. 1 is a diagram that shows a schematic cross-sectional configuration of an electronic device 10 according to an embodiment of the present technology.
  • FIG. 2 is a diagram that shows in detail a cross-sectional configuration of a part of the electronic device 10 according to an embodiment of the present technology.
  • FIG. 2 is a diagram that shows in detail a part surrounded by a dashed line in FIG. 1.
  • FIG. 3 is a diagram that shows in schematic planar configuration of the electronic device 10 according to an embodiment of the present technology.
  • FIG. 4 is a diagram that shows in detail a planar configuration near a convex wiring layer of the electronic device 10 according to an embodiment of the present technology.
  • FIG. 4 is a diagram that shows in detail a cross section (transverse section) of a part surrounded by a dashed line in FIG. 3.
  • the electronic device 10-1 includes a substrate device 50 (see FIG. 31) and a number of dies 200, as shown in FIG. 1.
  • the die 200 is an IC chip (a semiconductor chip on which an integrated circuit is formed), such as an imaging chip, a logic chip, a memory chip, a CPU chip, an AI chip, or an interface chip.
  • IC chip a semiconductor chip on which an integrated circuit is formed
  • the substrate device 50 includes a wiring substrate 100 and a wiring layer 300 that protrudes from one surface (top surface) of the wiring substrate 100 and electrically connects a plurality of dies 200.
  • the wiring layer 300 is integrally formed in a convex shape on one surface (top surface) of the wiring substrate 100. Therefore, in this specification, the wiring layer 300 is also referred to as a "convex wiring layer.”
  • One surface (top surface) of the wiring board 100 is flat.
  • the wiring board 100 does not have a cavity in which a conventional bridge structure would be disposed, and the convex wiring layer protrudes upward from the flat surface.
  • the substrate device 50 has, as an example, multiple (e.g., four) convex wiring layers.
  • each of the first and second joints J1 and J2 is provided in multiple (multiple) numbers.
  • Each of the first and second joints J1, J2 is a bump, for example.
  • the bump is, for example, a solder ball.
  • the bump serving as the second joint J2 is smaller than the bump serving as the first joint J1. This allows the wiring connecting the dies 200 to be highly dense and the wiring length to be shortened.
  • the wiring board 100 has a substrate 100a and an internal wiring 100b arranged inside the substrate 100a.
  • the substrate 100a is an insulating film made of a dielectric material such as a prepreg in which a fiber cloth is impregnated with a resin, Ajinomoto Build-up Film (ABF, registered trademark), ceramic, glass, PI (Polyimide), PBO (Polybenzoxazole), SiO 2 , SiN, or SiON.
  • the wiring 100b is made of a metal such as Al, Cu, or W.
  • the internal wiring 100b includes a horizontal wiring 100b1 and a via 100b2.
  • the wiring board 100 has a multilayer structure in which an interlayer insulating film, which is a part of the thickness direction of the substrate 100a, and a horizontal wiring 100b1 are alternately stacked.
  • the horizontal wirings 100b1 adjacent to each other vertically are connected to each other via a via 100b2.
  • Each wiring layer 300 has an insulating film 300a and an internal wiring 300b arranged inside the insulating film 300a.
  • the insulating film 300a is an insulating film made of a dielectric material such as PI (Polyimide), PBO (Polybenzoxazole), SiO 2 , SiN, or SiON.
  • the internal wiring 300b is made of a metal such as Al, Cu, or W.
  • the internal wiring 300b includes a horizontal wiring 300b1 and a via 300b2.
  • each wiring layer 300 has a multilayer structure in which an interlayer insulating film, which is a part of the thickness direction of the insulating film 300a, and a horizontal wiring 300b1 are alternately stacked.
  • the horizontal wirings 300b2 adjacent to each other are connected to each other via the via 300b2.
  • the die side connection terminal T21 provided on the underside of each die 200 at a position facing the wiring substrate 100 is connected to the substrate side connection terminal T12 provided on the upper surface of the wiring substrate 100 at a position corresponding to the die side connection terminal T21 via a first joint J1.
  • the die side connection terminal T21 is connected to the circuit of the die 200.
  • the substrate side connection terminal T12 is connected to the internal wiring 100b of the wiring substrate 100.
  • the die side connection terminal T23 provided on the underside of each die 200 at a position facing the wiring layer 300 and the wiring layer side connection terminal T32 provided on the upper surface of the wiring layer 300 at a position corresponding to the die side connection terminal T23 are connected via a second joint J2.
  • the die side connection terminal T23 is connected to the circuit of the die 200.
  • the wiring layer side connection terminal T32 is connected to the internal wiring 300b of the wiring layer 300.
  • a substrate-side connection terminal T13 is provided on the upper surface of the substrate 100a in the area where the wiring layer 300 is formed.
  • the substrate-side connection terminal T13 is connected to the internal wiring 100b of the wiring substrate 100 and the internal wiring 300b of the wiring layer 300.
  • a substrate-side connection terminal T10 for connection to a circuit board 800 (see FIG. 19).
  • the substrate-side connection terminal T10 is connected to the internal wiring 100b.
  • a solder resist 500 so as to expose the substrate-side connection terminal T10.
  • the height of the convex wiring layer is, for example, 60 ⁇ m to 70 ⁇ m.
  • the pitch (bump pitch) of the second joint J2 is, for example, 20 ⁇ m or more and 50 ⁇ m or less (e.g., 40 ⁇ m), and the pitch (bump pitch) of the first joint J1 is 100 ⁇ m or more.
  • the size of the convex wiring layer and the pitch of each bump may be smaller or larger. In any case, it is preferable that the ratio of the pitch of the first joint J1 to the pitch of the second joint J2 is 2.0 or more and 5.0 or less.
  • the bump layout of the convex wiring layer is staggered to facilitate wiring with surface wiring, but it may also be arranged in a grid, for example.
  • the dies 200 may be connected to each other using layers other than the surface layer, such as the second and third layers.
  • the underfill 400 is filled around the first joint J1 between the wiring substrate 100 and the multiple dies 200, and around the second joint J2 between the wiring layer 300 and the multiple dies 200. This improves the bump connection reliability against temperature stress caused by the operation and stop of each die 200.
  • the underfill 400 is mainly made of epoxy resin as a base material and may contain a filler such as silicon oxide with a small linear expansion coefficient. Note that the underfill 400 is not essential for the electronic device 10.
  • Methods for forming the first and second bonding portions J1 and J2 that is, bumps of different sizes, are roughly classified into three types: a ball mounting method, a paste printing method, and a plating method.
  • Figure 5 is a diagram for explaining a method for forming bumps of different sizes using the ball mounting method (part 1).
  • a metal mask MM is arranged on a substrate S and has multiple types (e.g., two types) of openings of different sizes.
  • a brush B is used to insert solder balls SB of a size corresponding to the size of the opening into each opening, thereby forming solder bumps of different sizes on the substrate S.
  • Figure 6 is a diagram for explaining a method for forming bumps of different sizes using the ball mounting method (part 2).
  • solder balls SB of sizes corresponding to the sizes of each of the multiple types of openings are ejected from the solder ball mounting head of a solder ball mounter arranged on a substrate onto a metal mask MM having multiple types (e.g., two types) of openings of different sizes, thereby forming solder bumps of different sizes on the substrate.
  • FIG. 7 is a diagram for explaining a method for forming bumps of different sizes using a paste printing method.
  • a metal mask MM having multiple types (e.g., two types) of openings of different sizes is used as a mask to print solder paste SP onto a substrate S using a squeegee SQ, and then reflow is performed to form solder bumps of different sizes on the substrate S.
  • FIG. 8 is a diagram for explaining a method for forming bumps of different sizes by plating.
  • a photoresist PR having multiple types (e.g., two types) of openings of different sizes is used as a mask to grow solder paste SP on a substrate S by electrolytic plating or electroless plating, and then reflowing, thereby forming solder bumps of different sizes on the substrate S.
  • Each wiring layer 300 preferably has a shape in plan view that corresponds to the planar arrangement of at least two dies 200 corresponding to the wiring layer 300, as in the following Examples 1 to 6.
  • Examples of the shape in plan view include a rectangular shape, an L-shape, a T-shape, a cross shape, a U-shape, a curved shape, or a combination of at least two of these shapes.
  • Example 1 9A is a diagram illustrating a schematic planar configuration of an electronic device 10-1 according to a first embodiment of the present technology.
  • a large die 200 and two small dies 200 arranged on either side of the large die 200 are connected to each other via wiring layers 300 each having a rectangular shape in plan view (a line-of-sight shape in plan view).
  • wiring layers 300 each having a rectangular shape in plan view (a line-of-sight shape in plan view).
  • a total of four wiring layers 300 are provided.
  • Example 2 9B is a diagram illustrating a planar configuration of an electronic device 10-2 according to a second embodiment of the present technology.
  • a plurality of (e.g., three) dies 200 each having a rectangular shape in a plan view and arranged in an L-shape in a plan view are connected via a wiring layer 300 having an L-shape in a plan view.
  • Example 3 10A is a diagram illustrating a schematic planar configuration of an electronic device 10-3 according to a third embodiment of the present technology.
  • a plurality of (e.g., three) dies 200 each having a rectangular shape in a plan view and arranged to form a T-shaped gap in a plan view are connected via a wiring layer 300 having a T-shaped shape in a plan view.
  • Example 4 10B is a diagram illustrating a schematic planar configuration of an electronic device 10-4 according to a fourth embodiment of the present technology.
  • a plurality of (e.g., four) dies 200 each having a rectangular shape in a plan view, arranged in a T-shape in a plan view (arranged to form a U-shaped gap in a plan view), are connected via a wiring layer 300 having a U-shaped shape in a plan view.
  • Example 5 11A is a diagram illustrating a schematic planar configuration of an electronic device 10-5 according to a fifth embodiment of the present technology.
  • a plurality of (e.g., four) square dies 200 in a planar view are arranged to form cross-shaped gaps in a planar view (arranged in a square lattice in a planar view) and are connected via a wiring layer 300 in a cross-shaped view in a planar view.
  • Example 6 is a diagram illustrating a schematic planar configuration of an electronic device 10-6 according to Example 6 of an embodiment of the present technology.
  • a plurality of (e.g., four) dies 200 that are square in plan view and arranged to form cross-shaped gaps in plan view (arranged in a square lattice in plan view) are connected via a wiring layer 300 that is petal-shaped and protrudes in all four directions in plan view.
  • the substrate device 50 provided in the electronic device 10 according to one embodiment of the present technology described above includes a wiring substrate 100 and a wiring layer 300 that protrudes from one surface of the wiring substrate 100 and electrically connects a plurality of dies 200.
  • the process of mounting the wiring layer 300 to the wiring substrate 100 is not required, and connection bumps between the wiring layer 300 and the wiring substrate 100 are not required, which prevents parasitic capacitance and resistance from increasing.
  • the substrate device 50 is a substrate device that has a wiring layer that electrically connects multiple dies, and can improve productivity while suppressing degradation of electrical characteristics.
  • the electronic device 10 includes a plurality of dies 200 and a substrate device 50. This makes it possible to provide an electronic device that can improve productivity while suppressing degradation of electrical characteristics.
  • the wiring board 100 is bonded to the support substrate 700 (see FIG. 13A). Specifically, the wiring board 100 is attached to the support substrate 700 with a peelable adhesive 600.
  • the adhesive 600 may be any adhesive that can be used in a peeling method that can release the bond between the wiring board 100 and the support substrate 700, such as laser peeling, mechanical peeling, or thermal peeling.
  • a convex wiring layer is formed on the wiring substrate 100. Specifically, first, a photosensitive dielectric material 300am is applied to the entire surface of the wiring substrate 100, and via holes of the convex wiring layer are formed by exposure and development (see FIG. 13B). Next, a seed layer 150 is formed by seed sputtering (see FIG. 14A). The material of the seed layer 150 is, for example, a titanium copper alloy (Ti/Cu). Next, the via 300b2 and horizontal wiring 300b1 of the first layer of the convex wiring layer are formed by a redistribution layer (RDL: Redistribution Layer) plating process. After that, unnecessary parts of the seed layer 150 are removed by etching (see FIG. 14B).
  • RDL Redistribution Layer
  • the process of forming the photosensitive dielectric material 300am, the via 300b2, and the horizontal wiring 300b1 is repeated to form a wiring layer with a multilayer structure (see FIG. 15A).
  • a resist R is applied to the entire surface of the photosensitive dielectric material 300am, and the resist R other than the resist R covering the area where the convex wiring layer is to be formed by exposure and development is removed (see FIG. 15B).
  • the photosensitive dielectric material 300am other than the photosensitive dielectric material 300am of the convex wiring layer is removed by etching (see FIG. 16A).
  • the resist R on the convex wiring layer is removed (see FIG. 16B).
  • each die 200 is bonded to the wiring substrate 100 via the first bonding portion J1, and each die 200 is bonded to the wiring layer 300 via the second bonding portion J2.
  • underfill 400 is filled (see FIG. 17B). Specifically, underfill 400 is filled around the first joints J1 between the wiring substrate 100 and the multiple dies 200, and around the second joints J2 between the wiring layer 300 and the multiple dies 200.
  • the support substrate 700 is removed (see FIG. 18). Specifically, the support substrate 700 is peeled off from the wiring substrate 100.
  • a non-photosensitive dielectric material may be used for the insulating film 300a of the convex wiring layer instead of the photosensitive dielectric material.
  • a glass material may be used for the insulating film 300a of the convex wiring layer. In this case, the mismatch in the linear expansion coefficient between the convex wiring layer and the die 200 is reduced, which has the effect of improving the bump connection reliability.
  • the manufacturing method of the electronic device 10 using the photosensitive dielectric material is called “manufacturing method 1"
  • the manufacturing method of the electronic device 10 using the non-photosensitive dielectric material is called "manufacturing method 2".
  • the manufacturing method of the electronic device 10 (including the electronic devices 10-1 to 10-6 of Examples 1 to 6) described above includes a step of forming the wiring layer 300 in a convex shape on the wiring substrate 100, and a step of connecting each of the multiple dies 200 to the wiring substrate 100 via a first joint J1, and connecting each of the multiple dies 200 to the wiring layer 300 via a second joint J2.
  • the manufacturing method for the electronic device 10 eliminates the need to mount the wiring layer 300 on the wiring board 100, improving productivity.
  • the step of forming the wiring layer 300 in a convex shape on the wiring board 100 includes a sub-step of forming a layer on the wiring board 100 in which the internal wiring 300b is formed within a part of the in-plane direction of the photosensitive dielectric film (photosensitive dielectric material 300am), and a sub-step of removing the other part of the in-plane direction of the photosensitive dielectric film (photosensitive dielectric material 300am) from the layer by etching.
  • the process of forming the wiring layer 300 in a convex shape on the wiring board 100 repeats a cycle (damascene process) including a sub-process of laminating a dielectric film DF (non-photosensitive dielectric material) on the wiring board WB (see the cross-sectional view of FIG. 32A and the plan view of FIG. 32B), a sub-process of etching the dielectric film DF to form a groove T (see the cross-sectional view of FIG. 33A and the plan view of FIG. 33B), a sub-process of forming a metal film MF on the dielectric film DF in which the groove T has been formed (see the cross-sectional view of FIG. 34A and the plan view of FIG.
  • a cycle including a sub-process of laminating a dielectric film DF (non-photosensitive dielectric material) on the wiring board WB (see the cross-sectional view of FIG. 32A and the plan view of FIG. 32B), a sub-process of etching the dielectric
  • FIG. 19 is a diagram that illustrates a schematic cross-sectional configuration of an electronic device 1 that includes an electronic device 10 according to an embodiment of the present technology.
  • the electronic device 1 includes an electronic device 10 and a circuit board 800 on which the electronic device 10 is mounted.
  • the electronic device 10 and the circuit board 800 are electrically connected via the third joint J3.
  • the third joint J3 is, for example, a solder bump. Note that the third joint J3 may or may not be a component of the electronic device 10.
  • Steps S11 to S15 in FIG. 20 are similar to steps S1 to S5 in FIG. 12.
  • the electronic device 10 is mounted on the circuit board 800. Specifically, first, a solder ball that will become the third joint J3 is mounted on the board-side connection terminal T10 of the electronic device 10 (see FIG. 21A). Next, the electronic device 10 and the circuit board 800 are electrically connected via the third joint J3 by, for example, mass reflow or thermal compression bonding (TCB) (see FIG. 21B).
  • TCB thermal compression bonding
  • the electronic device 1 including the electronic device 10 according to the embodiment of the present technology described above includes the electronic device 10 and a circuit board 800 on which the electronic device 10 is mounted. This makes it possible to provide an electronic device capable of improving productivity while suppressing deterioration of electrical characteristics.
  • the method for manufacturing electronic device 1 includes a step of forming wiring layer 300 in a convex shape on wiring substrate 100, a step of connecting each of the multiple dies 200 to wiring substrate 100 via first joint J1 and connecting each of the multiple dies 200 to wiring layer 300 via second joint J2 to generate electronic device 10, and a step of mounting electronic device 10 on circuit substrate 800.
  • the manufacturing method for electronic device 1 eliminates the need to mount wiring layer 300 on wiring board 100, improving productivity.
  • Fig. 22 is a diagram illustrating in detail a cross-sectional configuration of a portion of an electronic device 10-7 according to Example 7 of an embodiment of the present technology.
  • the substrate 100a of the wiring substrate 100 includes an organic substrate. According to the electronic device 10-7, since the substrate 100a includes an organic substrate, it is possible to reduce costs.
  • Example 8 23 is a diagram showing in detail a cross-sectional configuration of a part of an electronic device 10-8 according to Example 8 of an embodiment of the present technology.
  • the substrate 100a of the wiring substrate 100 includes a FOWLP (Fan Out Wafer Level Package) or a FOPLP (Fan Out Panel Level Package).
  • FOWLP Fean Out Wafer Level Package
  • FOPLP Fean Out Panel Level Package
  • the electronic device 10-8 includes a die 200 arranged across the wiring substrate 100 and the wiring layer 300, as well as a die 200 (also called an "internal die") arranged inside the wiring substrate 100.
  • the internal die is connected to the internal wiring 100b.
  • the die 200 can be built into the wiring substrate 100, so that the wiring length between the dies 200 can be shortened, improving electrical characteristics and enabling miniaturization.
  • Fig. 24 is a diagram showing in detail a cross-sectional configuration of a portion of an electronic device 10-9 according to Example 9 of an embodiment of the present technology.
  • the substrate 100a of the wiring substrate 100 includes a ceramic substrate.
  • the manufacturing steps after the step of forming a convex wiring layer on the wiring substrate 100 are the same as the manufacturing method shown in Fig. 12.
  • the electronic device 10-9 since the substrate 100a includes a ceramic substrate, the electronic device 10-9 has high thermal conductivity, low thermal expansion coefficient, low dielectric constant, and excellent chemical resistance.
  • FIG. 25 is a diagram showing in detail a cross-sectional configuration of a part of an electronic device 10-10 according to Example 10 of an embodiment of the present technology.
  • the substrate 100a of the wiring substrate 100 includes a glass substrate (e.g., borosilicate glass).
  • the manufacturing process after the process of forming a convex wiring layer on the wiring substrate 100 is the same as the manufacturing method shown in FIG. 12.
  • the substrate 100a of the wiring substrate 100 includes a glass substrate (e.g., borosilicate glass)
  • the electronic device 10-10 has excellent heat resistance and impact resistance.
  • the glass substrate e.g., borosilicate glass
  • the glass substrate 100a has a thermal expansion coefficient close to that of silicon (silicon: 2.4 ppm/K, borosilicate glass: 3.2 to 3.8 ppm/K)
  • the connection reliability of the first and third joints J1 and J3 is improved.
  • Example 11 26 is a diagram illustrating in detail a cross-sectional configuration of a portion of an electronic device 10-11 according to an example 11 of an embodiment of the present technology.
  • each of the first and second bonding portions is a metal bonding portion.
  • each of the first and second bonding portions is, for example, a Cu-Cu bonding portion.
  • a SiO 2 film 450 is formed by plasma CVD on the surface (lower surface) of the die side connection terminals T21 and T23 made of Cu, and then planarized by CMP (Chemical Mechanical Polishing).
  • CMP Chemical Mechanical Polishing
  • a thermosetting resin 460 is applied to a substrate device 50 having a convex wiring layer provided on a wiring substrate 100 so that the surface (upper surface) is free of unevenness, and the substrate device 50 is planarized by CMP in the B stage (semi-cured state).
  • annealing (200°C to 300°C) is performed to metal-bond (solid-phase diffusion) the die side connection terminals T21 and the substrate side connection terminals T12, and metal-bond (solid-phase diffusion) the die side connection terminals T23 and the wiring layer side connection terminals T32.
  • This annealing brings the thermosetting resin 460 formed on the substrate device 50, which is bonded to the SiO 2 film 450 formed on the die 200, to a C stage (fully cured state).
  • the die 200 and the substrate device 50 are bonded by metal bonding, no connection bumps are required, and the wiring inductance and wiring resistance are reduced, resulting in improved electrical characteristics.
  • thermosetting resin 460 formed on the substrate device 50 may be C-staged before bonding with the die 200.
  • the resin material on the surface of the substrate device 50 that is connected to the die 200 is not limited to a thermosetting resin, and may be, for example, a thermoplastic resin, a photosensitive dielectric material, or a non-photosensitive dielectric material.
  • FIG. 27 is a detailed diagram illustrating a cross-sectional configuration of a portion of an electronic device 10-12 according to a twelfth example of an embodiment of the present technology.
  • the electronic device 10-12 further includes a heat spreader 1100 arranged across the surfaces of the multiple dies 200 opposite the wiring substrate 100. This allows for efficient heat diffusion from each die 200.
  • the contact thermal resistance of the interface can be reduced by sandwiching a thermal interface material 1400 (TIM: Thermal Interface Material) between the die 200 and the heat spreader 1100.
  • TIM Thermal Interface Material
  • examples of the TIM include alumina (Al 2 O 3 ), aluminum nitride (AlN), and liquid metal (gallium, gallium alloy).
  • the heat spreader 1100 is supported on the wiring board 100 via a support member 1200.
  • the lower end of the support member 1200 is fixed to the wiring board 100 with adhesive 1300.
  • the electronic device 10 according to the embodiment described above and the electronic devices 10-1 to 10-12 according to Examples 1 to 12 may be partially combined to the extent that they are not mutually inconsistent. Furthermore, the shape, size, number, etc. of each of the dies 200 and the convex wiring layers in the electronic device 10 may be changed as appropriate. For example, the number of dies 200 in the electronic device 10 may be two or more, and the number of convex wiring layers may be one or more.
  • Fig. 28 is a block diagram showing functions of an HPC (High Performance Computing) which is an example of an electronic device including an electronic device 10 according to an embodiment (for example, electronic devices 10-1 to 10-12 according to Examples 1 to 12).
  • Fig. 29 is a diagram showing a configuration example of a node (computing server) in Fig. 28.
  • the electronic device 10 used in HPC comprises hardware such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and an FPGA (Field Programmable Gate Array).
  • a CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • FPGA Field Programmable Gate Array
  • the functions of the HPC are broadly divided into computing servers (see FIG. 29), networks, and data storage.
  • the electronic device 10 can be used to realize at least one of the computing servers, networks, and data storage.
  • FIG. 28 To build an HPC architecture, multiple computing servers (e.g., several to several thousand) that make up a cluster are networked as shown in Figure 28. There are multiple clusters. Each computing server in the cluster is called a node. Each node in the cluster works in parallel with each other, improving processing speed and achieving HPC. Software programs and algorithms run simultaneously on the servers in the cluster. The cluster is networked to data storage to obtain the output. These components work seamlessly to perform various tasks.
  • each component needs to maintain the same speed as the other components.
  • data storage needs to be able to feed and pull data to and from computing servers as soon as it is processed.
  • the network needs to be able to support high-speed data transfer between computing servers and data storage.
  • electronic device 10 including electronic devices 10-1 to 10-12 of Examples 1 to 12 for components of the HPC makes it possible to achieve these capabilities.
  • the technology according to the present disclosure (the present technology) can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.
  • FIG. 30 is a diagram showing an automobile, which is an example of a moving body equipped with an electronic device including an electronic device 10 according to an embodiment of the present technology (including electronic devices 10-1 to 10-12 of Examples 1 to 12).
  • the electronic device 10 is used, for example, as a component of a sensing unit of the automobile.
  • the sensing unit is used, for example, for autonomous driving control.
  • Examples of electronic device use 37 is a diagram showing an example of use of the substrate device, electronic device, or electronic equipment according to the present technology constituting at least a part of a solid-state imaging device (image sensor).
  • the case of constituting at least a part of an image sensor is, for example, a case in which a plurality of dies 200 includes an imaging chip on which a solid-state imaging element is mounted, a logic chip, a memory chip, an AI chip, an interface chip, and the like.
  • the electronic device 10 according to one embodiment of the present technology (e.g., electronic devices 1 to 12 according to Examples 1 to 12), the substrate device 50 of the electronic device 10, and an electronic device including the electronic device 10 can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as described below. That is, as shown in FIG. 37, for example, it can be used in devices used in the fields of appreciation for capturing images for appreciation, transportation, home appliances, medicine/healthcare, security, beauty, sports, agriculture, etc.
  • any of the board devices, electronic devices, and electronic equipment related to this technology can be used in devices for taking images for appreciation, such as digital cameras, smartphones, and mobile phones with camera functions.
  • the substrate device, electronic device, or electronic equipment related to this technology can be used in devices used for transportation purposes, such as on-board sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles.
  • on-board sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition
  • surveillance cameras that monitor moving vehicles and roads
  • distance measuring sensors that measure distances between vehicles.
  • the substrate device, electronic device, or electronic equipment related to this technology can be used in devices provided to home appliances such as television sets, refrigerators, and air conditioners to capture images of user gestures and operate the appliances in accordance with those gestures.
  • the substrate device, electronic device, or electronic equipment related to this technology can be used in devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography by receiving infrared light.
  • the substrate device, electronic device, or electronic equipment related to this technology can be used in devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication.
  • the substrate device, electronic device, or electronic equipment related to this technology can be used in devices used for beauty purposes, such as skin measuring devices that take pictures of the skin and microscopes that take pictures of the scalp.
  • the substrate device, electronic device, or electronic equipment related to this technology can be used in devices used for sports, such as action cameras and wearable cameras for sports applications.
  • the circuit board device, electronic device, or electronic equipment related to this technology can be used in equipment used for agricultural purposes, such as cameras for monitoring the condition of fields and crops.
  • the substrate device, electronic device, and electronic device according to the present technology can be applied to any type of electronic device with an imaging function, such as a camera system such as a digital still camera or video camera, or a mobile phone with an imaging function, as at least a part of a solid-state imaging device 501.
  • FIG. 38 shows the schematic configuration of an electronic device 510 (camera) as an example.
  • the electronic device 510 is, for example, a video camera capable of taking still or moving images, and has a solid-state imaging device 501, an optical system (optical lens) 502, a shutter device 503, a drive unit 504 that drives the solid-state imaging device 501 and the shutter device 503, and a signal processing unit 505.
  • a solid-state imaging device 501 an optical system (optical lens) 502
  • a shutter device 503 a drive unit 504 that drives the solid-state imaging device 501 and the shutter device 503, and a signal processing unit 505.
  • the optical system 502 guides image light (incident light) from the subject to the pixel area of the solid-state imaging device 501.
  • This optical system 502 may be composed of multiple optical lenses.
  • the shutter device 503 controls the light irradiation period and light blocking period to the solid-state imaging device 501.
  • the drive unit 504 controls the transfer operation of the solid-state imaging device 501 and the shutter operation of the shutter device 503.
  • the signal processing unit 505 performs various signal processing on the signal output from the solid-state imaging device 501.
  • the video signal Dout after signal processing is stored in a storage medium such as a memory, or is output to a monitor, etc.
  • the substrate device, electronic device, and electronic device according to the present technology can also be applied to at least a part of other electronic devices that detect light, such as a TOF (Time Of Flight) sensor.
  • a TOF sensor When applied to a TOF sensor, it can be applied to, for example, a distance image sensor using a direct TOF measurement method or a distance image sensor using an indirect TOF measurement method.
  • a distance image sensor using a direct TOF measurement method the arrival timing of photons is directly obtained in the time domain at each pixel, so a light pulse with a short pulse width is transmitted and an electrical pulse is generated by a receiver that responds quickly.
  • the present disclosure can be applied to the receiver in this case.
  • the indirect TOF method the flight time of light is measured using a semiconductor element structure in which the detection and accumulation amount of carriers generated by light changes depending on the arrival timing of light.
  • FIG. 39 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 functions as a control device for a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
  • the body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps.
  • radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020.
  • the body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
  • the outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030.
  • the outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle, and receives the captured images.
  • the outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface, based on the received images.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received.
  • the imaging unit 12031 can output the electrical signal as an image, or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects information inside the vehicle.
  • a driver state detection unit 12041 that detects the state of the driver is connected.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
  • the microcomputer 12051 can calculate the control target values of the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output a control command to the drive system control unit 12010.
  • the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating vehicle collisions, following the vehicle based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 can also perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.
  • the microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.
  • the audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • Figure 40 shows an example of the installation position of the imaging unit 12031.
  • the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100.
  • the imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100.
  • the imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100.
  • the images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
  • FIG. 40 shows an example of the imaging ranges of the imaging units 12101 to 12104.
  • Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door.
  • an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 can obtain the distance to each solid object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on the driver's operation.
  • automatic braking control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles.
  • the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, it can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by forcibly decelerating or steering the vehicle to avoid a collision via the drive system control unit 12010.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured image of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian.
  • the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian.
  • the audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to, for example, the imaging unit 12031, among the configurations described above.
  • the solid-state imaging device 111 according to the present disclosure can be applied to the imaging unit 12031.
  • the present technology can also be configured as follows.
  • a substrate device comprising: (2) The substrate device according to (1), wherein the one surface is a flat surface. (3) the wiring substrate and each of the plurality of dies are connected via a first bonding portion; The substrate device according to (1) or (2), wherein the wiring layer and each of the plurality of dies are connected via a second bonding portion. (4) The substrate device according to (3), wherein the second joint portion is smaller than the first joint portion. (5) The substrate device according to (3) or (4), wherein each of the first and second bonding portions is a bump.
  • the wiring layer is An insulating film; A wiring disposed inside the insulating film; having The substrate device according to any one of (1) to (10), wherein the insulating film is made of a dielectric material.
  • the wiring board is A substrate; Wiring disposed inside the substrate; having The substrate device according to any one of (1) to (11), wherein the substrate includes any one of an organic substrate, a FOWLP or FOPLP, a ceramic substrate, and a glass substrate.

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PCT/JP2024/005645 2023-03-30 2024-02-19 基板装置、電子装置、電子機器、電子装置の製造方法及び電子機器の製造方法 Ceased WO2024202681A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202480021399.3A CN120958975A (zh) 2023-03-30 2024-02-19 基板装置、电子设备、电子装置、电子设备的制造方法和电子装置的制造方法
JP2025509915A JPWO2024202681A1 (https=) 2023-03-30 2024-02-19
KR1020257032164A KR20250165602A (ko) 2023-03-30 2024-02-19 기판 장치, 전자 장치, 전자 기기, 전자 장치의 제조 방법 및 전자 기기의 제조 방법
EP24778826.8A EP4693401A1 (en) 2023-03-30 2024-02-19 Substrate device, electronic device, electronic apparatus, method for manufacturing electronic device, and method for manufacturing electronic apparatus

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JP2021153172A (ja) 2020-03-24 2021-09-30 インテル・コーポレーション オープンキャビティブリッジの共平面配置アーキテクチャおよびプロセス
JP2022550707A (ja) * 2019-09-27 2022-12-05 インターナショナル・ビジネス・マシーンズ・コーポレーション 基板への側面接続を含む相互接続

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JP2014140022A (ja) * 2012-12-20 2014-07-31 Intel Corp 高密度有機ブリッジデバイスおよび方法
JP2018129528A (ja) 2012-12-20 2018-08-16 インテル・コーポレーション 高密度有機ブリッジデバイスおよび方法
US20200219816A1 (en) * 2017-12-29 2020-07-09 Intel Corporation Microelectronic assemblies
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JP2022550707A (ja) * 2019-09-27 2022-12-05 インターナショナル・ビジネス・マシーンズ・コーポレーション 基板への側面接続を含む相互接続
JP2021153172A (ja) 2020-03-24 2021-09-30 インテル・コーポレーション オープンキャビティブリッジの共平面配置アーキテクチャおよびプロセス

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