KR20250165602A - 기판 장치, 전자 장치, 전자 기기, 전자 장치의 제조 방법 및 전자 기기의 제조 방법 - Google Patents

기판 장치, 전자 장치, 전자 기기, 전자 장치의 제조 방법 및 전자 기기의 제조 방법

Info

Publication number
KR20250165602A
KR20250165602A KR1020257032164A KR20257032164A KR20250165602A KR 20250165602 A KR20250165602 A KR 20250165602A KR 1020257032164 A KR1020257032164 A KR 1020257032164A KR 20257032164 A KR20257032164 A KR 20257032164A KR 20250165602 A KR20250165602 A KR 20250165602A
Authority
KR
South Korea
Prior art keywords
substrate
wiring
electronic device
dies
joint
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020257032164A
Other languages
English (en)
Korean (ko)
Inventor
히로히사 야스카와
Original Assignee
소니 세미컨덕터 솔루션즈 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 소니 세미컨덕터 솔루션즈 가부시키가이샤 filed Critical 소니 세미컨덕터 솔루션즈 가부시키가이샤
Publication of KR20250165602A publication Critical patent/KR20250165602A/ko
Pending legal-status Critical Current

Links

Classifications

    • H01L23/13—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H01L23/3675—
    • H01L23/49838—
    • H01L23/5226—
    • H01L23/5283—
    • H01L23/5381—
    • H01L23/5384—
    • H01L23/5386—
    • H01L23/5389—
    • H01L24/17—
    • H01L25/0655—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/231—Arrangements for cooling characterised by their places of attachment or cooling paths
    • H10W40/242—Arrangements for cooling characterised by their places of attachment or cooling paths comprising thermal conductors between chips and the and the arrangements for cooling, e.g. compliant heat-spreaders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/7295—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors on the rear surface of insulating package substrates, interposers or RDLs, for connection outside of the package, e.g. ball grid array [BGA] bumps

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Combinations Of Printed Boards (AREA)
KR1020257032164A 2023-03-30 2024-02-19 기판 장치, 전자 장치, 전자 기기, 전자 장치의 제조 방법 및 전자 기기의 제조 방법 Pending KR20250165602A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2023055472 2023-03-30
JPJP-P-2023-055472 2023-03-30
PCT/JP2024/005645 WO2024202681A1 (ja) 2023-03-30 2024-02-19 基板装置、電子装置、電子機器、電子装置の製造方法及び電子機器の製造方法

Publications (1)

Publication Number Publication Date
KR20250165602A true KR20250165602A (ko) 2025-11-26

Family

ID=92904239

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020257032164A Pending KR20250165602A (ko) 2023-03-30 2024-02-19 기판 장치, 전자 장치, 전자 기기, 전자 장치의 제조 방법 및 전자 기기의 제조 방법

Country Status (6)

Country Link
EP (1) EP4693401A1 (https=)
JP (1) JPWO2024202681A1 (https=)
KR (1) KR20250165602A (https=)
CN (1) CN120958975A (https=)
TW (1) TW202439541A (https=)
WO (1) WO2024202681A1 (https=)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018129528A (ja) 2012-12-20 2018-08-16 インテル・コーポレーション 高密度有機ブリッジデバイスおよび方法
JP2021153172A (ja) 2020-03-24 2021-09-30 インテル・コーポレーション オープンキャビティブリッジの共平面配置アーキテクチャおよびプロセス

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11342320B2 (en) * 2017-12-29 2022-05-24 Intel Corporation Microelectronic assemblies
EP3732716A4 (en) * 2017-12-29 2021-12-01 Intel Corporation MICROELECTRONIC ARRANGEMENTS
US11264314B2 (en) * 2019-09-27 2022-03-01 International Business Machines Corporation Interconnection with side connection to substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018129528A (ja) 2012-12-20 2018-08-16 インテル・コーポレーション 高密度有機ブリッジデバイスおよび方法
JP2021153172A (ja) 2020-03-24 2021-09-30 インテル・コーポレーション オープンキャビティブリッジの共平面配置アーキテクチャおよびプロセス

Also Published As

Publication number Publication date
EP4693401A1 (en) 2026-02-11
JPWO2024202681A1 (https=) 2024-10-03
TW202439541A (zh) 2024-10-01
WO2024202681A1 (ja) 2024-10-03
CN120958975A (zh) 2025-11-14

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St.27 status event code: A-0-1-A10-A15-nap-PA0105

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Q12 Application published

Free format text: ST27 STATUS EVENT CODE: A-1-1-Q10-Q12-NAP-PG1501 (AS PROVIDED BY THE NATIONAL OFFICE)

P22-X000 Classification modified

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P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000