TW202439541A - 基板裝置、電子裝置、電子機器、電子裝置之製造方法及電子機器之製造方法 - Google Patents
基板裝置、電子裝置、電子機器、電子裝置之製造方法及電子機器之製造方法 Download PDFInfo
- Publication number
- TW202439541A TW202439541A TW113109935A TW113109935A TW202439541A TW 202439541 A TW202439541 A TW 202439541A TW 113109935 A TW113109935 A TW 113109935A TW 113109935 A TW113109935 A TW 113109935A TW 202439541 A TW202439541 A TW 202439541A
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- wiring
- aforementioned
- electronic device
- wiring layer
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/42—Vias, e.g. via plugs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/435—Cross-sectional shapes or dispositions of interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
- H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
- H10W40/231—Arrangements for cooling characterised by their places of attachment or cooling paths
- H10W40/242—Arrangements for cooling characterised by their places of attachment or cooling paths comprising thermal conductors between chips and the and the arrangements for cooling, e.g. compliant heat-spreaders
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
- H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/7295—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors on the rear surface of insulating package substrates, interposers or RDLs, for connection outside of the package, e.g. ball grid array [BGA] bumps
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Combinations Of Printed Boards (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023055472 | 2023-03-30 | ||
| JP2023-055472 | 2023-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW202439541A true TW202439541A (zh) | 2024-10-01 |
Family
ID=92904239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW113109935A TW202439541A (zh) | 2023-03-30 | 2024-03-18 | 基板裝置、電子裝置、電子機器、電子裝置之製造方法及電子機器之製造方法 |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP4693401A1 (https=) |
| JP (1) | JPWO2024202681A1 (https=) |
| KR (1) | KR20250165602A (https=) |
| CN (1) | CN120958975A (https=) |
| TW (1) | TW202439541A (https=) |
| WO (1) | WO2024202681A1 (https=) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9236366B2 (en) | 2012-12-20 | 2016-01-12 | Intel Corporation | High density organic bridge device and method |
| US11342320B2 (en) * | 2017-12-29 | 2022-05-24 | Intel Corporation | Microelectronic assemblies |
| EP3732716A4 (en) * | 2017-12-29 | 2021-12-01 | Intel Corporation | MICROELECTRONIC ARRANGEMENTS |
| US11264314B2 (en) * | 2019-09-27 | 2022-03-01 | International Business Machines Corporation | Interconnection with side connection to substrate |
| US12176268B2 (en) | 2020-03-24 | 2024-12-24 | Intel Corporation | Open cavity bridge co-planar placement architectures and processes |
-
2024
- 2024-02-19 JP JP2025509915A patent/JPWO2024202681A1/ja active Pending
- 2024-02-19 KR KR1020257032164A patent/KR20250165602A/ko active Pending
- 2024-02-19 WO PCT/JP2024/005645 patent/WO2024202681A1/ja not_active Ceased
- 2024-02-19 EP EP24778826.8A patent/EP4693401A1/en active Pending
- 2024-02-19 CN CN202480021399.3A patent/CN120958975A/zh active Pending
- 2024-03-18 TW TW113109935A patent/TW202439541A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| EP4693401A1 (en) | 2026-02-11 |
| JPWO2024202681A1 (https=) | 2024-10-03 |
| KR20250165602A (ko) | 2025-11-26 |
| WO2024202681A1 (ja) | 2024-10-03 |
| CN120958975A (zh) | 2025-11-14 |
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