WO2024195725A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024195725A1
WO2024195725A1 PCT/JP2024/010258 JP2024010258W WO2024195725A1 WO 2024195725 A1 WO2024195725 A1 WO 2024195725A1 JP 2024010258 W JP2024010258 W JP 2024010258W WO 2024195725 A1 WO2024195725 A1 WO 2024195725A1
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WO
WIPO (PCT)
Prior art keywords
substrate
semiconductor
layer
semiconductor layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2024/010258
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English (en)
French (fr)
Japanese (ja)
Inventor
孝司 横山
陽介 新田
完 清水
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Sony Semiconductor Solutions Corp
Original Assignee
Sony Semiconductor Solutions Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to EP24774861.9A priority Critical patent/EP4682958A1/en
Priority to KR1020257033697A priority patent/KR20250163920A/ko
Priority to JP2025508395A priority patent/JPWO2024195725A1/ja
Priority to CN202480011036.1A priority patent/CN120660462A/zh
Publication of WO2024195725A1 publication Critical patent/WO2024195725A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/809—Constructional details of image sensors of hybrid image sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/807—Pixel isolation structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections

Definitions

  • This disclosure relates to a semiconductor device having a three-dimensional structure.
  • Patent Document 1 discloses a back-illuminated solid-state imaging device in which individualized memory circuits and logic circuits are laid out horizontally below the solid-state imaging element and embedded with an oxide film.
  • imaging devices are expected to achieve both high functionality and low costs.
  • a semiconductor device includes a first substrate having opposing first and second surfaces and having a plurality of semiconductor elements formed on the first surface side, a second substrate mounted on the second surface of the first substrate and configured by stacking a plurality of semiconductor layers each having one or more circuits, and a third substrate arranged in parallel with the second substrate and mounted on the second surface of the first substrate and configured by stacking one or more semiconductor layers each having one or more circuits.
  • a first substrate has a plurality of semiconductor elements formed on its first surface, and a second substrate and a third substrate are mounted on the second surface opposite the first surface.
  • the second substrate has a plurality of stacked semiconductor layers, each having one or more circuits.
  • the third substrate has one or more stacked semiconductor layers, each having one or more circuits. This allows the desired circuit chip to be mounted in the desired position.
  • FIG. 1 is a schematic cross-sectional view illustrating an example of a configuration of an imaging device according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic cross-sectional view illustrating another example of the configuration of the imaging device according to the embodiment of the present disclosure.
  • FIG. 3 is a flow chart for explaining the manufacturing process of the imaging device shown in FIGS.
  • FIG. 4 is an exploded perspective view showing an example of a schematic configuration of the imaging device shown in FIGS.
  • FIG. 5 is an exploded perspective view showing a connection state of the pixel array portion of the image pickup device shown in FIG.
  • FIG. 6 is a diagram for explaining the connections of the sensor pixels, the readout circuit, and the circuits provided in the multiple semiconductor layers constituting the first CoW layer shown in FIG.
  • FIG. 1 is a schematic cross-sectional view illustrating an example of a configuration of an imaging device according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic cross-sectional view illustrating another example of the configuration of the imaging device
  • FIG. 7 is an exploded perspective view showing a state of connection of the peripheral parts of the imaging device shown in FIG.
  • FIG. 8 is an exploded perspective view illustrating a connection state of a pixel array section of an imaging device according to the first modification of the present disclosure.
  • FIG. 9 is an exploded perspective view showing a mode of connection of the peripheral parts of an imaging device in the first modification of the present disclosure.
  • FIG. 10 is a schematic cross-sectional view illustrating an example of a configuration of an imaging device according to Modification 2 of the present disclosure.
  • FIG. 11 is a schematic cross-sectional view illustrating another example of the configuration of an imaging device according to the second modification of the present disclosure.
  • FIG. 12 is a schematic cross-sectional view illustrating another example of the configuration of an imaging device according to Modification 2 of the present disclosure.
  • FIG. 13 is a schematic cross-sectional view illustrating an example of a configuration of an imaging device according to Modification 3 of the present disclosure.
  • FIG. 14 is a block diagram of circuits mounted on the first CoW layer and the second CoW layer of the imaging device shown in FIG.
  • FIG. 15 is a diagram showing an example of a schematic configuration of an imaging system including the imaging devices according to the above-described embodiment and modifications 1 to 4.
  • FIG. 16 is a diagram showing an example of an imaging procedure in the imaging system of FIG.
  • FIG. 17 is a block diagram showing an example of a schematic configuration of a vehicle control system.
  • FIG. 16 is a diagram showing an example of an imaging procedure in the imaging system of FIG.
  • FIG. 17 is a block diagram showing an example of a schematic configuration of a vehicle control system.
  • FIG. 18 is an explanatory diagram showing an example of the installation positions of the outside-of-vehicle information detection unit and the imaging unit.
  • FIG. 19 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.
  • FIG. 20 is a block diagram showing an example of the functional configuration of the camera head and the CCU.
  • FIG. 21 is a schematic cross-sectional view illustrating an example of a configuration of an imaging device according to Modification 4 of the present disclosure.
  • FIG. 22A is a schematic cross-sectional view illustrating an example of a manufacturing process for the imaging device shown in FIG. 21.
  • FIG. 22B is a schematic cross-sectional view showing a step subsequent to FIG. 22A.
  • FIG. 22C is a schematic cross-sectional view showing a step subsequent to FIG. 22B.
  • FIG. 22D is a schematic cross-sectional view showing a step following FIG. 22C.
  • FIG. 22E is a schematic cross-sectional view showing a step subsequent to FIG. 22D.
  • FIG. 22F is a schematic cross-sectional view showing a step subsequent to FIG. 22E.
  • FIG. 22G is a schematic cross-sectional view showing a step subsequent to FIG. 22F.
  • FIG. 22H is a schematic cross-sectional view showing a step subsequent to FIG. 22G.
  • FIG. 23 is a schematic cross-sectional view illustrating an example of a configuration of an imaging device according to Modification 5 of the present disclosure.
  • FIG. 24 is a schematic cross-sectional view illustrating an example of a configuration of an imaging device according to Modification 6 of the present disclosure.
  • FIG. 23 is a schematic cross-sectional view illustrating an example of a configuration of an imaging device according to Modification 5 of the present disclosure.
  • FIG. 24 is a schematic cross-sectional view illustrating an example of
  • FIG. 25 is a schematic cross-sectional view illustrating another example of the configuration of an imaging device according to the sixth modification of the present disclosure.
  • FIG. 26 is a schematic cross-sectional view illustrating another example of the configuration of an imaging device according to the sixth modification of the present disclosure.
  • FIG. 27 is a schematic cross-sectional view illustrating an example of a configuration of an imaging device according to Modification 7 of the present disclosure.
  • FIG. 28 is a schematic cross-sectional view illustrating another example of the configuration of an imaging device according to the seventh modification of the present disclosure.
  • FIG. 29 is a schematic cross-sectional view illustrating another example of the configuration of an imaging device according to the seventh modification of the present disclosure.
  • FIG. 30 is a schematic cross-sectional view illustrating another example of the configuration of an imaging device according to the seventh modification of the present disclosure.
  • Embodiment an example of an imaging device having a plurality of CoW layers, each of which is made up of one or more layers, mounted in a planar direction on the front surface side of a sensor substrate
  • Modifications 2-1.
  • Modification 1 another example of connection of pixel array portion of imaging device
  • Modification 2 another example of the configuration of the imaging device 2-3.
  • Modification 3 (another example of the configuration of the imaging device) 2-4.
  • Modification 4 (another example of the configuration of the imaging device) 2-5.
  • Modification 5 (another example of the configuration of the imaging device) 2-6.
  • Modification 6 (another example of the configuration of the imaging device) 2-7.
  • Modification 7 (another example of the configuration of the imaging device) 3.
  • Application examples 4. Application examples 4.
  • Preferred embodiment 1 is a schematic diagram showing an example of a cross-sectional configuration of an imaging device according to an embodiment of the present disclosure (imaging device 1).
  • the imaging device 1 has a three-dimensional structure in which layers (hereinafter referred to as CoW layers) having a chip-on-wafer (CoW) structure in which one or more semiconductor layers are stacked are arranged in parallel in the in-plane directions (XY directions) of the sensor substrate 100 below the sensor substrate 100.
  • the imaging device 1 is a so-called back-illuminated imaging device that receives light from the back side of the sensor substrate 100 (for example, the back side (surface 100S1) of the semiconductor layer 100S constituting the sensor substrate 100).
  • the imaging device 1 has a plurality of (here, two) CoW layers (a first CoW layer 200 and a second CoW layer 300) formed by stacking one or a plurality of semiconductor layers, mounted side by side on the front surface (surface 100S2) side of the sensor substrate 100.
  • the sensor substrate 100 and the first CoW layer 200, and the sensor substrate 100 and the second CoW layer 300 are electrically connected to each other by hybrid junctions.
  • the first CoW layer 200 and the second CoW layer 300 are electrically connected to each other via the sensor substrate 100.
  • An insulating layer 410 is embedded between the first CoW layer 200 and the second CoW layer 300.
  • a support substrate 400 common to the first CoW layer 200 and the second CoW layer 300 is provided on the surface opposite to the surface facing the sensor substrate 100 of the first CoW layer 200 and the second CoW layer 300 .
  • the sensor substrate 100 corresponds to a specific example of a "first substrate” in the embodiment of the present disclosure.
  • the first CoW layer 200 corresponds to a specific example of a "second substrate” in the embodiment of the present disclosure.
  • the second CoW layer 300 corresponds to a specific example of a "third substrate” in the embodiment of the present disclosure.
  • the sensor substrate 100 has a semiconductor layer 100S having a pair of opposing surfaces (a front surface (surface 100S2) and a back surface (surface 100S2)) and a wiring layer 100T provided on the surface 100S2 side of the semiconductor layer 100S.
  • the semiconductor layer 100S has a pixel array section 110 in which a plurality of sensor pixels P are arranged in an array, and a peripheral section 120 provided around the pixel array section 110.
  • a photodiode PD that performs photoelectric conversion is embedded in each of the plurality of sensor pixels P as a light receiving element 111.
  • the semiconductor layer 100S is composed of, for example, a silicon (Si) substrate.
  • the semiconductor layer 100S can be composed of a semiconductor substrate made of germanium (Ge), selenium (Se), carbon (C), gallium arsenide (GaAs), gallium phosphide (GaP), nickel antimonide (NiSb), indium antimonide (InSb), indium arsenide (InAs), indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC), or indium gallium arsenide (InGaAs).
  • wiring 122, 123 including wiring connected to the floating diffusion FD, wiring including the gates of the multiple p-MOS transistors 112 and multiple n-MOS transistors 113 constituting the readout circuit, and pad electrodes 123X are formed in the interlayer insulating layer 121.
  • On the surface of the wiring layer 100T (specifically, the surface of the interlayer insulating layer 121), multiple pad parts 124 are exposed, for example, for use in bonding and electrical connection with the first CoW layer 200 and the second CoW layer 300.
  • the multiple pad parts 124 are connected to the floating diffusion FD and the gates of the multiple p-MOS transistors 112 and multiple n-MOS transistors 113 through vias, for example.
  • a color filter 131 and a light receiving lens 132 are provided on the surface 100S1 side of the semiconductor layer 100S.
  • the first CoW layer 200 is mounted, for example, at a position corresponding to the pixel array section 110 of the sensor substrate 100.
  • the first CoW layer 200 has a chip structure in which multiple semiconductor layers (here, a first layer 210, a second layer 220, and a third layer 230) are stacked.
  • One or more circuits with different technology nodes are formed in the first layer 210, the second layer 220, and the third layer 230.
  • different technology nodes means that at least one of the following is different: minimum power supply voltage (Vdd), thickness of the gate insulating film of the transistors constituting each circuit, gate length (lg) and minimum gate pitch (Pg) of the transistors constituting each circuit, wiring width and minimum wiring pitch (Pm) of the wiring provided in each circuit.
  • Vdd minimum power supply voltage
  • lg gate length
  • Pg minimum gate pitch
  • Pm minimum wiring pitch
  • a 22 nm node analog circuit is formed on the first layer 210.
  • a 5 nm node logic circuit is formed on the second layer 220.
  • a memory such as a Dynamic Random Access Memory (DRAM) is mounted on the third layer 230.
  • the first layer 210, the second layer 220, and the third layer 230 are electrically connected to each other by hybrid junctions.
  • DRAM Dynamic Random Access Memory
  • the first layer 210 has a semiconductor layer 210S having a pair of opposing faces 210S2 and 210S3, a wiring layer 210T-1 provided on the face 210S1 side of the semiconductor layer 210S, and a wiring layer 210T-2 provided on the face 210S2 side of the semiconductor layer 210S.
  • a plurality of p-MOS transistors 211 and a plurality of n-MOS transistors 212 constituting an analog circuit are provided on the face 210S1 of the semiconductor layer 210S.
  • the wiring layer 210T-1 includes a plurality of wirings 213, and a plurality of pad portions 214 are exposed on the surface.
  • the wiring layer 210T-2 includes a plurality of wirings 215, and a plurality of pad portions 216 are exposed on the surface.
  • the wiring layer 210T-1 and the wiring layer 210T-2 are electrically connected by, for example, a through wiring 217 that penetrates the semiconductor layer 210S.
  • the second layer 220 has a semiconductor layer 220S having a pair of opposing surfaces 220S1 and 220S2, a wiring layer 220T-1 provided on the surface 220S1 side of the semiconductor layer 220S, and a wiring layer 220T-2 provided on the surface 220S2 side of the semiconductor layer 220S.
  • a plurality of p-MOS transistors 221 and a plurality of n-MOS transistors 222 constituting a logic circuit are provided on the surface 220S1 of the semiconductor layer 220S.
  • the wiring layer 220T-1 includes a plurality of wirings 223, and a plurality of pad portions 224 are exposed on the surface.
  • the wiring layer 220T-2 includes a plurality of wirings 225, and a plurality of pad portions 226 are exposed on the surface.
  • the wiring layer 220T-1 and the wiring layer 220T-2 are electrically connected by, for example, a through wiring 227 that penetrates the semiconductor layer 220S.
  • the third layer 230 has a semiconductor layer 230S having a pair of opposing surfaces 230S1 and 230S2, and a wiring layer 230T provided on the surface 230S1 side of the semiconductor layer 230S.
  • a plurality of p-MOS transistors 231 and a plurality of n-MOS transistors 232 that constitute a circuit including a MEM are provided on the surface 230S1 of the semiconductor layer 230S.
  • the wiring layer 230T includes a plurality of wirings 233, and has a plurality of pad portions 234 exposed on the surface.
  • the semiconductor layers 210S, 220S, and 230S are each composed of, for example, a silicon substrate.
  • the semiconductor layers 210S, 220S, and 230S may be formed using different semiconductor materials.
  • the semiconductor layers 210S, 220S, and 230S may be made of a semiconductor substrate made of germanium (Ge), selenium (Se), carbon (C), or the like.
  • the semiconductor layers 210S, 220S, and 230S may be made of a compound semiconductor substrate made of silicon germanium (SiGe), gallium arsenide (GaAs), gallium phosphide (GaP), nickel antimonide (NiSb), indium antimonide (InSb), indium arsenide (InAs), indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC), or indium gallium arsenide (InGaAs).
  • the semiconductor layers 210S, 220S, and 230S may be formed using one-dimensional materials such as carbon nanotubes, or two-dimensional materials such as transition metal dichalcogenides (TMDs) and graphene.
  • TMDs transition metal dichalcogenides
  • the multiple p-MOS transistors 211, 221, 231 and the multiple n-MOS transistors 212, 222, 232 provided in the first layer 210, the second layer 220, and the third layer 230 may be made using different semiconductor materials.
  • SiGe and Ge may be used for the p-MOS transistors 211, 221, 231, and Si materials may be used for the n-MOS transistors 212, 222, 232.
  • Si materials may be used for the p-MOS transistors 211, 221, 231, and GaN, GaAs, nGaAs, etc. may be used for the n-MOS transistors 212, 222, 232.
  • the first layer 210 and the second layer 220 are electrically connected to each other by bonding a plurality of pads 216, 224 exposed on the respective surfaces of the opposing wiring layer 210T-2 and wiring layer 220T-1.
  • the second layer 220 and the third layer 230 are electrically connected to each other by bonding a plurality of pads 226, 34 exposed on the respective surfaces of the opposing wiring layer 220T-2 and wiring layer 230T-1.
  • the sensor substrate 100 and the first CoW layer 200 are electrically connected to each other by bonding a plurality of pads 124, 214 exposed on the respective surfaces of the opposing wiring layer 100T and wiring layer 210T-1.
  • Each of the plurality of pads 124, 214, 216, 224, 226, 234 is formed using, for example, copper (Cu).
  • Cu copper
  • the sensor substrate 100, the first CoW layer 200, and the first layer 210, the second layer 220, and the third layer 230 that constitute the first CoW layer 200 are electrically connected to each other by so-called CuCu junctions.
  • the second CoW layer 300 is mounted, for example, at a position corresponding to the peripheral portion 120 of the sensor substrate 100.
  • the second CoW layer 300 is a single-layer chip consisting of a semiconductor layer 300S having a pair of opposing faces 300S1 and 300S2, and a wiring layer 300T provided on the face 300S1 side of the semiconductor layer 300S.
  • a 3 nm node logic circuit is formed in the semiconductor layer 300S.
  • a plurality of p-MOS transistors 311 and a plurality of n-MOS transistors 312 that constitute the logic circuit are provided on the face 300S1 of the semiconductor layer 300S.
  • the wiring layer 300T includes a plurality of wires 313, and has a plurality of pad portions 314 exposed on the surface.
  • the semiconductor layer 300S is, for example, composed of a silicon substrate.
  • the semiconductor layer 300S may be a semiconductor substrate made of germanium (Ge), selenium (Se), carbon (C), or the like.
  • the semiconductor layer 300S may be a compound semiconductor substrate made of silicon germanium (SiGe), gallium arsenide (GaAs), gallium phosphide (GaP), nickel antimonide (NiSb), indium antimonide (InSb), indium arsenide (InAs), indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC), or indium gallium arsenide (InGaAs).
  • the semiconductor layer 300S may be formed using a one-dimensional material such as carbon nanotubes, or a two-dimensional material such as transition metal dichalcogenide (TMD) or graphene.
  • TMD transition metal dichalcogenide
  • the multiple p-MOS transistors 311 and multiple n-MOS transistors 312 provided in the semiconductor layer 300S may be made using different semiconductor materials.
  • the p-MOS transistors 311 may be made using SiGe or Ge, and the n-MOS transistors 312 may be made using Si materials.
  • the p-MOS transistors 311 may be made using Si materials, and the n-MOS transistors 312 may be made using GaN, GaAs, nGaAs, etc.
  • the sensor substrate 100 and the second CoW layer 300 are electrically connected to each other by bonding a plurality of pad portions 124, 314 exposed on the respective surfaces of the opposing wiring layers 100T and 300T.
  • the plurality of pad portions 314 are formed, for example, using copper (Cu) like the plurality of pad portions 124.
  • CuCu bonding the sensor substrate 100 and the second CoW layer 300 are electrically connected to each other by so-called CuCu bonding.
  • FIG. 2 is a schematic diagram showing another example (imaging device 2) of the cross-sectional configuration of an imaging device according to an embodiment of the present disclosure.
  • the sensor substrate 100 may be configured by stacking a semiconductor layer 100S-1 in which a photodiode PD is embedded in each of a plurality of sensor pixels P, and a semiconductor layer 100S-2 having a readout circuit that outputs a pixel signal based on the charge output from the sensor pixel P.
  • a plurality of p-MOS transistors 112 such as transfer transistors, and a plurality of n-MOS transistors 113 are provided for each sensor pixel P or for a plurality of sensor pixels P.
  • a wiring layer 100T-1 is provided having wiring including gates of the plurality of p-MOS transistors 112 and the plurality of n-MOS transistors 113 and wiring 122, 123 including pad electrodes 123X, etc., within the interlayer insulating layer 121.
  • a plurality of pad parts 124 used for bonding and electrical connection with the semiconductor layer 100S-2 are exposed.
  • the surface 100S3 of the semiconductor layer 100S-2 facing the semiconductor layer 100S-1 is provided with a plurality of p-MOS transistors and a plurality of n-MOS transistors constituting a readout circuit.
  • the surface 100S3 side of the semiconductor layer 100S-2 is provided with a wiring layer 100T-2 having wirings 142, 143 including wirings including gates of a plurality of p-MOS transistors and a plurality of n-MOS transistors within an interlayer insulating layer 141.
  • a plurality of pad portions 144 used for bonding and electrical connection with the semiconductor layer 100S-1 are exposed on the surface of the wiring layer 100T-2 (specifically, the surface of the interlayer insulating layer 141).
  • the surface 100S4 side of the semiconductor layer 100S-2 is provided with a wiring layer 100T-3 having wirings 146 within an interlayer insulating layer 145.
  • a plurality of pads 147 are exposed on the surface of the wiring layer 100T-3 (specifically, the surface of the interlayer insulating layer 145) to be used for bonding and electrical connection with the first CoW layer 200 and the second CoW layer 300.
  • the wiring layer 100T-2 and the wiring layer 100T-3 are electrically connected by, for example, a through-wire 148 that penetrates the semiconductor layer 100S-2.
  • the sensor substrate 100 and the first CoW layer 200, and the sensor substrate 100 and the second CoW layer 300 are electrically connected to each other by bonding a plurality of pad portions 147 and a plurality of pad portions 214, 314 exposed on the respective opposing surfaces.
  • FIG. 3 shows a flow of a manufacturing process for the image pickup devices 1 and 2 shown in Fig. 1 and Fig. 2.
  • the image pickup devices 1 and 2 can be manufactured, for example, as follows.
  • the first layer 210, the second layer 220, and the third layer 230 are connected to each other by CuCu bonding to form the first CoW layer 200 (step S101).
  • the sensor substrate 100, the first CoW layer 200, and the second CoW layer 300 are connected to each other by CuCu bonding, and the first CoW layer 200 and the second CoW layer 300 are mounted on the sensor substrate 100 (step S102).
  • step S103 the surfaces 200SS2, 300S2 of the first CoW layer 200 and the second CoW layer 300 are polished, for example, by chemical mechanical polishing (CMP) to thin them down to a predetermined thickness (step S103).
  • CMP chemical mechanical polishing
  • step S104 the space between the first CoW layer 200 and the second CoW layer 300 is filled with an insulating layer 410, for example, by chemical vapor deposition (CVD) (step S104).
  • CVD chemical vapor deposition
  • the surfaces of the film 410 formed on the surfaces 200SS2, 300S2 of the first CoW layer 200 and the second CoW layer 300 are planarized by CMP, and then the support substrate 400 is bonded to the surfaces 200SS2, 300S2 of the first CoW layer 200 and the second CoW layer 300.
  • the light receiving element 111, the color filter 131, and the light receiving lens 132 are formed on the surface 100S1 of the sensor substrate 100 by a back surface process.
  • FIG. 4 shows an example of the circuit configuration of the imaging devices 1 and 2.
  • Figs. 5 and 6 are exploded perspective views showing the manner of connection of the pixel array section 110 of the imaging device 2 shown in Fig. 2, for example.
  • the first CoW layer 200 is provided at a position corresponding to the pixel array section 110 of the sensor substrate 100, and as described above, three layers (first layer 210, second layer 220, and third layer 230) with different technology nodes are stacked.
  • the first layer 210 including the semiconductor layer 100S-2 of the sensor substrate 100, has an analog circuit formed therein, including a circuit configuration for amplifying pixel signals generated in a plurality of sensor pixels P and converting them into digital signals.
  • the analog circuit is a part of the image capture device 2, such as the analog-to-digital converter (ADC) 610 or a control unit that controls each unit in the image capture device 1, and has a circuit configuration to which a power supply voltage for the analog circuit is supplied.
  • ADC analog-to-digital converter
  • the analog circuit includes various transistors (readout circuits) that read out analog pixel signals from the sensor pixels P, a vertical drive circuit that drives the sensor pixels P arranged in a two-dimensional lattice in the row and column directions on a row-by-row basis, a comparator and counter of the ADC 610, a reference voltage supply unit that supplies a reference voltage to the comparator, a Phase Locked Loop (PLL) circuit, a load MOS, etc.
  • PLL Phase Locked Loop
  • the second layer 220 is formed with, for example, a logic circuit that corrects and modulates the digital signal converted in the analog circuit 210.
  • the second layer 220 is formed with a latch circuit 620, a sensor interface (SIF) 630, a digital unit (DU) 640, etc.
  • the second layer 220 may further be formed with an application processor (AP) etc. that includes a circuit configuration capable of machine learning such as a deep neural network (DNN).
  • DNN deep neural network
  • the third layer 230 includes a memory 650 such as a DRAM.
  • the third layer 230 includes a circuit section 660 including an interface driver (IFD) and a physical layer (PHY).
  • IFD interface driver
  • PHY physical layer
  • the imaging device 2 has a configuration capable of analog conversion on a pixel-by-pixel basis. Specifically, for example, a signal output from a sensor pixel P is converted on a pixel-by-pixel basis in an analog circuit, for example, a 22 nm node, in the first layer 210, and correction processing is performed in a logic circuit, for example, a 5 nm node, in the second layer 220.
  • a memory 650 is formed in the third layer 230, and is capable of linking with a learning function such as DNN.
  • FIG. 7 is an exploded perspective view showing the connection state of the peripheral portion 120 of the imaging device 2 shown in FIG. 2.
  • the second CoW layer 300 is mounted at a position corresponding to the peripheral portion 120 of the sensor substrate 100 as described above.
  • An interface circuit (IF) 670 is formed in the second CoW layer 300.
  • the IF 670 includes a circuit configuration that outputs data (digital signals) processed in a logic circuit or the like formed in the second layer 220 of the first CoW layer 200 to the outside.
  • the IF 670 is supplied with data processed in the DU 640 formed in the second layer 220 of the first CoW layer 200, and the data is output to the outside via a pad electrode 123X provided on the sensor substrate 100.
  • a first CoW layer 200 and a second CoW layer 300 are mounted side by side in the in-plane direction on a surface 100S2 side opposite to a light incident surface (surface 100S1) of a sensor substrate 100 on which a plurality of light receiving elements 111 are formed in an array. This allows a desired circuit chip to be mounted in a desired position. This will be described below.
  • image sensors with a three-dimensional structure have been developed in which the sensor section and control circuit section are fabricated on separate wafers and then stacked.
  • three-dimensional image sensors there is a tendency for the number of signal processing circuits for correction within the sensor to increase, and for the amount of memory required to hold the processing information to increase.
  • image sensors have been proposed that incorporate a single-layer chip that combines various functions into one chip, and image sensors that incorporate three or more layers of stacked chips.
  • a CoW layer (e.g., first CoW layer 200) consisting of multiple stacked semiconductor layers is mounted in locations where a large circuit area is required, and a single layer or a CoW layer with a small number of stacked layers (e.g., second CoW layer 300) is mounted in locations where a small circuit area is required, thereby making it possible to suppress increases in costs while achieving the desired circuit operation.
  • the imaging devices 1 and 2 of this embodiment are able to achieve both high functionality and reduced costs.
  • a CoW layer consisting of multiple semiconductor layers selectively stacked only in positions where a large circuit area is required, making it possible to reduce heat generation due to the density of stacked circuits.
  • the chip (second CoW layer 300) on which the IF circuit 670, which generates a large amount of heat, is formed has a single-layer structure, so that the heat generated in the IF circuit 670 can be dissipated to the support substrate 400. This makes it possible to reduce the occurrence of circuit defects due to chip heat generation.
  • a CoW layer made of multiple semiconductor layers is mounted in locations where a large circuit area is required, so the wiring distance can be shortened compared to when they are mounted side by side in a planar direction. This makes it possible to reduce signal delays and increases in power consumption.
  • CoW layers having multiple functions can be manufactured in parallel, which makes it possible to shorten the time required for manufacturing.
  • Fig. 8 is an exploded perspective view showing a connection state of a pixel array unit 110 of an imaging device (e.g., imaging device 2) according to Modification 1 of the present disclosure.
  • Fig. 9 is an exploded perspective view showing a connection state of a peripheral unit 120 of an imaging device (e.g., imaging device 2) according to Modification 1 of the present disclosure.
  • each sensor pixel P and the ADC 610 are connected on a circuit block basis, rather than on a pixel-by-pixel basis.
  • the imaging device 2 of this modified example has multiple vertical drive circuits and multiple (here, four) AD blocks 611, 612, 613, and 614 as the ADC 610.
  • the AD blocks 611 and 612 are provided in the semiconductor layer 100S-2 of the sensor substrate 100, and the AD blocks 613 and 614 are provided in the semiconductor layer 210S of the first layer 210 of the first CoW layer.
  • the multiple sensor pixels P arranged in an array in the pixel array section 110 are divided into multiple blocks (for example, four pixel blocks), and each pixel block is connected to the AD blocks 611, 612, 613, and 614 via vertical signal lines.
  • the pixel signals output from the AD blocks 611, 612, 613, and 614 are supplied in that order to the SIF 630 and DU 640 provided in the second layer 220.
  • each sensor pixel P is connected to the ADC 610 in circuit block units. This allows the imaging device 2 to achieve high-speed driving and complex driving in addition to the same effects as the above embodiment.
  • AD blocks 611, 612, 613, 614 are arranged separately in multiple semiconductor layers (for example, semiconductor layer 100S-2 and semiconductor layer 210S), making it possible to achieve high-speed driving and complex driving without increasing the size of the device.
  • Fig. 10 is a schematic diagram showing an example of a cross-sectional configuration of an imaging device (imaging device 3) according to an embodiment of the present disclosure.
  • Fig. 11 is a schematic diagram showing an example of a cross-sectional configuration of an imaging device (imaging device 4) according to an embodiment of the present disclosure.
  • Fig. 12 is a schematic diagram showing an example of a cross-sectional configuration of an imaging device (imaging device 5) according to an embodiment of the present disclosure.
  • the imaging device 3 of this modified example has the first CoW layer 200 consisting of two stacked layers (first layer 210 and second layer 220) and the second CoW layer 300 consisting of two stacked layers (first layer 310 and second layer 320) mounted side by side on the surface 100S2 side of the sensor substrate 100.
  • the imaging device 4 is provided with a first CoW layer 200 having three layers (first layer 210, second layer 220, and third layer 230) stacked on the surface 100S2 side of the sensor substrate 100, and a second CoW layer 300 having three layers (first layer 310, second layer 320, and third layer 330) stacked on the surface 100S2 side of the sensor substrate 100.
  • the imaging device 5 is provided with a first CoW layer 200 having three layers (first layer 210, second layer 220, and third layer 230) stacked on the surface 100S2 side of the sensor substrate 100, and a second CoW layer 300 having two layers (first layer 310 and second layer 320) stacked on the surface 100S2 side of the sensor substrate 100.
  • the second CoW layer 300 has a chip structure in which two or three semiconductor layers (first layer 310 and second layer 320 or first layer 310, second layer 320 and third layer 330) are stacked as described above.
  • the first layer 310, second layer 320 and third layer 330 may each have one or more circuits with the same technology node formed therein, or one or more circuits with different technology nodes formed therein.
  • the first layer 310 has a semiconductor layer 310S having a pair of opposing surfaces, and a wiring layer is provided on each of the pair of surfaces of the semiconductor layer 310S.
  • the second layer 320 has a semiconductor layer 320S having a pair of opposing surfaces, and a wiring layer is provided on each of the pair of surfaces of the semiconductor layer 320S.
  • the third layer 330 has a semiconductor layer 330S having a pair of opposing surfaces, and a wiring layer is provided on each of the pair of surfaces of the semiconductor layer 330S.
  • the semiconductor layers 310S, 320S, and 330S are each provided with a plurality of p-MOS transistors 311, 322, and 332 and a plurality of n-MOS transistors 312, 322, and 332.
  • a plurality of pad portions are exposed on the surfaces of the opposing wiring layers, and by bonding these, the first layer 310 and the second layer 220, and the second layer 220 and the third layer 230 are electrically connected to each other by hybrid bonding, similar to the first CoW layer 200.
  • the wiring layers provided on each pair of surfaces of the semiconductor layers 310S and 320S are electrically connected by through-wires 317 and 327 that penetrate the semiconductor layer 310S.
  • the semiconductor layers 310S, 320S, and 330S are, for example, made of a silicon substrate.
  • the semiconductor layers 310S, 320S, and 330S can be made of a semiconductor substrate made of germanium (Ge), selenium (Se), carbon (C), or the like.
  • the semiconductor layer 300S can be made of a compound semiconductor substrate made of silicon germanium (SiGe), gallium arsenide (GaAs), gallium phosphide (GaP), nickel antimonide (NiSb), indium antimonide (InSb), indium arsenide (InAs), indium phosphide (InP), gallium nitride (GaN), silicon carbide (SiC), or indium gallium arsenide (InGaAs).
  • the semiconductor layer 300S can be made of a one-dimensional material such as a carbon nanotube, or a two-dimensional material such as a transition metal dichalcogenide (TMD) or graphene.
  • TMD transition metal dichalcogenide
  • the multiple p-MOS transistors 311, 322, 332 and the multiple n-MOS transistors 312, 322, 332 provided in the semiconductor layers 310S, 320S, 330S may be made using different semiconductor materials.
  • SiGe or Ge may be used for the p-MOS transistors 311, 322, 332, and Si material may be used for the n-MOS transistors 312, 322, 332.
  • Si material may be used for the p-MOS transistors 311, 322, 332, and GaN, GaAs, nGaAs, etc. may be used for the n-MOS transistors 312, 322, 332.
  • the first CoW layer 200 and the second CoW layer 300 mounted on the surface 100S2 side of the sensor substrate 100 may each have two or three semiconductor layers stacked together, as in the imaging devices 3 and 4 shown in Figures 10 and 11.
  • the first CoW layer 200 may have three semiconductor layers stacked together and the second CoW layer 300 may have two semiconductor layers stacked together.
  • the imaging devices 3 to 5 of this modified example can achieve the same effects as the above embodiment.
  • first CoW layer 200 may be a stack of two semiconductor layers and the second CoW layer 300 may be a single layer, or the first CoW layer 200 and the second CoW layer 300 may each be a stack of four or more semiconductor layers.
  • FIG. 13 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 6) according to an embodiment of the present disclosure.
  • the pad electrodes 123X are provided in the wiring layer 100T of the sensor substrate 100 and are connected to the outside from the surface 100S1 side via the pad electrodes 123X exposed by the openings H, but this is not limited to the example.
  • the imaging device 6 of this modified example has terminals (bumps 515) for external connection provided on the surfaces of the first CoW layer 200 and the second CoW layer 300 opposite the surfaces facing the sensor substrate 100.
  • insulating layers 410, 510 are laminated on the surfaces of the first CoW layer 200 and the second CoW layer 300 opposite the surfaces facing the sensor substrate 100.
  • Conductive films 511, 512, 513 are embedded in the insulating layers 410, 510.
  • a through electrode 514 that penetrates the semiconductor layer 320S, for example, is connected to the conductive film 511 embedded in the insulating layer 410, and the conductive film 513 is exposed on the surface of the insulating layer 510.
  • a bump 515 used for connection to the outside is formed on the conductive film 513.
  • a light-transmitting resin layer 610 and a glass substrate 620 may be provided on the surface 100S1 side of the sensor substrate 100.
  • FIG. 14 shows an example of the configuration of a circuit block with a communication chip mounted on the first CoW layer 200 and the second CoW layer 300.
  • AFE analog front-end
  • RF-IC radio frequency integrated circuit
  • BB baseband circuit 683
  • a compound semiconductor substrate can be used for the semiconductor layer 320S of the second layer 320 on which the AFE circuit section 681 is formed.
  • a silicon substrate can be used for the semiconductor layer 310S of the first layer 310 on which the RF-IC 682 is formed.
  • a terminal for external connection on the surface of the second CoW layer 300 opposite the surface facing the sensor substrate 100, and to provide a light-transmitting resin layer 610 and a glass substrate 620 on the surface 100S1 side of the sensor substrate 100.
  • FIG. 21 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 7) according to Modification 4 of the present disclosure.
  • the imaging device 7 of this modified example is formed by stacking the second layer 320 and the third layer 330, each of which includes a dummy semiconductor layer 320SA, 330SA, on the first layer 310 of the second CoW layer 300 so as to match the height of each of the semiconductor layers 210S, 220S, and 230S of the first layer 210, second layer 220, and third layer 230 constituting the first CoW layer 200. Except for this point, the imaging device 7 has a substantially similar configuration to the imaging device 2 of the above embodiment.
  • the second CoW layer 300 like the first CoW layer 200, has a chip structure in which multiple semiconductor layers (here, the first layer 310, the second layer 320, and the third layer 330) are stacked.
  • the first layer 310 has a semiconductor layer 310S having a pair of opposing surfaces, and a wiring layer 300T is provided on the surface 200S1 side of the pair of surfaces of the semiconductor layer 310S.
  • the semiconductor layer 310S is provided with multiple p-MOS transistors 311 and multiple n-MOS transistors 312.
  • the second layer 320 has a semiconductor layer 320SA having a pair of opposing surfaces, and insulating layers 325A and 325B are provided on the pair of surfaces of the semiconductor layer 320SA, respectively.
  • the third layer 330 has a semiconductor layer 330SA having a pair of opposing surfaces, and an insulating layer 325 is provided on the surface of the semiconductor layer 330SA facing the second layer 220.
  • semiconductor layers 320SA and 330SA are dummy semiconductor layers, and unlike semiconductor layer 310S, no p-MOS transistors or n-MOS transistors are provided.
  • the first layer 310 and the second layer 320, and the second layer 320 and the third layer 330 are bonded to each other by insulating layers 315 and 325A, and insulating layers 325B and 335, respectively.
  • the first layer 210 of the first CoW layer 200 and the first layer 310 of the second CoW layer 300 are connected to the sensor substrate 100 by CuCu bonding.
  • the semiconductor layers 210S, 310S constituting the first layers 210, 310 of the first CoW layer 200 and the second CoW layer 300 are polished, for example, by CMP to thin them to a predetermined thickness.
  • the space between the semiconductor layer 210S and the semiconductor layer 310S is filled with an insulating layer 410, for example, by a CVD method.
  • the insulating layer 410 formed on the semiconductor layers 210S and 310S is removed by polishing using, for example, CMP, and then the wiring layer 210T-2 is formed on the semiconductor layer 210S, and the insulating layer 315 is formed on the semiconductor layer 310S.
  • the second layers 220 and 320 are connected to the first layers 210 and 310, respectively, by CuCu bonding.
  • the semiconductor layers 220S, 320SA constituting the second layers 220, 320 of the first CoW layer 200 and the second CoW layer 300 are polished, for example, by CMP to thin them to a predetermined thickness.
  • the space between the semiconductor layer 220S and the semiconductor layer 320SA is filled with an insulating layer 410, for example, by a CVD method.
  • the insulating layer 410 formed on the semiconductor layers 220S and 320SA is removed by polishing, for example, by CMP, and then the wiring layer 220T-2 is formed on the semiconductor layer 220S, and the insulating layer 325B is formed on the semiconductor layer 320SA.
  • the third layers 230 and 330 are connected to the second layers 220 and 320, respectively, by CuCu bonding.
  • the semiconductor layers 230S, 330SA constituting the third layers 230, 330 of the first CoW layer 200 and the second CoW layer 300 are polished, for example, by CMP to thin them to a predetermined thickness.
  • the space between the semiconductor layer 230S and the semiconductor layer 330SA is filled with an insulating layer 410, for example, by a CVD method.
  • the support substrate 400 is bonded onto the insulating layer 410, and the light receiving element 111, the color filter 131, and the light receiving lens 132 are formed on the surface 100S1 side of the sensor substrate 100 by a back surface process. This completes the imaging device 7 shown in FIG. 21.
  • the manufacturing process of the imaging device 7 is not limited to this.
  • the first layer 210, the second layer 220, and the third layer 230 constituting the first CoW layer 200, and the first layer 310, the second layer 320, and the third layer 330 constituting the second CoW layer 300 may be connected in advance to form the first CoW layer 200 and the second CoW layer 300, respectively, and then the sensor substrate 100 may be connected to the first CoW layer 200 and the second CoW layer 300 by CuCu bonding.
  • the second layer 320 and the third layer 330 including the dummy semiconductor layers 320SA and 330SA are laminated on the surface 300S2 side of the first layer 310 of the second CoW layer 300 so as to match the height of the semiconductor layers 210S, 220S, and 230S of the first layer 210, second layer 220, and third layer 230 constituting the first CoW layer 200.
  • the imaging device 7 of this modification has the same heights of the semiconductor layers 210S and 310S of the first layers 210 and 310, the semiconductor layers 220S and 320SA of the second layers 220 and 320, and the semiconductor layers 230S and 330SA of the third layers 230 and 330 constituting the first CoW layer 200 and the second CoW layer 300, making it easier to flatten by grinding.
  • the imaging device 7 of this modified example as described above, the first CoW layer 200 and the second CoW layer 300 have the same semiconductor layer configuration, so that the thermal expansion coefficients of the first CoW layer 200 and the second CoW layer 300 can be matched. Therefore, compared to the imaging device 1 of the above embodiment, the imaging device 7 of this modified example can improve heat dissipation performance and strength.
  • the first layers 210, 310, second layers 220, 320, and third layers 230, 330 of the first CoW layer 200 and second CoW layer 300 are stacked on the sensor substrate 100 in order with the thickness of each layer being uniform, so that the embedding depth of the insulating layer 410 is shallow. Therefore, for example, it is easier to flatten the insulating layer embedded between the first CoW layer 200 and the second CoW layer 300, compared to the above embodiment in which the first CoW layer 200 and the second CoW layer 300 are formed in advance and then the sensor substrate 100 and the first CoW layer 200 and the second CoW layer 300 are connected to each other by CuCu bonding.
  • FIG. 23 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 7A) according to Modification 5 of the present disclosure.
  • the first layer 310 and the second layer 320, and the second layer 320 and the third layer 330 constituting the second CoW layer 300 are bonded to each other by the insulating layer 315 and the insulating layer 325A, and the insulating layer 325B and the insulating layer 335, respectively, but the present invention is not limited to this.
  • a plurality of pad portions 316, 324, 326, and 334 are provided on the surfaces of the insulating layers 315, 325A, 325B, and 335 that are bonded to each other, and are connected to each other by hybrid bonding. Except for this point, the imaging device 7A has a configuration substantially similar to that of the imaging device 7 of the above-mentioned modification 4.
  • the imaging device 7A of this modified example the first layer 310 and the second layer 320, and the second layer 320 and the third layer 330 constituting the second CoW layer 300, are connected by hybrid junctions, respectively. Even with this configuration, the imaging device 7A of this modified example can obtain the same effects as the modified example 7 described above.
  • FIG. 24 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 8) according to Modification 6 of the present disclosure.
  • the semiconductor layer 210S of the first layer 210, the semiconductor layer 220S of the second layer 220, and the semiconductor layer 230S of the third layer 230 constituting the first CoW layer 200 have the same size, but this is not limited to this.
  • the second layer 220 constituting the first CoW layer 200 includes two semiconductor layers 220A and 220B that are smaller than the semiconductor layers 210S and 230S of the first layer 210 and the third layer 230. Except for this point, the imaging device 8 has a configuration substantially similar to that of the imaging device 1 of the above embodiment.
  • this technology can be combined with any of the above-mentioned embodiments and modifications 1 to 5.
  • this technology can be applied to a configuration in which a semiconductor layer 100S-1 in which a photodiode PD is embedded in each of a plurality of sensor pixels P is stacked, as in the image pickup device 8A shown in FIG. 25, and a semiconductor layer 100S-2 having a readout circuit that outputs a pixel signal based on the charge output from the sensor pixel P are stacked.
  • this technology can be applied to a configuration in which a first CoW layer 200 has three layers and a second CoW layer 300 has two layers, as in the image pickup device 8B shown in FIG. 26.
  • the second layer 220 constituting the first CoW layer 200 includes two semiconductor layers 220A and 220B that are smaller than the semiconductor layers 210S and 230S of the first layer 210 and the third layer 230.
  • a general-purpose chip such as a DRAM can be used, the imaging devices 8, 8A, and 8B of this modified example can achieve even higher functionality and reduced costs compared to the above embodiment.
  • FIG. 27 is a schematic diagram illustrating an example of a cross-sectional configuration of an imaging device (imaging device 9) according to the sixth modification of the present disclosure.
  • the second layer 220 constituting the first CoW layer 200 includes two semiconductor layers 220A, 220B smaller than the semiconductor layers 210S, 230S of the first layer 210 and the third layer 230, but this is not limited to the above.
  • the first CoW layer 200 includes a third layer 230 on the support substrate 401, in which multiple semiconductor layers (here, two semiconductor layers 230SA, 230SB) smaller than the semiconductor layers 210S, 220S of the first layer 210 and the second layer 220 are arranged side by side. Except for this point, the imaging device 8 has a substantially similar configuration to the imaging device 1 of the above-mentioned embodiment.
  • this technology can be combined with any of the above-mentioned embodiments and modifications 1 to 6.
  • this technology can be applied to a configuration in which a semiconductor layer 100S-1 in which a photodiode PD is embedded in each of a plurality of sensor pixels P and a semiconductor layer 100S-2 having a readout circuit that outputs a pixel signal based on the charge output from the sensor pixel P are stacked, as in the image pickup device 9A shown in FIG. 28.
  • this technology can be applied to the third layer 230 of the first CoW layer 200, in which the first CoW layer 200 is stacked with three semiconductor layers and the second CoW layer 300 is stacked with two semiconductor layers, as in the image pickup device 8B shown in FIG. 29.
  • this technology can be applied to the second layer 220 of the first CoW layer 200, in which the first CoW layer 200 is stacked with two semiconductor layers and the second CoW layer 300 is stacked with one semiconductor layer, as in the image pickup device 9C shown in FIG. 30.
  • the semiconductor layer mounted closest to the support substrate 400 in the first CoW layer 200 (e.g., the semiconductor layer 230S of the third layer 230) is made smaller than the semiconductor layers of the other layers (e.g., the semiconductor layers 210S and 220S of the first layer 210 and the second layer 220), and a plurality of these (here, two semiconductor layers 230SA and 230SB) are stacked side by side on the support substrate 401.
  • a general-purpose chip such as a DRAM can be used, the imaging devices 9, 9A, 9B, and 9C of this modification can achieve even higher functionality and reduced costs compared to the above embodiment.
  • FIG. 15 shows an example of a schematic configuration of an imaging system 10 including an imaging device (eg, imaging device 1) according to the above-described embodiment and modifications 1 to 4.
  • an imaging device eg, imaging device 1
  • the imaging system 10 is, for example, an electronic device such as a camera, such as a digital still camera or a video camera, or a mobile terminal device, such as a smartphone or a tablet terminal.
  • the imaging system 10 includes, for example, an imaging device 1, an optical system 741, a shutter device 742, a DSP circuit 743, a frame memory 744, a display unit 745, a storage unit 746, an operation unit 747, and a power supply unit 748.
  • the imaging device 1, the DSP circuit 743, the frame memory 744, the display unit 745, the storage unit 746, the operation unit 747, and the power supply unit 748 are connected to each other via a bus line 749.
  • the imaging device 1 outputs image data according to the incident light.
  • the optical system 741 is configured with one or more lenses, and guides light (incident light) from a subject to the imaging device 1, forming an image on the light receiving surface of the imaging device 1.
  • the shutter device 742 is disposed between the optical system 741 and the imaging device 1, and controls the light irradiation period and the light blocking period to the imaging device 1 according to the control of the drive circuit.
  • the DSP circuit 743 is a signal processing circuit that processes the signal (image data) output from the imaging device 1.
  • the frame memory 744 temporarily holds the image data processed by the DSP circuit 743 on a frame-by-frame basis.
  • the display unit 745 is, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays the moving image or still image captured by the imaging device 1.
  • the storage unit 746 records the image data of the moving image or still image captured by the imaging device 1 in a recording medium such as a semiconductor memory or a hard disk.
  • the operation unit 747 issues operation commands for various functions of the imaging system 10 in accordance with operations by the user.
  • the power supply unit 748 appropriately supplies various types of power to these targets as operating power sources for the imaging device 1, the DSP circuit 743, the frame memory 744, the display unit 745, the storage unit 746, and the operation unit 747.
  • FIG. 16 shows an example of a flowchart of the imaging operation in the imaging system 10.
  • the user operates the operation unit 747 to instruct the start of imaging (step S201).
  • the operation unit 747 then transmits an imaging command to the imaging device 1 (step S202).
  • the imaging device 1 specifically, the system control circuit
  • the imaging device 1 outputs image data obtained by imaging to the DSP circuit 743.
  • image data refers to data for all pixels of pixel signals generated based on the charges temporarily stored in the floating diffusion FD.
  • the DSP circuit 743 performs predetermined signal processing (e.g., noise reduction processing) based on the image data input from the imaging device 1 (step S204).
  • the DSP circuit 743 stores the image data that has been subjected to the predetermined signal processing in the frame memory 744, and the frame memory 744 stores the image data in the storage unit 746 (step S205). In this manner, imaging is performed in the imaging system 10.
  • the imaging device according to the above embodiment and its modified examples 1 to 4 (for example, imaging device 1) is applied to imaging system 10.
  • imaging device 1 is applied to imaging system 10.
  • the technology according to the present disclosure (the present technology) can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.
  • FIG. 17 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 functions as a control device for a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
  • the body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps.
  • radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020.
  • the body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
  • the outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030.
  • the outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle, and receives the captured images.
  • the outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface, based on the received images.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received.
  • the imaging unit 12031 can output the electrical signal as an image, or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects information inside the vehicle.
  • a driver state detection unit 12041 that detects the state of the driver is connected.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
  • the microcomputer 12051 can calculate the control target values of the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output a control command to the drive system control unit 12010.
  • the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating vehicle collisions, following the vehicle based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 can also perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.
  • the microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.
  • the audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • FIG. 18 shows an example of the installation position of the imaging unit 12031.
  • the vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100.
  • the imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100.
  • the imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100.
  • the images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
  • FIG. 18 shows an example of the imaging ranges of the imaging units 12101 to 12104.
  • Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door.
  • an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 can obtain the distance to each solid object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on the driver's operation.
  • automatic braking control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles.
  • the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, it can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by forcibly decelerating or steering to avoid a collision via the drive system control unit 12010.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured image of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian.
  • the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian.
  • the audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology of the present disclosure can be applied to the imaging unit 12031.
  • the imaging device 1 according to the above embodiment and its modified example can be applied to the imaging unit 12031.
  • FIG. 19 is a diagram showing an example of the general configuration of an endoscopic surgery system to which the technology disclosed herein (the present technology) can be applied.
  • an operator (doctor) 11131 is shown using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a patient bed 11153.
  • the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.
  • the endoscope 11100 is composed of a lens barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 at a predetermined length, and a camera head 11102 connected to the base end of the lens barrel 11101.
  • the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.
  • the tip of the tube 11101 has an opening into which an objective lens is fitted.
  • a light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the tube by a light guide extending inside the tube 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132.
  • the endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.
  • An optical system and an image sensor are provided inside the camera head 11102, and the reflected light (observation light) from the object of observation is focused on the image sensor by the optical system.
  • the observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image.
  • the image signal is sent to the camera control unit (CCU: Camera Control Unit) 11201 as RAW data.
  • CCU Camera Control Unit
  • the CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and controls the overall operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), in order to display an image based on the image signal.
  • a CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • the display device 11202 under the control of the CCU 11201, displays an image based on the image signal that has been subjected to image processing by the CCU 11201.
  • the light source device 11203 is composed of a light source such as an LED (Light Emitting Diode) and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.
  • a light source such as an LED (Light Emitting Diode) and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.
  • the input device 11204 is an input interface for the endoscopic surgery system 11000.
  • a user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204.
  • the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.
  • the treatment tool control device 11205 controls the operation of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc.
  • the insufflation device 11206 sends gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity in order to ensure a clear field of view for the endoscope 11100 and to ensure a working space for the surgeon.
  • the recorder 11207 is a device capable of recording various types of information related to the surgery.
  • the printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.
  • the light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these.
  • a white light source composed of, for example, an LED, a laser light source, or a combination of these.
  • the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203.
  • the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals.
  • the image sensor of the camera head 11102 may be controlled to acquire images in a time-division manner in synchronization with the timing of the change in the light intensity, and the images may be synthesized to generate an image with a high dynamic range that is free of so-called blackout and whiteout.
  • the light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to special light observation.
  • special light observation for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band of light is irradiated compared to the light irradiated during normal observation (i.e., white light), and a specific tissue such as blood vessels on the surface of the mucosa is photographed with high contrast, so-called narrow band imaging is performed.
  • fluorescence observation may be performed in which an image is obtained by fluorescence generated by irradiating excitation light.
  • excitation light is irradiated to body tissue and fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally injected into the body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated to the body tissue to obtain a fluorescent image.
  • the light source device 11203 may be configured to supply narrow band light and/or excitation light corresponding to such special light observation.
  • FIG. 20 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in FIG. 19.
  • the camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405.
  • the CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413.
  • the camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.
  • the lens unit 11401 is an optical system provided at the connection with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401.
  • the lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.
  • the imaging unit 11402 is composed of an imaging element.
  • the imaging element constituting the imaging unit 11402 may be one (so-called single-plate type) or multiple (so-called multi-plate type).
  • each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these.
  • the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site.
  • 3D dimensional
  • the imaging unit 11402 does not necessarily have to be provided in the camera head 11102.
  • the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.
  • the driving unit 11403 is composed of an actuator, and moves the zoom lens and focus lens of the lens unit 11401 a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.
  • the communication unit 11404 is configured with a communication device for transmitting and receiving various information to and from the CCU 11201.
  • the communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.
  • the communication unit 11404 also receives control signals for controlling the operation of the camera head 11102 from the CCU 11201, and supplies them to the camera head control unit 11405.
  • the control signals include information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during imaging, and/or information specifying the magnification and focus of the captured image.
  • the camera head control unit 11405 controls the operation of the camera head 11102 based on a control signal from the CCU 11201 received via the communication unit 11404.
  • the communication unit 11411 also transmits to the camera head 11102 a control signal for controlling the operation of the camera head 11102.
  • the image signal and the control signal can be transmitted by electrical communication, optical communication, etc.
  • the image processing unit 11412 performs various image processing operations on the image signal, which is the RAW data transmitted from the camera head 11102.
  • the transmission cable 11400 that connects the camera head 11102 and the CCU 11201 is an electrical signal cable that supports electrical signal communication, an optical fiber that supports optical communication, or a composite cable of these.
  • the first substrate and the second substrate, and the first substrate and the third substrate are electrically connected to each other by CuCu bonding, an insulating film is embedded between the second substrate and the third substrate;
  • a common support substrate is provided on the surfaces of the second substrate and the third substrate opposite to the bonding surface with the first substrate.
  • the second substrate and the third substrate include, as the plurality of semiconductor layers, a dummy semiconductor layer that does not have the one or more circuits.
  • the dummy semiconductor layer is joined to another semiconductor layer by an insulating film.
  • the second substrate and the third substrate include semiconductor layers having different sizes as the plurality of semiconductor layers.
  • at least a portion of the one or more semiconductor layers constituting the second substrate and the third substrate includes a plurality of semiconductor layers arranged side by side in an in-plane direction.
  • the second substrate has, as the plurality of semiconductor layers, a third semiconductor layer having a plurality of analog circuits and a fourth semiconductor layer having a plurality of logic circuits; The semiconductor device according to (14), wherein the third semiconductor layer and the fourth semiconductor layer are stacked in this order from the first substrate side.
  • the third semiconductor layer has a comparator, a negative MOS, and an analog-to-digital converter circuit as the plurality of analog circuits;
  • the fourth semiconductor layer includes a latch circuit, a sensor interface circuit, and a digital unit circuit as the plurality of logic circuits;
  • the semiconductor device according to (15), wherein the analog circuits are connected to the logic circuits.
  • the second substrate further includes a fifth semiconductor layer having a memory element as the plurality of semiconductor layers.
  • the second substrate further includes a sixth semiconductor layer having an interface circuit as the plurality of semiconductor layers.
  • the plurality of pixels are divided into a plurality of pixel blocks, The semiconductor device according to any one of (11) to (18), wherein the circuits provided in the semiconductor layers constituting the second substrate are electrically connected to the pixel blocks, respectively.
  • the second substrate has, as the plurality of semiconductor layers, a third semiconductor layer having a plurality of analog circuit units and a fourth semiconductor layer having a plurality of logic circuit units; The semiconductor device according to (19), wherein the third semiconductor layer and the fourth semiconductor layer are stacked in this order from the first substrate side.
  • the third semiconductor layer has a plurality of analog-to-digital converter blocks as the plurality of analog circuit units; the plurality of pixel blocks and the plurality of analog-to-digital converter blocks are connected to each other via vertical signal lines;
  • the second substrate further includes a fifth semiconductor layer having a memory element as the plurality of semiconductor layers.
  • the semiconductor device according to (26), wherein the one-dimensional material is a carbon nanotube.
  • the semiconductor device according to (26), wherein the two-dimensional material is a transition metal dichalcogenide or graphene.
  • the semiconductor device according to any one of (1) to (28), wherein the plurality of semiconductor layers are made of a compound semiconductor.
  • the plurality of semiconductor layers include a semiconductor layer having an n-MOS transistor and a semiconductor layer having a p-MOS transistor; the semiconductor layer having the n-MOS transistor is made of silicon;
  • the semiconductor device according to any one of (1) to (29), wherein the semiconductor layer having the p-MOS transistor is made of silicon germanium or germanium.
  • the plurality of semiconductor layers include a semiconductor layer having an n-MOS transistor and a semiconductor layer having a p-MOS transistor; the semiconductor layer having the n-MOS transistor is made of a compound semiconductor; The semiconductor device according to any one of (1) to (30), wherein the semiconductor layer having the p-MOS transistor is made of silicon.
  • the third substrate further includes an optically transparent substrate on the first surface side of the first substrate, and an electrode provided on a surface of the third substrate opposite to the surface facing the first substrate and used for connection to an external device,
  • the semiconductor device according to any one of (1) to (33), wherein the first substrate and the electrode are electrically connected via a through electrode penetrating the third substrate.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
PCT/JP2024/010258 2023-03-17 2024-03-15 半導体装置 Ceased WO2024195725A1 (ja)

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JP2023042942A (ja) 2021-09-15 2023-03-28 高砂熱学工業株式会社 データセンターの空調システム

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JP2001036054A (ja) * 1999-07-19 2001-02-09 Mitsubishi Electric Corp Ｓｏｉ基板の製造方法
WO2017038403A1 (ja) * 2015-09-01 2017-03-09 ソニー株式会社 積層体
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JP2023042942A (ja) 2021-09-15 2023-03-28 高砂熱学工業株式会社 データセンターの空調システム

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TW202504081A (zh) 2025-01-16

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