WO2024183153A1 - 3d堆叠的半导体器件及其制造方法、电子设备 - Google Patents

3d堆叠的半导体器件及其制造方法、电子设备 Download PDF

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Publication number
WO2024183153A1
WO2024183153A1 PCT/CN2023/093997 CN2023093997W WO2024183153A1 WO 2024183153 A1 WO2024183153 A1 WO 2024183153A1 CN 2023093997 W CN2023093997 W CN 2023093997W WO 2024183153 A1 WO2024183153 A1 WO 2024183153A1
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Prior art keywords
layer
bit line
substrate
trench
semiconductor device
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English (en)
French (fr)
Inventor
艾学正
王祥升
王桂磊
赵超
桂文华
王海玲
刘晓萌
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the embodiments of the present disclosure relate to but are not limited to the field of semiconductor devices, and in particular to a 3D stacked semiconductor device, a manufacturing method thereof, and an electronic device.
  • DRAM dynamic random access memory
  • An embodiment of the present disclosure provides a method for manufacturing a 3D stacked semiconductor device, the method for manufacturing a 3D stacked semiconductor device comprising:
  • the second insulating layer is removed by etching to expose the dummy bit line layer between adjacent first insulating layers.
  • Each of the film layers is longitudinally etched to form a plurality of columns extending along the second direction and spaced apart in the first direction, each of the columns comprising a first conductive region, a semiconductor region, and a second conductive region; a surrounding gate insulating layer and a gate electrode are formed on the side walls of the semiconductor region of the column, and a word line is formed extending in a direction perpendicular to the substrate.
  • the substrate is a single crystal substrate
  • the dummy bit line layer is a single crystal film layer
  • the dummy bit line layer is made of the same material as the substrate
  • the etching of a plurality of first grooves extending toward the substrate in the stacked structure comprises:
  • the forming of a dummy bit line layer filling the first trench in the first trench comprises:
  • the dummy bit line layer extending into the first trench and filling the first trench is grown on the exposed substrate by a selective epitaxial process.
  • the film layer is a single crystal film layer, and the film layer and the dummy bit line layer are made of the same material;
  • the forming of a film layer filled between adjacent first insulating layers on the exposed sidewalls of the dummy bit line layer comprises:
  • dummy bit line layer as a seed layer, and using a selective epitaxial process to grow a first conductive layer extending along the first direction and the second direction on the exposed sidewalls of the dummy bit line layer;
  • a second conductive layer extending along the first direction and the second direction is grown on an end of the semiconductor layer away from the dummy bit line layer by a selective epitaxial process, wherein the first conductive layer forms the first conductive region of the film layer, and the semiconductor layer forms the semiconductor region of the film layer.
  • the second conductive layer forms the second conductive region of the membrane layer.
  • the step of growing a first conductive layer extending along the first direction and the second direction on the exposed sidewall of the dummy bit line layer using a selective epitaxial process may include:
  • Single crystal silicon is grown on the exposed sidewalls of the dummy bit line layer by adopting a selective epitaxial process, and an in-situ doping method is adopted during the growth of the single crystal silicon to obtain the first conductive layer formed of first doped single crystal silicon.
  • the step of growing a semiconductor layer along the first direction and the second direction at an end of the first conductive layer away from the dummy bit line layer using a selective epitaxial process includes:
  • a selective epitaxial process is adopted to grow intrinsic single crystal silicon at one end of the first conductive layer away from the dummy bit line layer, so as to obtain the semiconductor layer formed of intrinsic single crystal silicon.
  • the step of growing a second conductive layer extending along the first direction and the second direction at an end of the semiconductor layer away from the dummy bit line layer by using a selective epitaxial process comprises:
  • a selective epitaxial process is used to grow single crystal silicon at one end of the semiconductor layer away from the dummy bit line layer, and an in-situ doping method is used to dope the single crystal silicon during its growth to obtain the second conductive layer formed of second doped single crystal silicon.
  • the longitudinally etching each of the film layers to form a plurality of pillars extending along the second direction and spaced apart in the first direction may include:
  • Each of the film layers is longitudinally etched to form a plurality of third grooves extending along the second direction and spaced apart along the first direction in the film layer, wherein the third grooves space the film layer into a plurality of the pillars.
  • the method for manufacturing the 3D stacked semiconductor device may further include, after forming a film layer filled between adjacent first insulating layers and before spacing the film layer into a plurality of the pillars, performing the following steps:
  • a third electrode of the capacitor is formed at an end of the film layer away from the dummy bit line layer and in contact with the end, and a first insulating layer covering the third electrode and the second groove is deposited on the substrate. layer;
  • the dummy bit line layer in the first trench is removed by etching, so that the first trench exposes the film layer and the first insulating layer.
  • the method for manufacturing the 3D stacked semiconductor device may further include, after the film layer is spaced into a plurality of the pillars, performing the following steps:
  • a dielectric layer and a fourth electrode are sequentially deposited on the exposed surface of the third electrode, and the third electrode, the dielectric layer and the fourth electrode constitute a capacitor.
  • the forming of the third electrode of the capacitor in contact with the end of the film layer away from the dummy bit line layer may include:
  • a third conductive layer covering the end of the film layer exposed by the second groove is deposited on the substrate using polysilicon or metal to form a third electrode.
  • the forming of the third electrode of the capacitor in contact with the end of the film layer away from the dummy bit line layer may include:
  • a selective epitaxial process is used to grow single crystal silicon at the end of the film layer exposed by the second groove, and an in-situ doping method is used during the growth of the single crystal silicon to obtain a third conductive layer formed by doped single crystal silicon to form a third electrode.
  • forming a surrounding gate insulating layer and a gate electrode on a sidewall of the semiconductor region of the pillar may include:
  • a portion of the gate electrode layer between two adjacent semiconductor pillars distributed along the first direction is removed by etching, and only the gate electrode layer on the side walls of the two semiconductor pillars is retained to obtain a gate electrode.
  • the method for manufacturing the 3D stacked semiconductor device may further include, after removing the dummy bit line layer in the first trench and before forming the third trench, performing the following steps:
  • the first conductive regions of the film layer on both sides of the first trench are etched back to form a bit line groove extending into the first conductive region of the film layer and extending along the first direction, and a bit line is deposited in the bit line groove.
  • the method for manufacturing the 3D stacked semiconductor device may further include, after removing the dummy bit line layer in the first trench and before forming the bit line trench, performing the following steps:
  • the first insulating layer on both sides of the first trench is etched back to form a supporting groove extending into the first insulating layer and extending along the first direction, and a second insulating layer is deposited in the supporting groove to form a supporting layer.
  • the method for manufacturing the 3D stacked semiconductor device may further include, after forming the bit line and before forming the third trench, performing the following steps:
  • a third insulating layer is deposited in the first trench, and the third insulating layer separates two adjacent bit lines located in the same first trench.
  • the present disclosure also provides a 3D stacked semiconductor device, the 3D stacked semiconductor device comprising:
  • Each of the memory cells comprises a transistor; the transistor comprises a column extending along the second direction and a gate electrode surrounding the sidewall of the column, the column sequentially comprising a first conductive region, a semiconductor region and a second conductive region;
  • the semiconductor region includes the main material of the column, the first conductive region includes a first doping material, and the second conductive region includes a second doping material; the first doping material is uniformly distributed in the first conductive region, and the second doping material is uniformly distributed in the second conductive region.
  • the main body material may be single crystal silicon, single crystal germanium, single crystal silicon carbide or single crystal gallium arsenide.
  • the main body material may be single crystal silicon, and the main body material does not contain germanium.
  • the main body material may be single crystal germanium, and the main body material does not contain silicon.
  • the 3D stacked semiconductor device may further include: a plurality of bit lines extending along the first direction and spaced apart in a direction perpendicular to the substrate, the first conductive region of the pillar being connected to the bit lines.
  • the 3D stacked semiconductor device may further include: a plurality of word lines extending in a direction perpendicular to the substrate, the word lines surrounding sidewalls of the pillars.
  • the columns of transistors of multiple storage cells located in the same layer and distributed along the first direction are connected to the same bit line, and two adjacent columns connected to the same bit line are connected through a connecting portion, and the column and the connecting portion are an integrated structure.
  • one end of each of the pillars connected to the same bit line and the connecting portion can form a film layer extending along the first direction, the film layer is connected to the bit line, and the orthographic projection of the film layer on the substrate overlaps with the orthographic projection of the bit line on the substrate.
  • outer contours of the cross-section of the word line at different positions in the extending direction of the word line may be the same.
  • the storage unit also includes a capacitor connected to one end of the column, and the capacitor may include a third electrode connected to the second conductive region of the column, a fourth electrode, and a dielectric layer arranged between the third electrode and the fourth electrode.
  • the fourth electrodes of the capacitors of two columns of memory cells distributed in a direction perpendicular to the substrate and spaced apart in the second direction are common electrodes.
  • the fourth electrodes of the capacitors of a column of memory cells located in the same layer and distributed along the first direction may be an integrated structure.
  • the transistors and capacitors of the two columns of memory cells are distributed in a mirror image.
  • the third electrode is formed on the second conductive region of the column using an epitaxial process, the material of the third electrode is single crystal silicon, and the third electrode has the same cross-section as the first conductive region, the second conductive region, and the semiconductor region of the column.
  • An embodiment of the present disclosure further provides an electronic device, which includes the 3D stacked semiconductor device provided by the above embodiment of the present disclosure.
  • FIG. 1 is a process flow chart of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG. 2A is a schematic diagram of a three-dimensional structure of a method for manufacturing a 3D stacked semiconductor device after a stacked structure is formed according to an exemplary embodiment of the present disclosure
  • FIG2B is a cross-sectional view of the structure shown in FIG2A on a C1 plane parallel to the substrate;
  • FIG2C is a cross-sectional view of the structure shown in FIG2A on a C2 plane perpendicular to the substrate;
  • FIG2D is a cross-sectional view of the structure shown in FIG2A on a C3 plane perpendicular to the substrate;
  • 3A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after forming a first trench on a C1 plane parallel to a substrate;
  • FIG3B is a cross-sectional view of the structure shown in FIG3A on a C3 plane perpendicular to the substrate;
  • 4A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after forming a dummy bit line layer on a C1 plane parallel to a substrate;
  • FIG4B is a cross-sectional view of the structure shown in FIG4A on a C3 plane perpendicular to the substrate;
  • FIG. 5A is a diagram showing a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present disclosure. A cross-sectional view of the method on a C1 plane parallel to the substrate after forming the second trench;
  • FIG5B is a cross-sectional view of the structure shown in FIG5A on a C3 plane perpendicular to the substrate;
  • 6A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after removing the second insulating layer on a C1 plane parallel to the substrate;
  • FIG6B is a cross-sectional view of the structure shown in FIG6A on a C2 plane perpendicular to the substrate;
  • FIG6C is a cross-sectional view of the structure shown in FIG6A on a C3 plane perpendicular to the substrate;
  • FIG. 7 is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after forming a first conductive layer on a C3 plane perpendicular to the substrate;
  • FIG. 8A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after forming a film layer including a first conductive region, a semiconductor region, and a second conductive region on a C1 plane parallel to a substrate;
  • FIG8B is a cross-sectional view of the structure shown in FIG8A on a C2 plane perpendicular to the substrate;
  • FIG8C is a cross-sectional view of the structure shown in FIG8A on a C3 plane perpendicular to the substrate;
  • FIG9B is a cross-sectional view of the structure shown in FIG9A on a C2 plane perpendicular to the substrate;
  • FIG9C is a cross-sectional view of the structure shown in FIG9A on a C3 plane perpendicular to the substrate;
  • 10A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after removing a dummy bit line layer on a C1 plane parallel to a substrate;
  • FIG10B is a cross-sectional view of the structure shown in FIG10A on a C2 plane perpendicular to the substrate;
  • FIG10C is a cross-sectional view of the structure shown in FIG10A on a C3 plane perpendicular to the substrate;
  • 11A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after forming a support layer on a C1 plane parallel to a substrate;
  • FIG11B is a cross-sectional view of the structure shown in FIG11A on a C2 plane perpendicular to the substrate;
  • FIG11C is a cross-sectional view of the structure shown in FIG11A on a C3 plane perpendicular to the substrate;
  • FIG. 12A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after forming a bit line on a C1 plane parallel to a substrate;
  • FIG12B is a cross-sectional view of the structure shown in FIG12A on a C2 plane perpendicular to the substrate;
  • FIG12C is a cross-sectional view of the structure shown in FIG12A on a C3 plane perpendicular to the substrate;
  • FIG. 13A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after forming an insulating layer on a C1 plane parallel to a substrate;
  • FIG13B is a cross-sectional view of the structure shown in FIG13A on a C2 plane perpendicular to the substrate;
  • FIG13C is a cross-sectional view of the structure shown in FIG13A on a C3 plane perpendicular to the substrate;
  • FIG. 14 is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after forming a semiconductor pillar on a C1 plane parallel to a substrate;
  • 15A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after forming a third initial trench on a C1 plane parallel to the substrate;
  • FIG15B is a cross-sectional view of the structure shown in FIG15A on a C2 plane perpendicular to the substrate;
  • FIG15C is a cross-sectional view of the structure shown in FIG15A on a C3 plane perpendicular to the substrate;
  • 16A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after removing the third mask on a C1 plane parallel to the substrate;
  • FIG16B is a cross-sectional view of the structure shown in FIG16A on a C2 plane perpendicular to the substrate;
  • FIG16C is a cross-sectional view of the structure shown in FIG16A on a C3 plane perpendicular to the substrate;
  • 17A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after forming a capacitor on a C1 plane parallel to a substrate;
  • FIG17B is a cross-sectional view of the structure shown in FIG17A on a C2 plane perpendicular to the substrate;
  • FIG17C is a cross-sectional view of the structure shown in FIG17A on a C3 plane perpendicular to the substrate;
  • 18A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after forming a gate groove on a C1 plane parallel to the substrate;
  • FIG18B is a cross-sectional view of the structure shown in FIG18A on a C2 plane perpendicular to the substrate;
  • FIG18C is a cross-sectional view of the structure shown in FIG18A on a C3 plane perpendicular to the substrate;
  • 19A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure, when a gate electrode layer is formed but a gate electrode is not formed, on a C1 plane parallel to a substrate;
  • FIG19B is a cross-sectional view of the structure shown in FIG19A on a C2 plane perpendicular to the substrate;
  • FIG19C is a cross-sectional view of the structure shown in FIG19A on a C3 plane perpendicular to the substrate;
  • 20A is a cross-sectional view of a device manufactured by a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure on a C1 plane parallel to a substrate;
  • FIG20B is a cross-sectional view of the structure shown in FIG20A on a C2 plane perpendicular to the substrate;
  • FIG20C is a cross-sectional view of the structure shown in FIG20A on a C3 plane perpendicular to the substrate;
  • FIG. 20D is a partial enlarged view of the structure shown in FIG. 20A .
  • ordinal numbers such as “first” and “second” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • a channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in the present disclosure, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection includes the situation where components are connected together through an element having some kind of electrical function.
  • element having some kind of electrical function there is no particular limitation on the "element having some kind of electrical function” as long as it can transmit and receive electrical signals between connected components.
  • Examples of “element having some kind of electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°.
  • perpendicular means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced with “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • a and B are located in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process.
  • a and B are an integrated structure
  • a film layer patterned to form a connection is an integrated structure.
  • a and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.
  • the currently known 3D dynamic random access memory (DRAM) with a single crystal silicon channel uses an epitaxial process to alternately grow a single crystal silicon channel layer and a SiGe sacrificial layer to form a stacked structure, and then selectively etches away the SiGe sacrificial layer, and processes the single crystal silicon channel layer to form a 1T1C DRAM storage unit.
  • the stress caused by the Si/SiGe lattice mismatch will be released after the Si/SiGe multi-layer stacking, resulting in an increase in single crystal silicon channel defects, causing device degradation, and seriously affecting the performance of DRAM.
  • FIG. 1 is a process flow chart of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure.
  • the method for manufacturing the 3D stacked semiconductor device includes:
  • Each of the film layers is etched longitudinally (i.e., perpendicular to the substrate) to form a plurality of A plurality of columns extending in a second direction and spaced apart in the first direction, each of the columns comprising a first conductive region, a semiconductor region, and a second conductive region; a surrounding gate insulating layer and a gate electrode are formed on the sidewalls of the semiconductor region of the column, and a word line is formed extending in a direction perpendicular to the substrate.
  • the manufacturing method of the 3D stacked semiconductor device of the embodiment of the present disclosure forms a transistor by first forming a virtual bit line layer extending toward the substrate, then forming a film layer including a first conductive region, a semiconductor region, and a second conductive region on the side wall of the virtual bit line layer, and then spacing the film layer into a plurality of pillars used as the source, drain, and channel of the transistor. Therefore, there is no need to form a sacrificial layer such as SiGe by epitaxial formation in the entire manufacturing process, and the channel of the transistor will not have defects caused by Si/SiGe lattice mismatch. Therefore, the reliability of the manufactured 3D stacked semiconductor device is high, and the storage unit composed of transistors and capacitors can theoretically be infinitely stacked in a direction perpendicular to the substrate, which can greatly improve the integration of the 3D device.
  • the doping elements in the source electrode or drain electrode of the transistor formed by the epitaxial Si/SiGe stacking method are unevenly distributed, for example, they are Gaussian distributed, while the doping concentration of the doping elements in the source electrode or drain electrode obtained by the manufacturing method of the 3D stacked semiconductor device of the embodiment of the present disclosure can be the same in each region of the source electrode or drain electrode, thereby achieving uniform distribution of the doping elements in the source electrode or drain electrode.
  • the substrate is a single crystal substrate
  • the dummy bit line layer is a single crystal film layer
  • the dummy bit line layer is made of the same material as the substrate
  • the etching in the stacked structure to form a plurality of first trenches extending toward the substrate may include:
  • Etching all the first insulating layers and the second insulating layers in the stacked structure that is, etching each first insulating layer and each second insulating layer) so that the first groove exposes the substrate;
  • the forming of a dummy bit line layer filling the first trench in the first trench may include:
  • the dummy bit line layer extending into the first trench and filling the first trench is grown on the exposed substrate by a selective epitaxial process.
  • the film layer is a single crystal film layer, and the film layer and the dummy bit line layer are made of the same material;
  • the forming of a film layer filled between adjacent first insulating layers on the exposed sidewalls of the dummy bit line layer comprises:
  • dummy bit line layer as a seed layer, and using a selective epitaxial process to grow a first conductive layer extending along the first direction and the second direction on the exposed sidewalls of the dummy bit line layer;
  • a second conductive layer extending along the first direction and the second direction is grown at one end of the semiconductor layer away from the virtual bit line layer by a selective epitaxial process, the first conductive layer forms the first conductive region of the film layer, the semiconductor layer forms the semiconductor region of the film layer, and the second conductive layer forms the second conductive region of the film layer.
  • the first conductive layer may contain a first doping material
  • the second conductive layer may contain a second doping material
  • the first doping material is uniformly distributed in various regions of the first conductive layer
  • the second doping material is uniformly distributed in various regions of the second conductive layer.
  • the doping material is uniformly distributed in various regions of the film layer.
  • the doping concentration of the doping material in various regions of the film layer is the same (including completely the same and substantially the same).
  • the first doping material and the second doping material may be the same or different.
  • the doping concentration of the first doping material in the first conductive layer is a first doping concentration
  • the doping concentration of the second doping material in the second conductive layer is a second doping concentration.
  • the first doping concentration and the second doping concentration may be the same (including completely the same and approximately the same) or different.
  • the manufacturing method of the 3D stacked semiconductor device can first expose the single crystal substrate by grooving in the stacked structure, then grow a single crystal virtual bit line layer on the exposed substrate by a selective epitaxial process, and then selectively hollow out the second insulating layer in the stacked structure to form a channel for the subsequent selective growth of a single crystal film layer, and expose part of the side wall of the single crystal virtual bit line layer, and then use the exposed side wall of the single crystal virtual bit line layer as a seed layer to selectively epitaxially grow a single crystal film layer for forming a source, drain and channel in the channel.
  • the 3D semiconductor device of the present disclosure is preferably fabricated by a method of making grooves in the stacked structure, and then selectively growing a single crystal film layer for forming a source, drain and channel by a selective epitaxial process.
  • the manufacturing method of stacked semiconductor devices can avoid the problem of being limited by the number of Si/SiGe superlattice epitaxial layers when the traditional method forms a single-crystal silicon channel through Si/SiGe superlattice epitaxy, thereby breaking through the limitation on the number of stacked layers of memory cells, so that in theory the memory cells can be infinitely stacked in the direction perpendicular to the substrate and the reliability of device performance is guaranteed.
  • the virtual bit line layer can also serve as a dummy BL to occupy the space for subsequently forming the bit line.
  • the bit line can be formed after the virtual bit line layer is removed to free up the space.
  • a main body material of the first conductive layer may be single crystal silicon; a main body material of the second conductive layer may be single crystal silicon.
  • the step of growing a first conductive layer extending along the first direction and the second direction on the exposed sidewall of the dummy bit line layer using a selective epitaxial process may include:
  • Single crystal silicon is grown on the exposed sidewalls of the dummy bit line layer by adopting a selective epitaxial process, and an in-situ doping method is adopted during the growth of the single crystal silicon to obtain the first conductive layer formed of first doped single crystal silicon.
  • the step of growing a semiconductor layer along the first direction and the second direction at an end of the first conductive layer away from the dummy bit line layer using a selective epitaxial process includes:
  • a selective epitaxial process is adopted to grow intrinsic single crystal silicon at one end of the first conductive layer away from the dummy bit line layer, so as to obtain the semiconductor layer formed of intrinsic single crystal silicon.
  • the step of growing a second conductive layer extending along the first direction and the second direction at an end of the semiconductor layer away from the dummy bit line layer by using a selective epitaxial process comprises:
  • a selective epitaxial process is used to grow single crystal silicon at one end of the semiconductor layer away from the dummy bit line layer, and an in-situ doping method is used to dope the single crystal silicon during its growth to obtain the second conductive layer formed of second doped single crystal silicon.
  • the longitudinally etching each of the film layers to form a plurality of pillars extending along the second direction and spaced apart in the first direction may include:
  • Each of the film layers is etched longitudinally to form a A plurality of third grooves are spaced apart along the first direction, wherein the third grooves space the film layer into a plurality of the pillars.
  • the method for manufacturing the 3D stacked semiconductor device may further include, after forming a film layer filled between adjacent first insulating layers and before spacing the film layer into a plurality of the pillars, performing the following steps:
  • the dummy bit line layer in the first trench is removed by etching, so that the first trench exposes the film layer and the first insulating layer.
  • the method for manufacturing the 3D stacked semiconductor device may further include, after the film layer is spaced into a plurality of the pillars, performing the following steps:
  • a dielectric layer and a fourth electrode are sequentially deposited on the exposed surface of the third electrode, and the third electrode, the dielectric layer and the fourth electrode constitute a capacitor.
  • the forming of the third electrode of the capacitor in contact with the end of the film layer away from the dummy bit line layer may include:
  • a third conductive layer covering the end of the film layer exposed by the second groove is deposited on the substrate using polysilicon or metal to form a third electrode.
  • the forming of the third electrode of the capacitor in contact with the end of the film layer away from the dummy bit line layer may include:
  • a selective epitaxial process is used to grow single crystal silicon at the end of the film layer exposed by the second groove, and an in-situ doping method is used during the growth of the single crystal silicon to obtain a third conductive layer formed by doped single crystal silicon to form a third electrode.
  • forming a surrounding gate insulating layer and a gate electrode on a sidewall of the semiconductor region of the pillar may include:
  • a portion of the gate electrode layer between two adjacent semiconductor pillars distributed along the first direction is removed by etching, and only the gate electrode layer on the side walls of the two semiconductor pillars is retained to obtain a gate electrode.
  • the method for manufacturing the 3D stacked semiconductor device may further include, after removing the dummy bit line layer in the first trench and before forming the third trench, performing the following steps:
  • the first conductive regions of the film layer on both sides of the first trench are etched back to form a bit line groove extending into the first conductive region of the film layer and extending along the first direction, and a bit line is deposited in the bit line groove.
  • the method for manufacturing the 3D stacked semiconductor device may further include, after removing the dummy bit line layer in the first trench and before forming the bit line trench, performing the following steps:
  • the first insulating layer on both sides of the first trench is etched back to form a supporting groove extending into the first insulating layer and extending along the first direction, and a second insulating layer is deposited in the supporting groove to form a supporting layer.
  • the method for manufacturing the 3D stacked semiconductor device may further include, after forming the bit line and before forming the third trench, performing the following steps:
  • a third insulating layer is deposited in the first trench, wherein the third insulating layer separates two adjacent bit lines located in the same first trench.
  • the substrate may be a single crystal substrate, for example, a substrate formed of single crystal silicon, single crystal germanium, single crystal silicon carbide, or single crystal gallium arsenide.
  • the following is a further explanation of the technical solution of the disclosed embodiment through the manufacturing process of a 3D stacked semiconductor device of an exemplary embodiment.
  • the "photolithography/photolithography process” mentioned in this embodiment includes coating film layer, mask exposure and development, which is a mature preparation process in the relevant technology.
  • Deposition can be carried out by known processes such as sputtering, evaporation, chemical vapor deposition, etc.
  • coating can be carried out by known coating processes
  • etching can be carried out by known etching processes.
  • the known methods are not specifically limited here.
  • FIG2A is a schematic diagram of the three-dimensional structure of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after forming a stacked structure
  • FIG2B is a cross-sectional view of the structure shown in FIG2A on a C1 plane parallel to the substrate
  • FIG2C is a cross-sectional view of the structure shown in FIG2A on a C2 plane perpendicular to the substrate
  • FIG2D is a cross-sectional view of the structure shown in FIG2A on a C3 plane perpendicular to the substrate
  • FIG3A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure on a C1 plane parallel to the substrate after forming a first groove
  • FIG3B is a cross-sectional view of the structure shown in FIG3A on a C3 plane perpendicular to the substrate
  • FIG4A is a cross-sectional view of a method for manufacturing a
  • FIG. 4B is a cross-sectional view of the structure shown in FIG. 4A on a C3 plane perpendicular to the substrate;
  • FIG. 5A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure on a C1 plane parallel to the substrate after forming a second trench;
  • FIG. 5B is a cross-sectional view of the structure shown in FIG. 5A on a C3 plane perpendicular to the substrate;
  • FIG. 6A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure on a C1 plane parallel to the substrate after removing the second insulating layer;
  • FIG. 5A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure on a C1 plane parallel to the substrate after removing the second insulating layer;
  • FIG. 5A is a cross
  • FIG. 6B is a cross-sectional view of the structure shown in FIG. 6A on a C2 plane perpendicular to the substrate
  • FIG. 6C is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure on a C1 plane parallel to the substrate
  • FIG. 6A is a cross-sectional view of the structure shown in FIG. 6A on a C3 plane perpendicular to the substrate
  • FIG. 7 is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure on a C3 plane perpendicular to the substrate after forming a first conductive layer
  • FIG. 8A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure on a C1 plane parallel to the substrate after forming a film layer including a first conductive region, a semiconductor region, and a second conductive region;
  • FIG. 8B is a cross-sectional view of the structure shown in FIG. 8A on a C2 plane perpendicular to the substrate;
  • FIG. 8C is a cross-sectional view of the structure shown in FIG. 8A on a C3 plane perpendicular to the substrate;
  • FIG. 9A is a cross-sectional view of a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure
  • FIG. 9B is a cross-sectional view of the structure shown in FIG.
  • FIG. 9A on a C2 plane perpendicular to the substrate
  • FIG. 9C is a cross-sectional view of the structure shown in FIG. 9A on a C3 plane perpendicular to the substrate
  • FIG. 10A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure on a C1 plane parallel to the substrate after removing the dummy bit line layer
  • FIG. 10B is a cross-sectional view of the structure shown in FIG. 10A on a C2 plane perpendicular to the substrate
  • FIG. 10C is a cross-sectional view of the structure shown in FIG. 10A on a C3 plane perpendicular to the substrate
  • FIG. 10A is a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure on a C1 plane parallel to the substrate after removing the dummy bit line layer
  • FIG. 10B is a cross-sectional view of the structure shown in FIG.
  • FIG 11A is a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure after forming a third electrode
  • FIG11B is a cross-sectional view of the structure shown in FIG11A on a C2 plane perpendicular to the substrate
  • FIG11C is a cross-sectional view of the structure shown in FIG11A on a C3 plane perpendicular to the substrate
  • FIG12A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an exemplary embodiment of the present disclosure on a C1 plane parallel to the substrate after forming a bit line
  • FIG12B is a cross-sectional view of the structure shown in FIG12A on a C2 plane perpendicular to the substrate
  • FIG12C is a cross-sectional view of the structure shown in FIG12A on a C3 plane perpendicular to the substrate
  • FIG13A is a cross-sectional view of a method for manufacturing a 3D stacked semiconductor device provided by an
  • the method for manufacturing the 3D stacked semiconductor device may include:
  • S10 Provide a substrate 1, such as a single crystal silicon substrate, and alternately deposit a first insulating layer 11 and a second insulating layer 12 on the substrate 1 to obtain a stacked structure consisting of a plurality of first insulating layers 11 and a plurality of second insulating layers 12; deposit a first mask plate 21 on the top surface of the stacked structure, as shown in Figures 2A, 2B, 2C and 2D.
  • a substrate 1 such as a single crystal silicon substrate, and alternately deposit a first insulating layer 11 and a second insulating layer 12 on the substrate 1 to obtain a stacked structure consisting of a plurality of first insulating layers 11 and a plurality of second insulating layers 12; deposit a first mask plate 21 on the top surface of the stacked structure, as shown in Figures 2A, 2B, 2C and 2D.
  • Figure 2B is a cross-sectional view on the C1 plane parallel to the substrate, and the C1 plane passes through the second insulating layer 12;
  • Figure 2C is a cross-sectional view on the C2 plane perpendicular to the substrate, and
  • Figure 2D is a cross-sectional view on the C3 plane perpendicular to the substrate, and the C3 plane is perpendicular to the C2 plane;
  • the positions of the C1 plane, C2 plane and C3 plane can be as shown in Figure 2A, and the C1 plane, C2 plane and C3 plane in the following text have the same direction as the C1 plane, C2 plane and C3 plane in Figure 2A, but the interception position may be different.
  • the materials of the first insulating layer and the second insulating layer can be independently selected from any one or more of silicon oxide (for example, SiO2 ), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN), and the materials of the first insulating layer and the second insulating layer are different, so that when the second insulating layer is subsequently etched to remove, the first insulating layer and the second insulating layer can have different etching rates, thereby removing the second insulating layer and retaining the first insulating layer.
  • silicon oxide for example, SiO2
  • SiON silicon oxynitride
  • SiN silicon nitride
  • SiCN silicon carbonitride
  • the stacked structure shown in FIG. 2A includes six first insulating layers 11 and five second insulating layers 12 , which is only an example. In other embodiments, the stacked structure may include more or fewer first insulating layers 11 and second insulating layers 12 that are alternately arranged.
  • the first mask plate can be used as a hard mask (HM) when the stacked structure is subsequently etched.
  • the thickness of the first mask plate can be 50nm.
  • FIG. 3A is a cross-sectional view on a C1 plane parallel to the substrate, and the C1 plane passes through the second insulating layer 12;
  • FIG. 3B is a cross-sectional view on a C3 plane perpendicular to the substrate; and the cross-sectional view on a C2 plane that does not pass through the first trench 31 is the same as FIG. 2C.
  • the first direction may be the X direction as shown in FIG. 3A.
  • S23 Anisotropically etching the stacked structure to make the initial first trench extend toward the substrate 1, thereby forming a plurality of first trenches 31 extending toward the substrate 1 and along the first direction in the stacked structure, wherein the plurality of first trenches 31 are spaced apart along a second direction, and the first trenches 31 expose the substrate 1.
  • the second direction may be the Y direction as shown in FIG3A .
  • first direction and the second direction may be perpendicular to each other.
  • the anisotropic etching in step S23 may be dry etching.
  • the first trench 31 may be perpendicular to the substrate 1 .
  • step S30 may include: selectively epitaxially growing a virtual bit line layer 41 in the first trench 31, and making the virtual bit line layer 41 fill the first trench 31, as shown in Figures 4A and 4B, the material of the virtual bit line layer 41 may be single crystal silicon; here, Figure 4A is a cross-sectional view on the C1 plane parallel to the substrate, and the C1 plane passes through the second insulating layer 12; Figure 4B is a cross-sectional view on the C3 plane perpendicular to the substrate; the cross-sectional view on the C2 plane that does not pass through the first trench 31 is the same as Figure 2C.
  • FIGS. 5A and 5B etching the stacked structure to form a second trench 32 extending toward the substrate 1 between two adjacent dummy bit line layers 41, and the second trench 32 extends along the first direction, as shown in FIGS. 5A and 5B ;
  • FIG. 5A is a cross-sectional view on a C1 plane parallel to the substrate, and the C1 plane passes through the second insulating layer 12;
  • FIG. 5B is a cross-sectional view on a C3 plane perpendicular to the substrate;
  • the cross-sectional view on the C2 plane that does not pass through the first trench 31 and the second trench 32 is the same as that of Fig. 2C.
  • the second trench 32 may be formed with reference to steps S21 to S23.
  • the second trench 32 may be perpendicular to the substrate 1 ; the second trench 32 and the first trench 31 may be parallel to each other.
  • the second insulating layer 12 is removed by an isotropic etching method to expose part of the side wall of the virtual bit line layer 41 located between adjacent first insulating layers in the second groove 32, and the exposed side wall extends along the first direction, as shown in Figures 6A, 6B and 6C;
  • Figure 6A is a cross-sectional view on the C1 plane parallel to the substrate, and the C1 plane passes through the first insulating layer 11;
  • Figure 6B is a cross-sectional view on the C2 plane perpendicular to the substrate, and the C2 plane is located between the first groove 31 and the second groove 32;
  • Figure 6C is a cross-sectional view on the C3 plane perpendicular to the substrate.
  • a film layer 50 is formed on the exposed side wall of the virtual bit line layer 41 to fill in between adjacent first insulating layers, wherein the film layer 50 extends along the first direction and the second direction, and the film layer 50 includes a first conductive region, a semiconductor region, and a second conductive region in sequence along the direction away from the virtual bit line layer 41 in the second direction, and the second groove 32 exposes the end face of the film layer 50 away from one end of the virtual bit line layer 41 (i.e., the second conductive region), and multiple film layers 50 and multiple first insulating layers 11 are staggered and stacked to form a stacked structure.
  • step S60 may include:
  • FIG7 is a cross-sectional view on a C3 plane perpendicular to the substrate; the cross-sectional view on a C1 plane passing through the first insulating layer 11 is the same as FIG6A, and the cross-sectional view on a C2 plane located between the first trench 31 and the second trench 32 is the same as FIG6B;
  • a semiconductor layer 52 and a second conductive layer 53 are sequentially formed at one end of the first conductive layer 51 away from the virtual bit line layer 41, the semiconductor layer 52 forms the semiconductor region of the film layer 50, the second conductive layer 53 forms the second conductive region of the film layer 50, the first conductive layer 51, the semiconductor layer 52 and the second conductive layer 53 constitute the film layer 50, the second groove 32 exposes the end surface of the second conductive layer 53, and a plurality of film layers 50 and a plurality of first insulating layers 11 are alternately stacked to form a stacked structure, as shown in FIGS. 8A, 8B and 8C; here, FIG.
  • FIG. 8A is a cross-sectional view on a C1 plane parallel to the substrate, and the C1 plane passes through the film layer 50;
  • FIG. 8B is a cross-sectional view on a C2 plane perpendicular to the substrate, and the C2 plane passes through the first trench 31;
  • FIG. 8C is a cross-sectional view on a C3 plane perpendicular to the substrate.
  • a selective epitaxial process may be used to grow the first conductive layer 51 on the exposed sidewall of the virtual bit line layer 41.
  • the material of the first conductive layer 51 may be single crystal silicon containing a first doping material, and may be formed by an in-situ doping method, that is, a doping gas containing the first doping material is introduced during the growth of the single crystal silicon.
  • the in-situ doping method is used to form the first conductive layer 51 so that the first doping material is evenly distributed in various regions of the first conductive layer 51, and the first doping material will not diffuse into the virtual bit line layer 41.
  • the first doping material in the first conductive layer 51 may be arsenic (As), and the doping concentration may be 1e19.
  • the material of the semiconductor layer 52 may be intrinsic single crystal silicon, and the semiconductor layer 52 may be formed by a selective epitaxial process.
  • the material of the second conductive layer 53 may be single crystal silicon containing a second doping material.
  • the second doping material may be doped during the growth of the single crystal silicon using a selective epitaxial process and an in-situ doping method to form the second conductive layer 53.
  • the second doping material in the second conductive layer 53 may be arsenic (As), and the doping concentration may be 1e19.
  • the length L1 of the film layer 50 in the second direction may be smaller than the length L2 of the first insulating layer 11 in the second direction, so that there is a gap between two adjacent first insulating layers 11 in a direction perpendicular to the substrate 1.
  • S70 depositing a third conductive layer on the substrate 1 to obtain a third electrode 61 covering the exposed end of the film layer 50 (i.e., the second conductive region of the film layer 50 ); depositing a first insulating layer 11 on the substrate 1 to cover the third electrode 61 and the second groove 32 .
  • step S70 may include:
  • S72 Anisotropically etch the third conductive layer to remove the third conductive layer on the side wall of the first insulating layer 11, and to separate the third conductive layer between two adjacent first insulating layers 11. The two ends are flush with the two ends of the first insulating layer 11, and the remaining third conductive layer forms a third electrode 61, which covers the end surface of the film layer 50 away from the end of the dummy bit line layer 41 and exposes the end surface of the first insulating layer 11;
  • FIGS. 9A, 9B and 9C depositing a first insulating layer 11 on the substrate 1 so that the first insulating layer 11 covers the third electrode 61 and the second groove 32, and planarizing the first insulating layer 11 on the surface of the substrate 1 by chemical mechanical polishing (CMP) and removing the remaining first mask plate 21, as shown in FIGS. 9A, 9B and 9C;
  • CMP chemical mechanical polishing
  • FIG. 9A is a cross-sectional view on a C1 plane parallel to the substrate, and the C1 plane passes through the film layer 50
  • FIG. 9B is a cross-sectional view on a C2 plane perpendicular to the substrate, and the C2 plane is located between the first groove 31 and the second groove 32
  • FIG. 9C is a cross-sectional view on a C3 plane perpendicular to the substrate.
  • the material of the third conductive layer may be polysilicon, heavily doped single crystal silicon, conductive metal, etc.
  • the material of the third conductive layer is heavily doped single crystal silicon, and the third conductive layer may be formed by a selective epitaxial process and an in-situ doping method.
  • step S80 may include:
  • S81 depositing a second mask plate 22 on the top surface of the stacked structure, and forming a second photoresist pattern on the top surface of the second mask plate 22 by photolithography, wherein the second photoresist pattern exposes a partial area of the second mask plate 22;
  • FIG. 10A is a cross-sectional view on a C1 plane parallel to the substrate, and the C1 plane passes through the film layer 50;
  • FIG. 10B is a cross-sectional view on a C2 plane perpendicular to the substrate
  • FIG. 10C is a cross-sectional view on a C2 plane which is perpendicular to the substrate, and the C2 plane is located between the first trench 31 and the second trench 32
  • FIG. 10C is a cross-sectional view on a C3 plane which is perpendicular to the substrate.
  • step S90 may include: depositing a second insulating layer 12 covering the supporting groove, the first groove 31 and the second mask plate 22 on the substrate 1, removing the second insulating layer 12 in the first groove 31 by anisotropic etching, and the second insulating layer 12 in the supporting groove forms a supporting layer 70.
  • FIG. 12A is a cross-sectional view on a C1 plane parallel to the substrate, and the C1 plane passes through the bit line 40
  • Figure 12B is a cross-sectional view on a C2 plane perpendicular to the substrate, and the C2 plane passes through the bit line 40
  • Figure 12C is a cross-sectional view on a C3 plane perpendicular to the substrate.
  • the fifth conductive layer may be a multilayer structure, for example, may include an anti-oxidation layer and a metal layer.
  • the anti-oxidation layer may prevent the metal in the metal layer from being oxidized, and may be formed of titanium nitride (TiN) or the like.
  • the metal layer may be formed of a metal such as tungsten (W).
  • step S100 may include:
  • S101 using an isotropic etching method, laterally etching the film layer 50 on both sides in the first trench 31 to form a bit line trench extending into the first conductive layer 51 of the film layer 50 and extending along the first direction;
  • S102 depositing an anti-oxidation layer of the second insulating layer 12 covering the inner wall of the bit line groove, the inner wall of the first trench 31 and the top surface of the substrate 1 on the substrate 1, and depositing a metal layer filling the bit line groove and the first trench 31 and covering the anti-oxidation layer on the substrate 1, wherein the anti-oxidation layer and the metal layer constitute a fifth conductive layer;
  • S103 using an isotropic etching method to remove the fifth conductive layer in the first trench 31, wherein the fifth conductive layer in the bit line trench forms a bit line 40, and the bit line 40 is distributed on both sides of the first trench 31 and extends along the first direction.
  • FIGS. 13A , 13B and 13C A third insulating layer 82 covering the first trench 31 is deposited on the substrate 1, and the third insulating layer is planarized by a CMP process, wherein the third insulating layer 82 separates two adjacent bit lines 40 located in the same first trench 31, as shown in FIGS. 13A , 13B and 13C;
  • FIG. 13A is a cross-sectional view on a C1 plane parallel to the substrate, and the C1 plane passes through the film layer 50
  • FIG. 13B is a cross-sectional view on a C2 plane perpendicular to the substrate, and the C2 plane passes through the bit line 40
  • FIG. 13C is a cross-sectional view on a C3 plane perpendicular to the substrate.
  • the third insulating layer and the second insulating layer may be made of the same material, for example, both may be silicon nitride (SiN).
  • step S120 may refer to steps S21 to S23 to form a plurality of third grooves 33 by depositing a mask plate, photolithography and etching the mask plate, removing the photoresist on the mask plate, and anisotropically etching the stacked structure.
  • two pillars 54 are distributed along the second direction between two adjacent first trenches 31 and are separated by the first insulating layer 11 in the second trench 32.
  • a plurality of pillars distributed along the first direction and located in the same layer are connected to a bit line 40.
  • the third trench 33 may be perpendicular to the substrate 1 .
  • step S140 may include:
  • FIG. 15A is a cross-sectional view on a C1 plane parallel to the substrate, and the C1 plane passes through the column 54;
  • FIG. 15B is a cross-sectional view on a C2 plane perpendicular to the substrate, and the C2 plane passes through the column 54;
  • FIG. 15C is a cross-sectional view on a C3 plane perpendicular to the substrate;
  • S142 etching the first insulating layer 11 between two adjacent first trenches 31 by anisotropic etching, so that the third initial trench extends toward the substrate 1 to form a fourth trench 34 extending along the first direction; illustratively, the fourth trench 34 can be formed at the position of the second trench 32 and the two have the same size;
  • the first insulating layer 11 is isotropically etched in the fourth groove 34 to remove the first insulating layer 11 covering the third electrode 61 to expose the third electrode 61, but retain the first insulating layer 11 on the side wall of the third insulating layer 82, and remove the third mask plate 23, as shown in Figures 16A, 16B and 16C;
  • Figure 16A is a cross-sectional view on the C1 plane parallel to the substrate, and the C1 plane passes through the column 54
  • Figure 16B is a cross-sectional view on the C2 plane perpendicular to the substrate, and the C2 plane passes through the column 54
  • Figure 16C is a cross-sectional view on the C3 plane perpendicular to the substrate.
  • FIGS. 17A , 17B and 17C A dielectric layer and a fourth conductive layer are sequentially deposited on the surface of the exposed third electrode 61 to form a dielectric layer 62 and a fourth electrode 63 respectively.
  • the third electrode 61, the dielectric layer 62 and the fourth electrode 63 constitute a capacitor, as shown in FIGS. 17A , 17B and 17C ; here, FIG. 17A is a cross-sectional view on a C1 plane parallel to the substrate, and the C1 plane passes through the column 54; FIG. 17B is a cross-sectional view on a C2 plane perpendicular to the substrate, and the C2 plane passes through the column 54; and FIG. 17C is a cross-sectional view on a C3 plane perpendicular to the substrate.
  • the dielectric layer may be made of a High-K dielectric material. Formation, that is, a dielectric material with a dielectric constant K ⁇ 3.9.
  • the High-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide (Al 2 O 3 ), hafnium oxide, and the like.
  • the material of the fourth conductive layer includes but is not limited to at least one of the following: polysilicon, tungsten, and titanium nitride.
  • the second insulating layer 12 may be deposited on the sidewall of the fourth trench, or the second insulating layer 12 may not be deposited.
  • TiN or the like may be deposited on the surface of the dielectric layer to form an anti-oxidation layer, so as to prevent the tungsten metal forming the fourth electrode 63 from being oxidized by the oxygen-containing dielectric layer such as silicon oxide.
  • the dielectric layer is a film layer that does not contain oxygen, there is no need to add an anti-oxidation layer.
  • the fourth electrodes 63 on the plurality of pillars 54 located on the same layer and extending into the same fourth trench may be an integrated structure.
  • the fourth electrodes 63 of the plurality of capacitors distributed in a direction perpendicular to the substrate 1 may be an integrated structure.
  • two fourth electrodes 63 on two adjacent pillars 54 extending toward each other along the second direction into the same fourth trench may be shared.
  • the plurality of fourth electrodes 63 located in the fourth trench may be an integrated structure.
  • FIGS 18A, 18B and 18C Etching and removing the first insulating layer 11 on the side wall of the first trench 31 to form a gate groove, as shown in Figures 18A, 18B and 18C;
  • Figure 18A is a cross-sectional view on the C1 plane parallel to the substrate, and the C1 plane passes through the column 54;
  • Figure 18B is a cross-sectional view on the C2 plane perpendicular to the substrate, and the C2 plane passes through the groove formed after removing the first insulating layer 11;
  • Figure 18C is a cross-sectional view on the C3 plane perpendicular to the substrate.
  • FIGS. 19A , 19B and 19C depositing a gate insulating layer 90 on the inner wall of the gate groove, and filling a gate electrode layer 101 in the gate groove, as shown in FIGS. 19A , 19B and 19C ;
  • FIG. 19A is a cross-sectional view on a C1 plane parallel to the substrate, and the C1 plane passes through the pillar 54;
  • FIG. 19B is a cross-sectional view on a C2 plane perpendicular to the substrate, and the C2 plane passes through the gate electrode layer 91;
  • FIG. 19C is a cross-sectional view on a C2 plane perpendicular to the substrate, and the C2 plane passes through the gate electrode layer 91;
  • FIG20A is a cross-sectional view on a C1 plane parallel to the substrate, and the C1 plane passes through the pillars 54
  • FIG20B is a cross-sectional view on a C2 plane perpendicular to the substrate, and the C2 plane passes through the gate electrode 100
  • FIG20C is a cross-sectional view on a C3 plane perpendicular to the substrate.
  • a portion of the gate electrode layer between two adjacent pillars 54 distributed along the first direction may be removed by depositing a mask, photolithography, and etching.
  • the gate insulating layer may be a High-K dielectric material, that is, a dielectric material with a dielectric constant K ⁇ 3.9.
  • the High-K dielectric material may include but is not limited to at least one of the following: silicon oxide, aluminum oxide (Al 2 O 3 ), and hafnium oxide.
  • the gate insulating layer may be deposited by ALD.
  • the gate electrode layer may be formed of or include a conductive material, and the conductive material may be, for example, one of a doped semiconductor material, a conductive metal nitride, a metal material, and a metal-semiconductor compound, such as W, etc.; illustratively, the gate electrode layer may include but is not limited to at least one of the following: indium tin oxide (ITO), a composite film layer of TiN and W, aluminum doped zinc oxide (AZO), and indium zinc oxide (IZO).
  • ITO indium tin oxide
  • AZO aluminum doped zinc oxide
  • IZO indium zinc oxide
  • the gate electrodes 100 of a column of transistors distributed along a direction perpendicular to the substrate 1 can be connected to the same word line 110, or the gate electrodes 100 of a column of transistors distributed along a direction perpendicular to the substrate 1 are connected together to form a word line 110.
  • the embodiments of the present disclosure further provide a 3D stacked semiconductor device, which can be manufactured by the method for manufacturing the 3D stacked semiconductor device provided by the embodiments of the present disclosure as above.
  • the 3D stacked semiconductor device provided by the embodiment of the present disclosure includes:
  • Each of the memory cells 120 includes a transistor; the transistor includes a column 54 extending along the second direction and a gate electrode 100 surrounding the sidewall of the column 54, and the column 54 includes a first conductive region 55, a semiconductor region 57 and a second conductive region 56 in sequence;
  • the storage unit is a 1T1C structure, and the storage unit further includes a capacitor, one of the electrodes of the capacitor is connected to one end of the pillar 54;
  • the memory cell is a 2T0C structure or a 1T capacitor-free structure, and the memory cell does not include a capacitor for storing capacitance.
  • the semiconductor region 57 includes the main material of the column 54, the first conductive region 55 includes the first doping material, and the second conductive region 56 includes the second doping material.
  • the first doping material is uniformly distributed in various regions of the first conductive region 55, and the second doping material is uniformly distributed in various regions of the second conductive region 56.
  • the first direction may be the X direction as shown in FIG. 20A
  • the second direction may be the Y direction as shown in FIG. 20A
  • the first direction and the second direction may be perpendicular to each other.
  • the 3D stacked semiconductor device of the embodiment of the present disclosure does not need to form a transistor channel through epitaxial SiGe and other sacrificial layers, but can adopt the manufacturing method of the 3D stacked semiconductor device provided by the embodiment of the present disclosure as above, using a virtual bit line layer as a seed layer, and forming the channel and source and drain of the transistor by selective epitaxial growth on the seed layer. Therefore, the reliability of the 3D stacked semiconductor device is higher, and the storage unit can theoretically be infinitely stacked in a direction perpendicular to the substrate, which can greatly improve the integration of the 3D device.
  • the gate electrode surrounds the side wall of the semiconductor column, wherein the surround can be understood as the gate electrode partially or completely surrounding the side wall of the semiconductor column.
  • the surround can be that the gate electrode completely surrounds the side wall of the semiconductor column as a whole, that is, the cross section of the gate electrode is a closed ring, as shown in Figures 20A, 20B and 20C.
  • the interception direction of the cross section is intercepted along a direction parallel to the substrate.
  • the surround can be a partial surround, and the cross section after the surround is not closed, but presents a ring shape. For example, a ring with an opening.
  • the host material may be single crystal silicon, single crystal germanium, single crystal silicon carbide or single crystal gallium arsenide.
  • the main material may be single crystal silicon, and the main material does not contain germanium. Therefore, the 3D stacked semiconductor device of the embodiment of the present disclosure may not require an epitaxial Si/SiGe stack when forming a single crystal silicon channel. This can avoid the problem of being limited by the number of Si/SiGe superlattice epitaxial layers when forming a single crystal silicon channel through Si/SiGe superlattice epitaxy in the traditional method, thereby breaking through the limitation on the number of stacked layers of the memory cell, so that in theory the memory cells can be infinitely stacked in a direction perpendicular to the substrate and ensuring the reliability of the device performance.
  • the doping concentration of the first doping material in the first conductive region is a first doping concentration
  • the doping concentration of the second doping material in the second conductive region is a second doping concentration
  • the first doping concentration and the second doping concentration may be the same or different
  • the first doping material and the second doping material may be the same or different.
  • the first doping material and the second doping material may both be arsenic
  • the first doping concentration and the second doping concentration may both be 1e19.
  • the first conductive region may serve as a source electrode, and the second conductive region may serve as a drain electrode; or, the first electrode may serve as a drain electrode, and the second electrode may serve as a source electrode.
  • a channel between the first conductive region and the second conductive region of one of the transistors may be a horizontal channel.
  • a horizontal channel is a channel in which the carrier transmission direction is in a plane parallel to the substrate, but the carrier transmission direction is not limited to one direction.
  • the carrier transmission direction extends in one direction as a whole, but locally, it is related to the shape of the semiconductor layer.
  • a horizontal channel does not mean that it must extend in one direction in a horizontal plane, and may extend in different directions.
  • the carrier transmission direction in a plane parallel to the substrate is also a macroscopic concept, and is not limited to being absolutely parallel to the substrate.
  • the present disclosure protects the channel between the first electrode and the second electrode as a channel that is not perpendicular to the substrate.
  • the 3D stacked semiconductor device may also include: a plurality of bit lines 40 extending along the first direction, the plurality of bit lines 40 are spaced apart in a direction perpendicular to the substrate, and the first conductive region of the column 54 is connected to the bit line 40.
  • transistors of a plurality of memory cells 120 located in the same layer and distributed along the first direction may be connected to the same bit line 40 .
  • the 3D stacked semiconductor device may further include: a plurality of word lines 110 extending in a direction perpendicular to the substrate 1 , the word lines 110 surrounding the sidewalls of the pillars 54 .
  • the gate electrodes 100 of the transistors of a column of memory cells 120 distributed in a direction perpendicular to the substrate 1 are connected to the same word line 110 .
  • the pillars 54 of the transistors of the plurality of memory cells located in the same layer and distributed along the first direction are connected to the same bit line 40, and two adjacent pillars 54 connected to the same bit line 40 are connected via a connecting portion 130, and the pillars 54 and the connecting portion 130 are an integrated structure.
  • one end of each of the pillars 54 connected to the same bit line 40 and the connecting portion 130 form a film layer 50 extending along the first direction, the film layer 50 is connected to the bit line 40, and the orthographic projection of the film layer 50 on the substrate 1 overlaps with the orthographic projection of the bit line 40 on the substrate 1.
  • the outer contours of the cross-section of the word line at different positions in the extending direction of the word line are the same.
  • the 3D stacked semiconductor device may further include: a plurality of support layers 70 extending along the first direction, the support layer 70 being disposed between two adjacent bit lines 40 distributed along a direction perpendicular to the substrate 1, and separating the bit lines 40 from the word lines 110. Separating the bit lines 40 from the word lines 110 by the support layer 70 may prevent formation of parasitic capacitors between the bit lines 40 and the word lines 110.
  • the capacitor may include a third electrode 61 , a fourth electrode 63 , and a dielectric layer 62 disposed between the third electrode 61 and the fourth electrode 63 , and the third electrode 61 is connected to the second conductive region of the pillar 54 .
  • the fourth electrodes of the capacitors of the two columns of memory cells distributed in a direction perpendicular to the substrate and spaced apart in the second direction are common electrodes, and the transistors and capacitors of the two columns of memory cells are distributed in a mirror image.
  • the fourth electrodes 63 of the capacitors of a column of memory cells 120 distributed in a direction perpendicular to the substrate 1 may be an integrated structure.
  • the fourth electrodes 63 of the capacitors of a column of memory cells 120 located in the same layer and distributed along the first direction may be an integrated structure.
  • the fourth electrodes 63 of the capacitors of at least two adjacent memory cells 120 located in the same layer and distributed along the second direction may be an integrated structure.
  • the third electrode is formed on the second conductive region of the column using an epitaxial process, the material of the third electrode is single crystal silicon, and the third electrode has the same cross-section as the first conductive region, the second conductive region, and the semiconductor region of the column.
  • the 3D stacked semiconductor device may be a 3D memory, for example, a 3D DRAM or other memory.
  • the 3D memory may be a 1T1C structure.
  • An embodiment of the present disclosure further provides an electronic device, which includes the 3D stacked semiconductor device provided by the above embodiment of the present disclosure.
  • the electronic device may be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc.
  • the storage device may include a memory in a computer, etc., which is not limited here.

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Abstract

一种3D堆叠的半导体器件及其制造方法、电子设备，3D堆叠的半导体器件包括：分布于不同层、沿着垂直于衬底(1)的方向堆叠且周期性分布的多个存储单元(120)，每一层包括沿第一方向和第二方向阵列分布的多个存储单元(120)；每个存储单元(120)包括一个晶体管和一个电容器；晶体管包括沿第二方向延伸的柱(54)和环绕柱(54)侧壁的栅电极(100)，柱(54)包括第一导电区域(55)、半导体区域(57)和第二导电区域(56)；半导体区域(57)包含柱(54)的主体材料，第一导电区域(55)和第二导电区域(56)分别包含第一掺杂材料和第二掺杂材料；第一掺杂材料在第一导电区域(55)中均匀分布，第二掺杂材料在第二导电区域(56)中均匀分布。

Description

3D堆叠的半导体器件及其制造方法、电子设备
本公开要求于2023年03月09日提交中国专利局、申请号为202310222594X、发明名称为“3D堆叠的半导体器件及其制造方法、电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本公开中。
技术领域
本公开实施例涉及但不限于半导体器件领域，尤指一种3D堆叠的半导体器件及其制造方法、电子设备。
背景技术
随着动态随机存取存储器(Dynamic Random Access Memory，DRAM)技术步入更小尺寸的节点，平面的1T1C结构已经趋于极限，为了获取更高的存储电容，更低漏电，更高集成度，DRAM存储器逐渐向3D立体结构发展。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制本公开的保护范围。
本公开实施例提供了一种3D堆叠的半导体器件的制造方法，所述3D堆叠的半导体器件的制造方法包括：
在衬底上依次交替沉积第一绝缘层和第二绝缘层，得到堆叠结构；
在所述堆叠结构中刻蚀形成多个朝向所述衬底延伸的第一沟槽，并且各所述第一沟槽沿第一方向延伸并沿第二方向间隔；
在所述第一沟槽中形成填充所述第一沟槽的虚拟位线层；
在所述堆叠结构的相邻两个所述虚拟位线层之间刻蚀形成一个朝向所述衬底延伸的第二沟槽，并且所述第二沟槽沿所述第一方向延伸；
刻蚀去除所述第二绝缘层，露出相邻第一绝缘层之间的所述虚拟位线层 的侧壁，所述侧壁沿所述第一方向延伸；
在所述虚拟位线层的露出的侧壁上形成填充在相邻第一绝缘层之间的膜层，所述膜层沿所述第一方向和所述第二方向延伸，所述膜层从靠近所述虚拟位线层的侧壁向第二方向依次含第一导电区域、半导体区域、第二导电区域；
对每个所述膜层进行纵向刻蚀形成多个沿所述第二方向延伸并在所述第一方向间隔的多个柱，每个所述柱包含第一导电区域、半导体区域、第二导电区域；在所述柱的半导体区域的侧壁形成环绕型的栅极绝缘层和栅电极，以及形成沿垂直于所述衬底的方向延伸的字线。
在本公开的示例性实施例中，所述衬底为单晶衬底，所述虚拟位线层为单晶膜层，并且所述虚拟位线层与所述衬底的材料相同；
所述在所述堆叠结构中刻蚀形成多个朝向所述衬底延伸的第一沟槽包括：
对所述堆叠结构中全部的所述第一绝缘层和所述第二绝缘层进行刻蚀，使所述第一沟槽露出所述衬底；
所述在所述第一沟槽中形成填充所述第一沟槽的虚拟位线层包括：
采用选择性外延工艺在露出的所述衬底上生长延伸进入所述第一沟槽并填满所述第一沟槽的所述虚拟位线层。
在本公开的示例性实施例中，所述膜层为单晶膜层，并且所述膜层与所述虚拟位线层的材料相同；
所述在所述虚拟位线层的露出的侧壁上形成填充在相邻第一绝缘层之间的膜层包括：
以所述虚拟位线层作为种子层，采用选择性外延工艺在所述虚拟位线层的露出的侧壁上生长沿所述第一方向和所述第二方向延伸的第一导电层；
采用选择性外延工艺在所述第一导电层远离所述虚拟位线层的一端生长沿所述第一方向和所述第二方向的半导体层；
采用选择性外延工艺在所述半导体层远离所述虚拟位线层的一端生长沿所述第一方向和所述第二方向延伸的第二导电层，所述第一导电层形成所述膜层的所述第一导电区域，所述半导体层形成所述膜层的所述半导体区域， 所述第二导电层形成所述膜层的所述第二导电区域。
在本公开的示例性实施例中，所述采用选择性外延工艺在所述虚拟位线层的露出的侧壁上生长沿所述第一方向和所述第二方向延伸的第一导电层可以包括：
采用选择性外延工艺在所述虚拟位线层的露出的侧壁上生长单晶硅，并在单晶硅的生长过程中采用原位掺杂法进行掺杂，得到由第一掺杂的单晶硅形成的所述第一导电层。
在本公开的示例性实施例中，所述采用选择性外延工艺在所述第一导电层远离所述虚拟位线层的一端生长沿所述第一方向和所述第二方向的半导体层包括：
采用选择性外延工艺在所述第一导电层远离所述虚拟位线层的一端生长本征单晶硅，得到由本征单晶硅形成的所述半导体层。
在本公开的示例性实施例中，所述采用选择性外延工艺在所述半导体层远离所述虚拟位线层的一端生长沿所述第一方向和所述第二方向延伸的第二导电层包括：
采用选择性外延工艺在所述半导体层远离所述虚拟位线层的一端生长单晶硅，并在单晶硅的生长过程中采用原位掺杂法进行掺杂，得到由第二掺杂的单晶硅形成的所述第二导电层。
在本公开的示例性实施例中，所述对每个所述膜层进行纵向刻蚀形成多个沿所述第二方向延伸并在所述第一方向间隔的多个柱可以包括：
对每个所述膜层进行纵向刻蚀，在所述膜层中形成沿所述第二方向延伸并且沿第一方向间隔的多个第三沟槽，所述第三沟槽将所述膜层间隔为多个所述柱。
在本公开的示例性实施例中，所述3D堆叠的半导体器件的制造方法还可以包括，在形成填充在相邻第一绝缘层之间的膜层之后，在将所述膜层间隔为多个所述柱之前，进行下述步骤：
在所述膜层远离所述虚拟位线层的端部形成与该端部接触的电容器的第三电极，并在所述衬底上沉积覆盖所述第三电极和所述第二沟槽的第一绝缘 层；
刻蚀去除所述第一沟槽内的所述虚拟位线层，使所述第一沟槽露出所述膜层和所述第一绝缘层。
在本公开的示例性实施例中，所述3D堆叠的半导体器件的制造方法还可以包括，在将所述膜层间隔为多个所述柱之后，进行下述步骤：
在所述衬底上沉积覆盖所述第三沟槽的第一绝缘层；
对相邻两个所述第一沟槽之间的第一绝缘层进行刻蚀，露出所述第三电极，保留所述第一沟槽侧壁上的所述第一绝缘层；
在露出的所述第三电极的表面依次沉积介电质层和第四电极，所述第三电极、所述介电质层和所述第四电极构成电容器。
在本公开的示例性实施例中，所述在所述膜层远离所述虚拟位线层的端部形成与该端部接触的电容器的第三电极可以包括：
采用多晶硅或金属在所述衬底上沉积覆盖所述膜层的被所述第二沟槽露出的端部的第三导电层，形成第三电极。
在本公开的示例性实施例中，所述在所述膜层远离所述虚拟位线层的端部形成与该端部接触的电容器的第三电极可以包括：
采用选择性外延工艺在所述膜层的被所述第二沟槽露出的端部生长单晶硅，并在单晶硅的生长过程中采用原位掺杂法进行掺杂，得到由掺杂的单晶硅形成的第三导电层，形成第三电极。
在本公开的示例性实施例中，所述在所述柱的半导体区域侧壁形成环绕型的栅极绝缘层和和栅电极可以包括：
在得到所述电容器之后，刻蚀去除所述第一沟槽侧壁上的所述第一绝缘层，形成栅极槽；
在所述栅极槽的内壁上沉积栅极绝缘层，以及在所述栅极槽中填充栅电极层；
刻蚀去除沿所述第一方向分布的相邻两个所述半导体柱之间的部分所述栅电极层，仅保留该两个半导体柱侧壁上的所述栅电极层，得到栅电极。
在本公开的示例性实施例中，所述3D堆叠的半导体器件的制造方法，还可以包括，在去除所述第一沟槽内的所述虚拟位线层之后，形成所述第三沟槽之前，进行下述步骤：
对所述第一沟槽内两侧的所述膜层的第一导电区域进行回刻，形成延伸进入所述膜层的第一导电区域并且沿所述第一方向延伸的位线槽，在所述位线槽中沉积位线。
在本公开的示例性实施例中，所述3D堆叠的半导体器件的制造方法还可以包括，在去除所述第一沟槽内的所述虚拟位线层之后，形成所述位线槽之前，进行下述步骤：
对所述第一沟槽两侧的所述第一绝缘层进行回刻，形成延伸进入所述第一绝缘层并且沿所述第一方向延伸的支撑槽，在所述支撑槽中沉积第二绝缘层形成支撑层。
在本公开的示例性实施例中，所述3D堆叠的半导体器件的制造方法还可以包括，在形成位线之后，形成所述第三沟槽之前，进行下述步骤：
在所述第一沟槽中沉积第三绝缘层，所述第三绝缘层将位于同一个所述第一沟槽内的相邻两条位线间隔开。
本公开实施例还提供一种3D堆叠的半导体器件，所述3D堆叠的半导体器件包括：
分布于不同层、沿着垂直于衬底的方向堆叠且周期性分布的多个存储单元，每一层包括沿第一方向和第二方向阵列分布的多个存储单元；
每个所述存储单元包括一个晶体管；所述晶体管包括沿所述第二方向延伸的柱和环绕所述柱的侧壁的栅电极，所述柱依次包括第一导电区域、半导体区域和第二导电区域；
其中，所述半导体区域包含所述柱的主体材料，所述第一导电区域包含第一掺杂材料，所述第二导电区域包含第二掺杂材料；所述第一掺杂材料在所述第一导电区域中均匀分布，所述第二掺杂材料在所述第二导电区域中均匀分布。
在本公开的示例性实施例中，所述主体材料可以为单晶硅、单晶锗、单 晶碳化硅或单晶砷化镓。
在本公开的示例性实施例中，所述主体材料可以为单晶硅，所述主体材料中不含有锗元素。
在本公开的示例性实施例中，所述主体材料可以为单晶锗，所述主体材料中不含有硅元素。
在本公开的示例性实施例中，所述3D堆叠的半导体器件还可以包括：沿所述第一方向延伸且在垂直于所述衬底的方向上间隔设置的多条位线，所述柱的第一导电区域与所述位线连接。
在本公开的示例性实施例中，所述3D堆叠的半导体器件还可以包括：沿垂直于所述衬底的方向延伸的多条字线，所述字线环绕所述柱的侧壁。
在本公开的示例性实施例中，位于同一层且沿所述第一方向分布的多个存储单元的晶体管的所述柱与同一条位线连接，并且与同一条位线连接的相邻两个所述柱之间通过连接部相连接，并且所述柱与所述连接部为一体式结构。
在本公开的示例性实施例中，与同一条位线连接的各所述柱的一端和所述连接部可以形成沿所述第一方向延伸的膜层，所述膜层与所述位线连接，并且所述膜层在所述衬底上的正投影与所述位线在所述衬底上的正投影相交叠。
在本公开的示例性实施例中，所述字线的横截面在所述字线的延伸方向不同位置的外轮廓可以是相同的。
在本公开的示例性实施例中，存储单元还包括电容器，所述电容器与所述柱的一端连接，所述电容器可以包括与所述柱的所述第二导电区域连接的第三电极、第四电极以及设置在所述第三电极和所述第四电极之间的介电质层。
在本公开的示例性实施例中，沿垂直于所述衬底的方向分布且在第二方向上间隔分布的两列存储单元的电容器的所述第四电极为共用电极。
在本公开的示例性实施例中，位于同一层且沿所述第一方向分布的一列存储单元的电容器的所述第四电极可以为一体式结构。
在本公开的示例性实施例中，所述两列存储单元的晶体管和电容器镜像分布。
在本公开的示例性实施例中，所述第三电极在所述柱的第二导电区域上采用外延工艺形成，所述第三电极的材料为单晶硅，所述第三电极与所述柱的第一导电区域、第二导电区域、半导体区域的截面相同。
本公开实施例还提供一种电子设备，所述电子设备包括如上本公开实施例提供的所述3D堆叠的半导体器件。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法的工艺流程图；
图2A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成堆叠结构后的立体结构示意图；
图2B为图2A所示的结构在平行于衬底的C1平面上的截面图；
图2C为图2A所示的结构在垂直于衬底的C2平面上的截面图；
图2D为图2A所示的结构在垂直于衬底的C3平面上的截面图；
图3A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成第一沟槽后在平行于衬底的C1平面上的截面图；
图3B为图3A所示的结构在垂直于衬底的C3平面上的截面图；
图4A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成虚拟位线层后在平行于衬底的C1平面上的截面图；
图4B为图4A所示的结构在垂直于衬底的C3平面上的截面图；
图5A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方 法在形成第二沟槽后在平行于衬底的C1平面上的截面图；
图5B为图5A所示的结构在垂直于衬底的C3平面上的截面图；
图6A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在去除第二绝缘层后在平行于衬底的C1平面上的截面图；
图6B为图6A所示的结构在垂直于衬底的C2平面上的截面图；
图6C为图6A所示的结构在垂直于衬底的C3平面上的截面图；
图7为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成第一导电层后在垂直于衬底的C3平面上的截面图；
图8A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成包括第一导电区域、半导体区域、第二导电区域的膜层后在平行于衬底的C1平面上的截面图；
图8B为图8A所示的结构在垂直于衬底的C2平面上的截面图；
图8C为图8A所示的结构在垂直于衬底的C3平面上的截面图；
图9A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成第三电极后在平行于衬底的C1平面上的截面图；
图9B为图9A所示的结构在垂直于衬底的C2平面上的截面图；
图9C为图9A所示的结构在垂直于衬底的C3平面上的截面图；
图10A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在去除虚拟位线层后在平行于衬底的C1平面上的截面图；
图10B为图10A所示的结构在垂直于衬底的C2平面上的截面图；
图10C为图10A所示的结构在垂直于衬底的C3平面上的截面图；
图11A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成支撑层后在平行于衬底的C1平面上的截面图；
图11B为图11A所示的结构在垂直于衬底的C2平面上的截面图；
图11C为图11A所示的结构在垂直于衬底的C3平面上的截面图；
图12A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成位线后在平行于衬底的C1平面上的截面图；
图12B为图12A所示的结构在垂直于衬底的C2平面上的截面图；
图12C为图12A所示的结构在垂直于衬底的C3平面上的截面图；
图13A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成绝缘层后在平行于衬底的C1平面上的截面图；
图13B为图13A所示的结构在垂直于衬底的C2平面上的截面图；
图13C为图13A所示的结构在垂直于衬底的C3平面上的截面图；
图14为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成半导体柱后在平行于衬底的C1平面上的截面图；
图15A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成第三初始沟槽后在平行于衬底的C1平面上的截面图；
图15B为图15A所示的结构在垂直于衬底的C2平面上的截面图；
图15C为图15A所示的结构在垂直于衬底的C3平面上的截面图；
图16A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在去除第三掩膜板后在平行于衬底的C1平面上的截面图；
图16B为图16A所示的结构在垂直于衬底的C2平面上的截面图；
图16C为图16A所示的结构在垂直于衬底的C3平面上的截面图；
图17A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成电容器后在平行于衬底的C1平面上的截面图；
图17B为图17A所示的结构在垂直于衬底的C2平面上的截面图；
图17C为图17A所示的结构在垂直于衬底的C3平面上的截面图；
图18A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成栅极槽后在平行于衬底的C1平面上的截面图；
图18B为图18A所示的结构在垂直于衬底的C2平面上的截面图；
图18C为图18A所示的结构在垂直于衬底的C3平面上的截面图；
图19A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成栅电极层但未形成栅电极时在平行于衬底的C1平面上的截面图；
图19B为图19A所示的结构在垂直于衬底的C2平面上的截面图；
图19C为图19A所示的结构在垂直于衬底的C3平面上的截面图；
图20A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法制得的器件在平行于衬底的C1平面上的截面图；
图20B为图20A所示的结构在垂直于衬底的C2平面上的截面图；
图20C为图20A所示的结构在垂直于衬底的C3平面上的截面图；
图20D为图20A所示的结构的局部放大图。
附图中的标记符号的含义为：
1-衬底；11-第一绝缘层；12-第二绝缘层；21-第一掩膜板；22-第二掩膜
板；23-第三掩膜板；31-第一沟槽；32-第二沟槽；33-第三沟槽；34-第四沟槽；40-位线；41-虚拟位线层；50-膜层；51-第一导电层；52-半导体层；53-第二导电层；54-柱；55-第一导电区域；56-第二导电区域；57-半导体区域；61-第三电极；62-介电质层；63-第四电极；70-支撑层；82-第三绝缘层；90-栅极绝缘层；100-栅电极；101-栅电极层；110-字线；120-存储单元；130-连接部。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开的实施方式并不一定限定附图所示尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本公开中的“第一”、“第二”等序数词是为了避免构成要素的混同而设置，并不表示任何顺序、数量或者重要性。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造 和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在公开中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本公开中，可以是第一电极为漏电极、第二电极为源电极，或者可以是第一电极为源电极、第二电极为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器器、其它具有各种功能的元件等。
在本公开中，“平行”是指大约平行或几乎平行，比如，两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指大约垂直，比如，两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本公开中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成“导电膜”。与此同样，有时可以将“绝缘膜”换成“绝缘层”。
本公开所说的“A和B位于同一层”是指，A和B通过同一次图案化工艺同时形成。
本公开实施例中的“A和B为一体式结构”可以是指在微观结构上无明显的断层或间隙等明显的分界界面。一般地，在一个膜层上图案化形成连接的膜层为一体式。比如A和B使用相同的材料成一个膜层并通过同一次图案化工艺同时形成具有连接关系的结构。
目前已知的单晶硅沟道的3D动态随机存取存储器(Dynamic Random Access Memory，DRAM)是利用外延工艺交错生长单晶硅沟道层和SiGe牺牲层形成叠层结构，然后再选择性刻蚀除去SiGe牺牲层，以及对单晶硅沟道层进行处理形成1T1C的DRAM存储单元。由于Si/SiGe晶格失配导致的应力在Si/SiGe多层堆叠后会释放出来，导致单晶硅沟道缺陷增多，引起器件的退化，严重影响DRAM的性能。
图1为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法的工艺流程图。
如图1所示，所述3D堆叠的半导体器件的制造方法包括：
在衬底上依次交替沉积第一绝缘层和第二绝缘层，得到堆叠结构；
在所述堆叠结构中刻蚀形成多个朝向所述衬底延伸的第一沟槽，并且各所述第一沟槽沿第一方向延伸并沿第二方向间隔；
在所述第一沟槽中形成填充所述第一沟槽的虚拟位线层；
在所述堆叠结构的相邻两个所述虚拟位线层之间刻蚀形成一个朝向所述衬底延伸的第二沟槽，并且所述第二沟槽沿所述第一方向延伸；
刻蚀去除所述第二绝缘层，露出相邻第一绝缘层之间的所述虚拟位线层的侧壁，所述侧壁沿第一方向延伸；
在所述虚拟位线层的露出的侧壁上形成填充在相邻第一绝缘层之间的膜层，所述膜层沿所述第一方向和所述第二方向延伸，所述膜层从靠近所述虚拟位线层的侧壁向第二方向依次含第一导电区域、半导体区域、第二导电区域；
对每个所述膜层进行纵向(即垂直于衬底的方向)刻蚀形成多个沿所述 第二方向延伸并在所述第一方向间隔的多个柱，每个所述柱包含第一导电区域、半导体区域、第二导电区域；在所述柱的半导体区域的侧壁形成环绕型的栅极绝缘层和栅电极，以及形成沿垂直于所述衬底的方向延伸的字线。
本公开实施例的3D堆叠的半导体器件的制造方法，通过先形成朝向衬底延伸的虚拟位线层，然后在虚拟位线层侧壁上形成包括第一导电区域、半导体区域、第二导电区域的膜层，再将该膜层间隔为多个用作晶体管的源漏极和沟道的柱的方法来形成晶体管，因此整个制造工艺中不需要外延形成SiGe等牺牲层，晶体管的沟道不会出现由于Si/SiGe晶格失配导致的缺陷，因此制得的3D堆叠的半导体器件的可靠性较高，而且由晶体管和电容器构成的存储单元在理论上可以在垂直于衬底的方向上无限堆叠，可以极大地提高3D器件的集成度。
另外，采用外延Si/SiGe叠层的方法形成的晶体管的源电极或漏电极中的掺杂元素分布不均匀，例如呈高斯分布，而本公开实施例的3D堆叠的半导体器件的制造方法得到的源电极或漏电极中的掺杂元素在源电极或漏电极的各个区域的掺杂浓度可以相同，从而实现掺杂元素在源电极或漏电极中的均匀分布。
在本公开的示例性实施例中，所述衬底为单晶衬底，所述虚拟位线层为单晶膜层，并且所述虚拟位线层与所述衬底的材料相同；
所述在所述堆叠结构中刻蚀形成多个朝向所述衬底延伸的第一沟槽可以包括：
对所述堆叠结构中全部的所述第一绝缘层和所述第二绝缘层进行刻蚀(即对各层第一绝缘层和各层第二绝缘层均进行刻蚀)，使所述第一沟槽露出所述衬底；
所述在所述第一沟槽中形成填充所述第一沟槽的虚拟位线层可以包括：
采用选择性外延工艺在露出的所述衬底上生长延伸进入所述第一沟槽并填满所述第一沟槽的所述虚拟位线层。
在本公开的示例性实施例中，所述膜层为单晶膜层，并且所述膜层与所述虚拟位线层的材料相同；
所述在所述虚拟位线层的露出的侧壁上形成填充在相邻第一绝缘层之间的膜层包括：
以所述虚拟位线层作为种子层，采用选择性外延工艺在所述虚拟位线层的露出的侧壁上生长沿所述第一方向和所述第二方向延伸的第一导电层；
采用选择性外延工艺在所述第一导电层远离所述虚拟位线层的一端生长沿所述第一方向和所述第二方向的半导体层；
采用选择性外延工艺在所述半导体层远离所述虚拟位线层的一端生长沿所述第一方向和所述第二方向延伸的第二导电层，所述第一导电层形成所述膜层的所述第一导电区域，所述半导体层形成所述膜层的所述半导体区域，所述第二导电层形成所述膜层的所述第二导电区域。
在本公开的示例性实施例中，所述第一导电层中可以含有第一掺杂材料，所述第二导电层中可以含有第二掺杂材料，并且所述第一掺杂材料在所述第一导电层的各个区域均匀分布，所述第二掺杂材料在所述第二导电层的各个区域均匀分布。
本公开的描述中，“掺杂材料在膜层的各个区域均匀分布”是指掺杂材料在膜层的各个区域的掺杂浓度相同(包括完全相同和大致相同)。
在本公开的示例性实施例中，所述第一掺杂材料与所述第二掺杂材料可以相同或不同。
在本公开的示例性实施例中，所述第一掺杂材料在所述第一导电层中的掺杂浓度为第一掺杂浓度，所述第二掺杂材料在所述第二导电层中的掺杂浓度为第二掺杂浓度，所述第一掺杂浓度与所述第二掺杂浓度可以相同(包括完全相同和大致相同)或不同。
在上述示例性实施例中，所述3D堆叠的半导体器件的制造方法可以首先通过在堆叠结构中开槽的方法露出单晶衬底，接着采用选择性外延工艺在露出的衬底上生长单晶虚拟位线层，然后选择性掏空堆叠结构中的第二绝缘层，使得形成后续选择性生长单晶膜层的通道，并且露出单晶虚拟位线层的部分侧壁，接着以露出的单晶虚拟位线层侧壁作为种子层，在通道中选择性外延生长出用于形成源漏极和沟道的单晶膜层。因此，本公开实施例的3D 堆叠的半导体器件的制造方法可以避免传统方法通过Si/SiGe超晶格外延来形成单晶硅沟道时受Si/SiGe超晶格外延层数限制的问题，从而突破存储单元堆叠层数的限制，使得在理论上存储单元在垂直于衬底的方向上可以无限堆叠，并且保证器件性能的可靠性。
另外，虚拟位线层还可以作为dummy BL占据后续形成位线的空间，后续去除虚拟位线层腾出空间后即可形成位线。
在本公开的示例性实施例中，所述第一导电层的主体材料可以为单晶硅；所述第二导电层的主体材料可以为单晶硅。
在本公开的示例性实施例中，所述采用选择性外延工艺在所述虚拟位线层的露出的侧壁上生长沿所述第一方向和所述第二方向延伸的第一导电层可以包括：
采用选择性外延工艺在所述虚拟位线层的露出的侧壁上生长单晶硅，并在单晶硅的生长过程中采用原位掺杂法进行掺杂，得到由第一掺杂的单晶硅形成的所述第一导电层。
在本公开的示例性实施例中，所述采用选择性外延工艺在所述第一导电层远离所述虚拟位线层的一端生长沿所述第一方向和所述第二方向的半导体层包括：
采用选择性外延工艺在所述第一导电层远离所述虚拟位线层的一端生长本征单晶硅，得到由本征单晶硅形成的所述半导体层。
在本公开的示例性实施例中，所述采用选择性外延工艺在所述半导体层远离所述虚拟位线层的一端生长沿所述第一方向和所述第二方向延伸的第二导电层包括：
采用选择性外延工艺在所述半导体层远离所述虚拟位线层的一端生长单晶硅，并在单晶硅的生长过程中采用原位掺杂法进行掺杂，得到由第二掺杂的单晶硅形成的所述第二导电层。
在本公开的示例性实施例中，所述对每个所述膜层进行纵向刻蚀形成多个沿所述第二方向延伸并在所述第一方向间隔的多个柱可以包括：
对每个所述膜层进行纵向刻蚀，在所述膜层中形成沿所述第二方向延伸 并且沿第一方向间隔的多个第三沟槽，所述第三沟槽将所述膜层间隔为多个所述柱。
在本公开的示例性实施例中，所述3D堆叠的半导体器件的制造方法还可以包括，在形成填充在相邻第一绝缘层之间的膜层之后，在将所述膜层间隔为多个所述柱之前，进行下述步骤：
在所述膜层远离所述虚拟位线层的端部形成与该端部接触的电容器的第三电极，并在所述衬底上沉积覆盖所述第三电极和所述第二沟槽的第一绝缘层；
刻蚀去除所述第一沟槽内的所述虚拟位线层，使所述第一沟槽露出所述膜层和所述第一绝缘层。
在本公开的示例性实施例中，所述3D堆叠的半导体器件的制造方法还可以包括，在将所述膜层间隔为多个所述柱之后，进行下述步骤：
在所述衬底上沉积覆盖所述第三沟槽的第一绝缘层；
对相邻两个所述第一沟槽之间的第一绝缘层进行刻蚀，露出所述第三电极，保留所述第一沟槽侧壁上的所述第一绝缘层；
在露出的所述第三电极的表面依次沉积介电质层和第四电极，所述第三电极、所述介电质层和所述第四电极构成电容器。
在本公开的示例性实施例中，所述在所述膜层远离所述虚拟位线层的端部形成与该端部接触的电容器的第三电极可以包括：
采用多晶硅或金属在所述衬底上沉积覆盖所述膜层的被所述第二沟槽露出的端部的第三导电层，形成第三电极。
在本公开的示例性实施例中，所述在所述膜层远离所述虚拟位线层的端部形成与该端部接触的电容器的第三电极可以包括：
采用选择性外延工艺在所述膜层的被所述第二沟槽露出的端部生长单晶硅，并在单晶硅的生长过程中采用原位掺杂法进行掺杂，得到由掺杂的单晶硅形成的第三导电层，形成第三电极。
在本公开的示例性实施例中，所述在所述柱的半导体区域侧壁形成环绕型的栅极绝缘层和和栅电极可以包括：
在得到所述电容器之后，刻蚀去除所述第一沟槽侧壁上的所述第一绝缘层，形成栅极槽；
在所述栅极槽的内壁上沉积栅极绝缘层，以及在所述栅极槽中填充栅电极层；
刻蚀去除沿所述第一方向分布的相邻两个所述半导体柱之间的部分所述栅电极层，仅保留该两个半导体柱侧壁上的所述栅电极层，得到栅电极。
在本公开的示例性实施例中，所述3D堆叠的半导体器件的制造方法还可以包括，在去除所述第一沟槽内的所述虚拟位线层之后，形成所述第三沟槽之前，进行下述步骤：
对所述第一沟槽内两侧的所述膜层的第一导电区域进行回刻，形成延伸进入所述膜层的第一导电区域并且沿所述第一方向延伸的位线槽，在所述位线槽中沉积位线。
在本公开的示例性实施例中，所述3D堆叠的半导体器件的制造方法还可以包括，在去除所述第一沟槽内的所述虚拟位线层之后，形成所述位线槽之前，进行下述步骤：
对所述第一沟槽两侧的所述第一绝缘层进行回刻，形成延伸进入所述第一绝缘层并且沿所述第一方向延伸的支撑槽，在所述支撑槽中沉积第二绝缘层形成支撑层。
在本公开的示例性实施例中，所述3D堆叠的半导体器件的制造方法还可以包括，在形成位线之后，形成所述第三沟槽之前，进行下述步骤：
在所述第一沟槽中沉积第三绝缘层，所述第三绝缘层将位于同一个所述第一沟槽内的相邻两条位线间隔开。
在本公开的示例性实施例中，所述衬底可以为单晶衬底，例如，单晶硅、单晶锗、单晶碳化硅或单晶砷化镓形成的衬底。
下面通过一个示例性实施例的3D堆叠的半导体器件的制造过程进一步说明本公开实施例的技术方案。本实施例中所说的“光刻法/光刻工艺”包括涂覆膜层、掩模曝光和显影，是相关技术中成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用 已知的方法，在此不做具体的限定。
图2A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成堆叠结构后的立体结构示意图；图2B为图2A所示的结构在平行于衬底的C1平面上的截面图；图2C为图2A所示的结构在垂直于衬底的C2平面上的截面图；图2D为图2A所示的结构在垂直于衬底的C3平面上的截面图；图3A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成第一沟槽后在平行于衬底的C1平面上的截面图；图3B为图3A所示的结构在垂直于衬底的C3平面上的截面图；图4A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成虚拟位线层后在平行于衬底的C1平面上的截面图；图4B为图4A所示的结构在垂直于衬底的C3平面上的截面图；图5A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成第二沟槽后在平行于衬底的C1平面上的截面图；图5B为图5A所示的结构在垂直于衬底的C3平面上的截面图；图6A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在去除第二绝缘层后在平行于衬底的C1平面上的截面图；图6B为图6A所示的结构在垂直于衬底的C2平面上的截面图；图6C为图6A所示的结构在垂直于衬底的C3平面上的截面图；图7为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成第一导电层后在垂直于衬底的C3平面上的截面图；图8A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成包括第一导电区域、半导体区域、第二导电区域的膜层后在平行于衬底的C1平面上的截面图；图8B为图8A所示的结构在垂直于衬底的C2平面上的截面图；图8C为图8A所示的结构在垂直于衬底的C3平面上的截面图；图9A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成第三电极后在平行于衬底的C1平面上的截面图；图9B为图9A所示的结构在垂直于衬底的C2平面上的截面图；图9C为图9A所示的结构在垂直于衬底的C3平面上的截面图；图10A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在去除虚拟位线层后在平行于衬底的C1平面上的截面图；图10B为图10A所示的结构在垂直于衬底的C2平面上的截面图；图10C为图10A所示的结构在垂直于衬底的C3平面上的截面图；图11A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成 支撑层后在平行于衬底的C1平面上的截面图；图11B为图11A所示的结构在垂直于衬底的C2平面上的截面图；图11C为图11A所示的结构在垂直于衬底的C3平面上的截面图；图12A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成位线后在平行于衬底的C1平面上的截面图；图12B为图12A所示的结构在垂直于衬底的C2平面上的截面图；图12C为图12A所示的结构在垂直于衬底的C3平面上的截面图；图13A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成绝缘层后在平行于衬底的C1平面上的截面图；图13B为图13A所示的结构在垂直于衬底的C2平面上的截面图；图13C为图13A所示的结构在垂直于衬底的C3平面上的截面图；图14为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成半导体柱后在平行于衬底的C1平面上的截面图；图15A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成第三初始沟槽后在平行于衬底的C1平面上的截面图；图15B为图15A所示的结构在垂直于衬底的C2平面上的截面图；图15C为图15A所示的结构在垂直于衬底的C3平面上的截面图；图16A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在去除第三掩膜板后在平行于衬底的C1平面上的截面图；图16B为图16A所示的结构在垂直于衬底的C2平面上的截面图；图16C为图16A所示的结构在垂直于衬底的C3平面上的截面图；图17A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成电容器后在平行于衬底的C1平面上的截面图；图17B为图17A所示的结构在垂直于衬底的C2平面上的截面图；图17C为图17A所示的结构在垂直于衬底的C3平面上的截面图；图18A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成栅极槽后在平行于衬底的C1平面上的截面图；图18B为图18A所示的结构在垂直于衬底的C2平面上的截面图；图18C为图18A所示的结构在垂直于衬底的C3平面上的截面图；图19A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法在形成栅电极层但未形成栅电极时在平行于衬底的C1平面上的截面图；图19B为图19A所示的结构在垂直于衬底的C2平面上的截面图；图19C为图19A所示的结构在垂直于衬底的C3平面上的截面图；图20A为本公开示例性实施例提供的一种3D堆叠的半导体器件的制造方法制得的器件 在平行于衬底的C1平面上的截面图；图20B为图20A所示的结构在垂直于衬底的C2平面上的截面图；图20C为图20A所示的结构在垂直于衬底的C3平面上的截面图。
如图2A至图20C所示，在一个示例性实施例中，所述3D堆叠的半导体器件的制造方法可以包括：
S10：提供衬底1，例如单晶硅衬底，在衬底1上依次交替沉积第一绝缘层11和第二绝缘层12，得到由多个第一绝缘层11和多个第二绝缘层12构成的堆叠结构；在所述堆叠结构的顶面上沉积第一掩膜板21，如图2A、图2B、图2C和图2D所示。
这里，图2B为在平行于衬底的C1平面上的截面图，并且C1平面穿过第二绝缘层12；图2C为在垂直于衬底的C2平面上的截面图，图2D为在垂直于衬底的C3平面上的截面，C3平面垂直于C2平面；C1平面、C2平面和C3平面的位置可以如图2A所示，后文的C1平面、C2平面和C3平面与图2A中的C1平面、C2平面和C3平面的方向相同，但截取位置可以不同。
在本公开的示例性实施例中，所述第一绝缘层和所述第二绝缘层的材料可以各自独立地选自氧化硅(例如，SiO2)、氮氧化硅(SiON)、氮化硅(SiN)、碳氮化硅(SiCN)中的任意一种或多种，并且所述第一绝缘层和所述第二绝缘层的材料不同，以便后续刻蚀去除第二绝缘层时，所述第一绝缘层和所述第二绝缘层可以具有不同的刻蚀速率，从而去除第二绝缘层而保留第一绝缘层。
图2A所示的堆叠结构包括六层第一绝缘层11和五层第二绝缘层12，仅为示例，在其他实施例中，所述堆叠结构可以包括更多或更少层交替设置的第一绝缘层11和第二绝缘层12。
所述第一掩膜板可以在后续对所述叠层结构进行刻蚀时作为硬掩膜(Hard Mask,HM)。在本公开的示例性实施例中，所述第一掩膜板的厚度可以为50nm。
S20：采用第一掩膜板21作为硬掩膜，在所述堆叠结构中刻蚀形成多个朝向衬底1延伸的第一沟槽31，并且第一沟槽31沿第一方向延伸，如图3A 和图3B所示；这里，图3A为在平行于衬底的C1平面上的截面图，并且C1平面穿过第二绝缘层12；图3B为在垂直于衬底的C3平面上的截面图；在不穿过第一沟槽31的C2平面上的截面图与图2C相同。所述第一方向可以为如图3A所示的X方向。
示例性地，步骤S20可以包括：
S21：采用光刻法在第一掩膜板21顶面上形成第一光刻胶图案，所述第一光刻胶图案露出第一掩膜板21的部分区域；
S22：以所述第一光刻胶图案为掩膜板，对第一掩膜板21中露出的部分区域进行刻蚀，在第一掩膜板21中形成多个沿所述第一方向延伸的初始第一沟槽，所述初始第一沟槽可以露出第一绝缘层11，去除所述第一光刻胶图案；
S23：对所述堆叠结构进行各向异性刻蚀，使所述初始第一沟槽朝向衬底1延伸，从而在所述堆叠结构中形成多个朝向衬底1延伸并且沿所述第一方向延伸的第一沟槽31，多个第一沟槽31沿第二方向间隔，第一沟槽31露出衬底1。所述第二方向可以为如图3A所示的Y方向。
在本公开的示例性实施例中，所述第一方向与所述第二方向可以相互垂直。
示例性地，步骤S23中的所述各向异性刻蚀可以为干法刻蚀。
示例性地，第一沟槽31可以垂直于衬底1。
S30：在第一沟槽31中形成虚拟位线层41。
示例性地，步骤S30可以包括：在第一沟槽31中选择性外延生长虚拟位线层41，并使虚拟位线层41填满第一沟槽31，如图4A和图4B所示，虚拟位线层41的材料可以为单晶硅；这里，图4A为在平行于衬底的C1平面上的截面图，并且C1平面穿过第二绝缘层12；图4B为在垂直于衬底的C3平面上的截面图；在不穿过第一沟槽31的C2平面上的截面图与图2C相同。
S40：对所述堆叠结构进行刻蚀，在相邻两个虚拟位线层41之间形成一个朝向衬底1延伸的第二沟槽32，并且第二沟槽32沿第一方向延伸，如图5A和图5B所示；这里，图5A为在平行于衬底的C1平面上的截面图，并且C1平面穿过第二绝缘层12；图5B为在垂直于衬底的C3平面上的截面图； 在不穿过第一沟槽31和第二沟槽32的C2平面上的截面图与图2C相同。示例性地，步骤S40中可以参照步骤S21至S23形成第二沟槽32。
示例性地，第二沟槽32可以垂直于衬底1；第二沟槽32与第一沟槽31可以相互平行。
S50：采用各向同性刻蚀法去除第二绝缘层12，使第二沟槽32中露出位于相邻第一绝缘层之间的虚拟位线层41的部分侧壁，露出的侧壁沿所述第一方向延伸，如图6A、图6B和图6C所示；这里，图6A为在平行于衬底的C1平面上的截面图，并且C1平面穿过第一绝缘层11；图6B为在垂直于衬底的C2平面上的截面图，并且C2平面位于第一沟槽31与第二沟槽32之间；图6C为在垂直于衬底的C3平面上的截面图。
S60：在虚拟位线层41的露出的侧壁上形成填充在相邻第一绝缘层之间的膜层50，这里的膜层50沿所述第一方向和所述第二方向延伸，膜层50在所述第二方向上沿着远离虚拟位线层41的方向依次包括第一导电区域、半导体区域、第二导电区域，并且第二沟槽32露出膜层50远离虚拟位线层41一端(即第二导电区域)的端面，多个膜层50和多个第一绝缘层11交错堆叠构成叠层结构。
示例性地，步骤S60可以包括：
S61：在虚拟位线层41的露出的侧壁上形成沿所述第一方向和所述第二方向延伸的第一导电层51，第一导电层51延伸进入相邻两层第一绝缘层11之间，第一导电层形成膜层50的所述第一导电区域；如图7所示；这里，图7为在垂直于衬底的C3平面上的截面图；在穿过第一绝缘层11的C1平面上的截面图与图6A相同，在位于第一沟槽31与第二沟槽32之间的C2平面上的截面图与图6B相同；
S62：在第一导电层51远离虚拟位线层41的一端依次形成半导体层52和第二导电层53，半导体层52形成膜层50的所述半导体区域，第二导电层53形成膜层50的所述第二导电区域，第一导电层51、半导体层52和第二导电层53构成膜层50，第二沟槽32露出第二导电层53的端面，多个膜层50和多个第一绝缘层11交错堆叠构成叠层结构，如图8A、图8B和图8C所示；这里，图8A为在平行于衬底的C1平面上的截面图，并且C1平面穿过膜层 50；图8B为在垂直于衬底的C2平面上的截面图，并且C2平面穿过第一沟槽31；图8C为在垂直于衬底的C3平面上的截面图。
示例性地，S61中可以采用选择性外延工艺在虚拟位线层41的露出的侧壁上生长第一导电层51。第一导电层51的材料可以为含有第一掺杂材料的单晶硅，可以采用原位掺杂法形成，即在生长单晶硅的过程中通入含有第一掺杂材料的掺杂气体，采用原位掺杂法形成第一导电层51可以使第一掺杂材料均匀分布在第一导电层51的各个区域，并且第一掺杂材料不会扩散进入虚拟位线层41。第一导电层51中的第一掺杂材料可以为砷(As)，掺杂浓度可以为1e19。
示例性地，半导体层52的材料可以为本征单晶硅，可以采用选择性外延工艺形成半导体层52。
示例性地，第二导电层53的材料可以为含有第二掺杂材料的单晶硅，可以采用选择性外延工艺和原位掺杂法在单晶硅的生长过程中掺杂第二掺杂材料，形成第二导电层53，第二导电层53中的第二掺杂材料可以为砷(As)，掺杂浓度可以为1e19。
示例性地，如图8C所示，对于位于同一个虚拟位线层40侧壁上的膜层50和第一绝缘层11，膜层50在所述第二方向上的长度L1可以小于第一绝缘层11在所述第二方向上的长度L2，使得相邻两个第一绝缘层11之间在垂直于衬底1的方向上具有空隙。
S70：在衬底1上沉积第三导电层，得到覆盖膜层50的露出端(即膜层50的第二导电区域)的第三电极61；在衬底1上沉积第一绝缘层11，使第一绝缘层11覆盖第三电极61和第二沟槽32。
示例性地，步骤S70可以包括：
S71：在衬底1上形成第三导电层，使所述第三导电层填满所述叠层结构的相邻两层第一绝缘层11之间的空隙，第一绝缘层11的侧壁也可能会被所述第三导电层覆盖；
S72：对所述第三导电层进行各向异性刻蚀，去除第一绝缘层11的侧壁上的所述第三导电层，并使相邻两层第一绝缘层11之间的所述第三导电层的 两端与第一绝缘层11的两端平齐，剩余的第三导电层形成第三电极61，第三电极61覆盖膜层50远离虚拟位线层41一端的端面并且露出第一绝缘层11的端面；
S73：在衬底1上沉积第一绝缘层11，使第一绝缘层11覆盖第三电极61和第二沟槽32，并通过化学机械抛光(Chemical Mechanical Polishing,CMP)对衬底1表面的第一绝缘层11进行平坦化并去除剩余的第一掩膜板21，如图9A、图9B和图9C所示；这里，图9A为在平行于衬底的C1平面上的截面图，并且C1平面穿过膜层50；图9B为在垂直于衬底的C2平面上的截面图，并且C2平面位于第一沟槽31与第二沟槽32之间；图9C为在垂直于衬底的C3平面上的截面图。
在本公开的示例性实施例中，所述第三导电层的材料可以为多晶硅、重掺杂的单晶硅、导电金属等。例如，所述第三导电层的材料为重掺杂的单晶硅，此时可以通过选择性外延工艺和原位掺杂法形成所述第三导电层。
S80：采用各向异性刻蚀法去除第一沟槽31内的虚拟位线层41，第一沟槽31露出膜层50远离第三电极61一侧(即膜层50的第一导电区域)的侧壁，第一沟槽31还露出第一绝缘层11。
示例性地，步骤S80可以包括：
S81：在所述叠层结构的顶面上沉积第二掩膜板22，采用光刻法在第二掩膜板22顶面上形成第二光刻胶图案，所述第二光刻胶图案露出第二掩膜板22的部分区域；
S82：以所述第二光刻胶图案为掩膜板，对第二掩膜板22中露出的部分区域进行刻蚀，在第二掩膜板22中形成多个沿所述第一方向延伸的初始第二沟槽，所述初始第二沟槽可以露出第一绝缘层11，去除所述第二光刻胶图案；
S83：对所述叠层结构进行各向异性刻蚀，使所述初始第二沟槽朝向衬底1延伸，从而刻蚀去除第一沟槽31内的虚拟位线层41，腾空的第一沟槽31露出膜层50远离第三电极61一侧的侧壁，例如，可以露出膜层50的第一导电层51远离第三电极61一侧的侧壁，第一沟槽31还露出第一绝缘层11，如图10A、图10B和图10C所示；这里，图10A为在平行于衬底的C1平面上的截面图，并且C1平面穿过膜层50；图10B为在垂直于衬底的C2 平面上的截面图，并且C2平面位于第一沟槽31与第二沟槽32之间；图10C为在垂直于衬底的C3平面上的截面图。
S90：对第一沟槽31两侧的第一绝缘层11进行回刻，形成延伸进入第一绝缘层11并且沿所述第一方向延伸的支撑槽，在所述支撑槽中沉积第二绝缘层12，形成位于所述支撑槽中的支撑层70，如图11A、图11B和图11C所示；这里，图11A为在平行于衬底的C1平面上的截面图，并且C1平面穿过支撑层70；图11B为在垂直于衬底的C2平面上的截面图，并且C2平面穿过支撑层70；图11C为在垂直于衬底的C3平面上的截面图。
示例性地，步骤S90可以包括：在衬底1上沉积覆盖所述支撑槽、第一沟槽31和第二掩膜板22的第二绝缘层12，采用各向异性刻蚀法去除第一沟槽31内的第二绝缘层12，所述支撑槽中的第二绝缘层12形成支撑层70。
S100：对第一沟槽31两侧的膜层50进行回刻，形成延伸进入膜层50并且沿所述第一方向延伸的位线槽，在衬底1上沉积覆盖所述位线槽的第五导电层，形成位于所述位线槽中的位线40，如图12A、图12B和图12C所示；这里，图12A为在平行于衬底的C1平面上的截面图，并且C1平面穿过位线40；图12B为在垂直于衬底的C2平面上的截面图，并且C2平面穿过位线40；图12C为在垂直于衬底的C3平面上的截面图。
在本公开的示例性实施例中，所述第五导电层可以为多层结构，例如，可以包括防氧化层和金属层。所述防氧化层可以防止金属层中的金属被氧化，可以由氮化钛(TiN)等形成。所述金属层可以由钨(W)等金属形成。
示例性地，步骤S100可以包括：
S101：采用各向同性刻蚀法，在第一沟槽31内对横向刻蚀两侧的膜层50，形成延伸进入膜层50的第一导电层51并且沿所述第一方向延伸的位线槽；
S102：在衬底1上沉积覆盖所述位线槽内壁、第一沟槽31内壁和衬底1顶面的第二绝缘层12的防氧化层，以及在衬底1上沉积填满所述位线槽和第一沟槽31并覆盖所述防氧化层的金属层，所述防氧化层和所述金属层构成第五导电层；
S103：采用各向同性刻蚀法，去除第一沟槽31内的第五导电层，所述位线槽内的第五导电层形成位线40，位线40分布在第一沟槽31两侧并且沿所述第一方向延伸。
S110：在衬底1上沉积覆盖第一沟槽31的第三绝缘层82，并通过CMP工艺对第三绝缘层进行平坦化，所述第三绝缘层82将位于同一个第一沟槽31内的相邻两条位线40间隔开，如图13A、图13B和图13C所示；这里，图13A为在平行于衬底的C1平面上的截面图，并且C1平面穿过膜层50；图13B为在垂直于衬底的C2平面上的截面图，并且C2平面穿过位线40；图13C为在垂直于衬底的C3平面上的截面图。
示例性地，步骤S110中的CMP工艺还可以包括：去除所述叠层结构顶面的第五导电层、第二绝缘层12和第二掩膜板22。
在本公开的示例性实施例中，所述第三绝缘层与所述第二绝缘层的材料可以相同，例如，可以均为氮化硅(SiN)。
S120：对所述叠层结构进行刻蚀，在所述叠层结构的相邻两个第一沟槽31之间形成朝着衬底1延伸并且沿所述第二方向延伸的多个第三沟槽33，第三沟槽33将膜层50间隔为在所述第一方向上间隔分布的多个柱54，膜层50的第一导电层51对应形成柱54的第一导电区域55，膜层50的第二导电层53对应形成柱54的第二导电区域56，膜层50的半导体层对应形成柱54的半导体区域57，因此柱54依次包括第一导电区域55、半导体区域57和第二导电区域56，如图14所示，这里，图14为在平行于衬底的C1平面上的截面图，并且C1平面穿过柱54；在垂直于衬底的C2平面上的截面图与图13B相同，在垂直于衬底的C3平面上的截面图与图13C相同。
示例性地，步骤S120可以参照步骤S21至步骤S23通过沉积掩膜板，对所述掩膜板进行光刻和刻蚀，去除所述掩膜板上的光刻胶，对所述叠层结构进行各向异性刻蚀的方法形成多个第三沟槽33。
如图14所示，相邻两个第一沟槽31之间沿所述第二方向分布有两个柱54，并且该两个柱54通过第二沟槽32内的第一绝缘层11相间隔。沿所述第一方向分布的位于同一层的多个柱与一条位线40连接。
示例性地，第三沟槽33可以垂直于衬底1。
S130：在衬底1上沉积覆盖第三沟槽33的第一绝缘层11。
S140：对相邻两个第一沟槽31之间的第一绝缘层11进行刻蚀，露出第三电极61，保留第一沟槽31侧壁上的第一绝缘层11。
示例性地，步骤S140可以包括：
S141：在衬底1顶面沉积第三掩膜板23，采用光刻在第三掩膜板23顶面形成第三光刻胶图案，以所述第三光刻胶图案为掩膜板对第三掩膜板23进行刻蚀，在第三掩膜板23中形成沿所述第一方向延伸的第三初始沟槽，去除所述第三光刻胶图案，如图15A、图15B和图15C所示；这里，图15A为在平行于衬底的C1平面上的截面图，并且C1平面穿过柱54；图15B为在垂直于衬底的C2平面上的截面图，并且C2平面穿过柱54；图15C为在垂直于衬底的C3平面上的截面图；
S142：采用各向异性刻蚀法对相邻两个第一沟槽31之间的第一绝缘层11进行刻蚀，使得所述第三初始沟槽朝向衬底1延伸形成沿所述第一方向延伸的第四沟槽34；示例性地，第四沟槽34可以在第二沟槽32的位置上形成并且二者的尺寸相同；
S143：在第四沟槽34中对第一绝缘层11进行各向同性刻蚀，使得去除覆盖第三电极61的第一绝缘层11而露出第三电极61，但保留第三绝缘层82侧壁上的第一绝缘层11，去除第三掩膜板23，如图16A、图16B和图16C所示；这里，图16A为在平行于衬底的C1平面上的截面图，并且C1平面穿过柱54；图16B为在垂直于衬底的C2平面上的截面图，并且C2平面穿过柱54；图16C为在垂直于衬底的C3平面上的截面图。
S150：在露出的第三电极61表面依次沉积介电质层和第四导电层，分别形成介电质层62和第四电极63，第三电极61、介电质层62和第四电极63构成电容器，如图17A、图17B和图17C所示；这里，图17A为在平行于衬底的C1平面上的截面图，并且C1平面穿过柱54；图17B为在垂直于衬底的C2平面上的截面图，并且C2平面穿过柱54；图17C为在垂直于衬底的C3平面上的截面图。
在本公开的示例性实施例中，所述介电质层可以由High-K介电质材料 形成，即介电常数K≥3.9的介电质材料。所述High-K介电质材料可以包括但不限于以下至少之一：氧化硅、三氧化二铝(Al2O3)、氧化铪等。
在本公开的示例性实施例中，所述第四导电层的材料包括但不限于以下至少之一：多晶硅、钨、氮化钛。
在本公开的示例性实施例中，在沉积所述介电质层之前，可以先在所述第四沟槽的侧壁上沉积第二绝缘层12，也可以不沉积第二绝缘层12。
在本公开的示例性实施例中，在沉积所述第四导电层之前，可以在所述介电质层表面先沉积TiN等形成防氧化层，以防止形成第四电极63的钨金属受到氧化硅等含氧介电质层的影响而氧化。当然若介电质层为不含氧的膜层，则不需要增加防氧化层。
在本公开的示例性实施例中，如图17A所示，位于同一层且延伸进入同一个第四沟槽中的多个柱54上的第四电极63可以为一体式结构。
在本公开的示例性实施例中，如图17C所示，沿垂直于衬底1的方向分布的多个电容器的第四电极63可以为一体式结构。
在本公开的示例性实施例中，如图17A和图17C所示，沿所述第二方向相向延伸进入同一个第四沟槽中的相邻两个柱54上的两个第四电极63可以为共用的。
在本公开的示例性实施例中，如图17A和图17C所示，位于第四沟槽中的多个第四电极63可以为一体式结构。
S160：刻蚀去除第一沟槽31侧壁上的第一绝缘层11，形成栅极槽，如图18A、图18B和图18C所示；这里，图18A为在平行于衬底的C1平面上的截面图，并且C1平面穿过柱54；图18B为在垂直于衬底的C2平面上的截面图，并且C2平面穿过去除第一绝缘层11后形成的沟槽；图18C为在垂直于衬底的C3平面上的截面图。
S170：在所述栅极槽的内壁上沉积栅极绝缘层90，以及在所述栅极槽中填充栅电极层101，如图19A、图19B和图19C所示；这里，图19A为在平行于衬底的C1平面上的截面图，并且C1平面穿过柱54；图19B为在垂直于衬底的C2平面上的截面图，并且C2平面穿过栅电极层91；图19C为在 垂直于衬底的C3平面上的截面图。
S180：刻蚀去除沿所述第一方向分布的相邻两个柱54之间的部分栅电极层101，仅保留该两个柱54侧壁上的栅电极层101，得到栅电极100，柱54和栅电极100构成晶体管，如图20A、图20B和图20C所示；这里，图20A为在平行于衬底的C1平面上的截面图，并且C1平面穿过柱54；图20B为在垂直于衬底的C2平面上的截面图，并且C2平面穿过栅电极100；图20C为在垂直于衬底的C3平面上的截面图。
示例性地，可以通过沉积掩膜板、光刻和刻蚀法去除沿所述第一方向分布的相邻两个柱54之间的部分栅电极层。
在本公开的示例性实施例中，所述栅极绝缘层可以是High-K介质材料，即介电常数K≥3.9的介质材料。所述High-K介质材料可以包括但不限于以下至少之一：氧化硅、三氧化二铝(Al2O3)、氧化铪。
在本公开的示例性实施例中，可以通过ALD沉积所述栅极绝缘层。
在本公开的示例性实施例中，所述栅电极层可以是导电材料形成或者包括导电材料，并且导电材料可以是例如掺杂半导体材料、导电金属氮化物、金属材料和金属-半导体化合物中的一种，比如可以为W等；示例性地，所述栅电极层可以包括但不限于以下至少之一：氧化铟锡(Indium Tin Oxide，ITO)、TiN和W的复合膜层、掺铝氧化锌(Aluminum doped Zinc Oxide，AZO)、氧化铟锌(Indium Zinc Oxide，IZO)。
在本公开的示例性实施例中，如图20B和图20C所示，沿垂直于衬底1的方向分布的一列晶体管的栅电极100可以与同一条字线110连接，或者，沿垂直于衬底1的方向分布的一列晶体管的栅电极100连接在一起形成一条字线110。
本公开实施例还提供一种3D堆叠的半导体器件，所述3D堆叠的半导体器件可以通过如上本公开实施例提供的3D堆叠的半导体器件的制造方法制得。
如图20A、图20B和图20C所示，本公开实施例提供的所述3D堆叠的半导体器件包括：
分布于不同层、沿着垂直于衬底1的方向堆叠且周期性分布的多个存储单元120，每一层包括沿第一方向和第二方向阵列分布的多个存储单元120；
每个所述存储单元120包括一个晶体管；所述晶体管包括沿所述第二方向延伸的柱54和环绕柱54侧壁的栅电极100，柱54依次包括第一导电区域55、半导体区域57和第二导电区域56；
一些实施例中，所述存储单元为1T1C结构，所述存储单元还包括电容器，所述电容器的其中一个电极与柱54一端连接；
一些实施方式中，所述存储单元为2T0C结构或1T无电容器的结构，所述存储单元不包含用于存储电容的电容器。
以下实施例以存储单元为1T1C结构为例说明。
其中，半导体区域57包含柱54的主体材料，第一导电区域55包含第一掺杂材料，第二导电区域56包含第二掺杂材料，所述第一掺杂材料在第一导电区域55的各个区域均匀分布，所述第二掺杂材料在第二导电区域56的各个区域均匀分布。
所述第一方向可以为如图20A所示的X方向，所述第二方向可以为如图20A所示的Y方向，所述第一方向与所述第二方向可以相互垂直。
本公开实施例的3D堆叠的半导体器件无需通过外延SiGe等牺牲层来形成晶体管沟道，而是可以采用如上本公开实施例提供的3D堆叠的半导体器件的制造方法通过以虚拟位线层作为种子层，在种子层上选择性外延生长的方式形成晶体管的沟道和源漏极，因此3D堆叠的半导体器件的可靠性较高，而且存储单元在理论上可以在垂直于衬底的方向上无限堆叠，可以极大地提高3D器件的集成度。
所述栅电极环绕所述半导体柱的侧壁，其中，环绕可以理解为栅电极部分或全部环绕半导体柱的侧壁。一些实施例中，所述环绕可以是栅电极在整体上全部环绕所述半导体柱的侧壁，即所述栅电极的横截面为闭合环形，如图20A、图20B和图20C所示。所述横截面的截取方向为沿着平行于衬底的方向截取。一些实施例中，所述环绕可以是部分环绕，环绕后的横截面不是闭合的，但是呈现环形状。比如，具有开口的环形。
在本公开的示例性实施例中，所述主体材料可以为单晶硅、单晶锗、单晶碳化硅或单晶砷化镓。
在本公开的示例性实施例中，所述主体材料可以为单晶硅，所述主体材料中不含有锗元素，因此本公开实施例的3D堆叠的半导体器件在形成单晶硅沟道时可以不需要外延Si/SiGe叠层，可以避免传统方法通过Si/SiGe超晶格外延来形成单晶硅沟道时受Si/SiGe超晶格外延层数限制的问题，从而突破存储单元堆叠层数的限制，使得在理论上存储单元在垂直于衬底的方向上可以无限堆叠，并且保证器件性能的可靠性。
在本公开的示例性实施例中，所述第一掺杂材料在所述第一导电区域中的掺杂浓度为第一掺杂浓度，所述第二掺杂材料在所述第二导电区域中的掺杂浓度为第二掺杂浓度，所述第一掺杂浓度与所述第二掺杂浓度可以相同或不同；所述第一掺杂材料与所述第二掺杂材料可以相同或不同。例如，所述第一掺杂材料与所述第二掺杂材料可以均为砷，所述第一掺杂浓度与所述第二掺杂浓度可以均为1e19。
在本公开的示例性实施例中，所述第一导电区域可以作为源电极，所述第二导电区域可以作为漏电极；或者，所述第一电极可以作为漏电极，所述第二电极可以作为源电极。
在本公开的示例性实施例中，一个所述晶体管的所述第一导电区域和所述第二导电区域之间的沟道可以为水平沟道。
水平沟道为沟道中载流子传输方向在平行于衬底的平面内，但是不限制载流子的传输方向必须是一个方向。实际应用中，载流子的传输方向整体上沿着一个方向延伸，但是在局部，与半导体层的形状有关。换句话说，水平沟道不代表在水平面内必须沿着一个方向延伸，可能沿着不同的方向延伸。当然载流子传输方向在平行于衬底的平面内也是一个宏观上的概念，并不局限于绝对的平行于衬底，本公开保护第一电极和第二电极之间的沟道为非垂直于衬底的沟道。
在本公开的示例性实施例中，如图20A和图20C所示，所述3D堆叠的半导体器件还可以包括：沿所述第一方向延伸的多条位线40，多条位线40在垂直于所述衬底的方向上间隔设置，柱54的第一导电区域与位线40连接。
在本公开的示例性实施例中，如图20A所示，位于同一层且沿所述第一方向分布的多个存储单元120的晶体管可以与同一条位线40连接。
在本公开的示例性实施例中，如图20A、图20B和图20C所示，所述3D堆叠的半导体器件还可以包括：沿垂直于所述衬底1的方向延伸的多条字线110，字线110环绕柱54的侧壁。
在本公开的示例性实施例中，沿垂直于所述衬底1的方向分布的一列存储单元120的晶体管的栅电极100与同一条字线110连接。
在本公开的示例性实施例中，如图20D所示，位于同一层且沿所述第一方向分布的多个存储单元的晶体管的所述柱54与同一条位线40连接，并且与同一条位线40连接的相邻两个所述柱54之间通过连接部130相连接，并且所述柱54与所述连接部130为一体式结构。
在本公开的示例性实施例中，与同一条位线40连接的各所述柱54的一端和所述连接部130形成沿所述第一方向延伸的膜层50，所述膜层50与所述位线40连接，并且所述膜层50在所述衬底1上的正投影与所述位线40在所述衬底1上的正投影相交叠。
在本公开的示例性实施例中，所述字线的横截面在所述字线的延伸方向不同位置的外轮廓是相同的。
在本公开的示例性实施例中，如图20C所示，所述3D堆叠的半导体器件还可以包括：沿所述第一方向延伸的多个支撑层70，支撑层70设置在沿垂直于所述衬底1的方向分布的相邻两条位线40之间，将位线40与字线110间隔开。通过支撑层70将位线40与字线110间隔开可以避免位线40与字线110之间形成寄生电容器。
在本公开的示例性实施例中，如图20A和图20C所示，所述电容器可以包括第三电极61、第四电极63以及设置在第三电极61与第四电极63之间的介电质层62，第三电极61与柱54的所述第二导电区域连接。
在本公开的示例性实施例中，沿垂直于所述衬底的方向分布且在第二方向上间隔分布的两列存储单元的电容器的所述第四电极为共用电极，所述两列存储单元的晶体管和电容器镜像分布。在本公开的示例性实施例中，如图 20C所示，沿垂直于所述衬底1的方向分布的一列存储单元120的电容器的第四电极63可以为一体式结构。
在本公开的示例性实施例中，如图20A所示，位于同一层且沿所述第一方向分布的一列存储单元120的电容器的第四电极63可以为一体式结构。
在本公开的示例性实施例中，如图20C所示，位于同一层且沿所述第二方向分布的至少两个相邻的存储单元120的电容器的第四电极63可以为一体式结构。
在本公开的示例性实施例中，所述第三电极在所述柱的第二导电区域上采用外延工艺形成，所述第三电极的材料为单晶硅，所述第三电极与所述柱的第一导电区域、第二导电区域、半导体区域的截面相同。
在本公开的示例性实施例中，所述3D堆叠的半导体器件可以为3D存储器，例如，3D DRAM等存储器。所述3D存储器可以为1T1C结构。
本公开实施例还提供一种电子设备，所述电子设备包括如上本公开实施例提供的所述3D堆叠的半导体器件。
在本公开的示例性实施例中，所述电子设备可以为：存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源等。存储装置可以包括计算机中的内存等，此处不作限定。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种3D堆叠的半导体器件的制造方法，包括：
    在衬底上依次交替沉积第一绝缘层和第二绝缘层，得到堆叠结构；
    在所述堆叠结构中刻蚀形成多个朝向所述衬底延伸的第一沟槽，并且各所述第一沟槽沿第一方向延伸并沿第二方向间隔；
    在所述第一沟槽中形成填充所述第一沟槽的虚拟位线层；
    在所述堆叠结构的相邻两个所述虚拟位线层之间刻蚀形成一个朝向所述衬底延伸的第二沟槽，并且所述第二沟槽沿所述第一方向延伸；
    刻蚀去除所述第二绝缘层，露出相邻第一绝缘层之间的所述虚拟位线层的侧壁，所述侧壁沿着第一方向延伸；
    在所述虚拟位线层的露出的侧壁上形成填充在相邻第一绝缘层之间的膜层，所述膜层沿所述第一方向和所述第二方向延伸，所述膜层从靠近所述虚拟位线层的侧壁向第二方向依次含第一导电区域、半导体区域、第二导电区域；
    对每个所述膜层进行纵向刻蚀形成多个沿所述第二方向延伸并在所述第一方向间隔的多个柱，每个所述柱包含第一导电区域、半导体区域、第二导电区域；在所述柱的半导体区域的侧壁形成环绕型的栅极绝缘层和栅电极，以及形成沿垂直于所述衬底的方向延伸的字线。
  2. 根据权利要求1所述的3D堆叠的半导体器件的制造方法，其中，所述衬底为单晶衬底，所述虚拟位线层为单晶膜层，并且所述虚拟位线层与所述衬底的材料相同；
    所述在所述堆叠结构中刻蚀形成多个朝向所述衬底延伸的第一沟槽包括：
    对所述堆叠结构中全部的所述第一绝缘层和所述第二绝缘层进行刻蚀，使所述第一沟槽露出所述衬底；
    所述在所述第一沟槽中形成填充所述第一沟槽的虚拟位线层包括：
    采用选择性外延工艺在露出的所述衬底上生长延伸进入所述第一沟槽并填满所述第一沟槽的所述虚拟位线层。
  3. 根据权利要求2所述的3D堆叠的半导体器件的制造方法，其中，所述膜层为单晶膜层，并且所述膜层与所述虚拟位线层的材料相同；
    所述在所述虚拟位线层的露出的侧壁上形成填充在相邻第一绝缘层之间的膜层包括：
    以所述虚拟位线层作为种子层，采用选择性外延工艺在所述虚拟位线层的露出的侧壁上生长沿所述第一方向和所述第二方向延伸的第一导电层；
    采用选择性外延工艺在所述第一导电层远离所述虚拟位线层的一端生长沿所述第一方向和所述第二方向的半导体层；
    采用选择性外延工艺在所述半导体层远离所述虚拟位线层的一端生长沿所述第一方向和所述第二方向延伸的第二导电层，所述第一导电层形成所述膜层的所述第一导电区域，所述半导体层形成所述膜层的所述半导体区域，所述第二导电层形成所述膜层的所述第二导电区域。
  4. 根据权利要求3所述的3D堆叠的半导体器件的制造方法，其中，
    所述采用选择性外延工艺在所述虚拟位线层的露出的侧壁上生长沿所述第一方向和所述第二方向延伸的第一导电层包括：
    采用选择性外延工艺在所述虚拟位线层的露出的侧壁上生长单晶硅，并在单晶硅的生长过程中采用原位掺杂法进行掺杂，得到由第一掺杂的单晶硅形成的所述第一导电层；和/或，
    所述采用选择性外延工艺在所述第一导电层远离所述虚拟位线层的一端生长沿所述第一方向和所述第二方向的半导体层包括：
    采用选择性外延工艺在所述第一导电层远离所述虚拟位线层的一端生长本征单晶硅，得到由本征单晶硅形成的所述半导体层；和/或，
    所述采用选择性外延工艺在所述半导体层远离所述虚拟位线层的一端生长沿所述第一方向和所述第二方向延伸的第二导电层包括：
    采用选择性外延工艺在所述半导体层远离所述虚拟位线层的一端生长单晶硅，并在单晶硅的生长过程中采用原位掺杂法进行掺杂，得到由第二掺杂的单晶硅形成的所述第二导电层。
  5. 根据权利要求1至4中任一项所述的3D堆叠的半导体器件的制造方 法，其中，所述对每个所述膜层进行纵向刻蚀形成多个沿所述第二方向延伸并在所述第一方向间隔的多个柱包括：
    对每个所述膜层进行纵向刻蚀，在所述膜层中形成沿所述第二方向延伸并且沿第一方向间隔的多个第三沟槽，所述第三沟槽将所述膜层间隔为多个所述柱；
    所述制造方法还包括：
    在形成填充在相邻第一绝缘层之间的膜层之后，在将所述膜层间隔为多个所述柱之前，进行下述步骤：
    在所述膜层远离所述虚拟位线层的端部形成与该端部接触的电容器的第三电极，并在所述衬底上沉积覆盖所述第三电极和所述第二沟槽的第一绝缘层；
    刻蚀去除所述第一沟槽内的所述虚拟位线层，使所述第一沟槽露出所述膜层和所述第一绝缘层；
    以及，在将所述膜层间隔为多个所述柱之后，进行下述步骤：
    在所述衬底上沉积覆盖所述第三沟槽的第一绝缘层；
    对相邻两个所述第一沟槽之间的第一绝缘层进行刻蚀，露出所述第三电极，保留所述第一沟槽侧壁上的所述第一绝缘层；
    在露出的所述第三电极的表面依次沉积介电质层和第四电极，所述第三电极、所述介电质层和所述第四电极构成电容器。
  6. 根据权利要求5所述的3D堆叠的半导体器件的制造方法，其中，所述在所述膜层远离所述虚拟位线层的端部形成与该端部接触的电容器的第三电极包括：
    采用多晶硅或金属在所述衬底上沉积覆盖所述膜层的被所述第二沟槽露出的端部的第三导电层，形成第三电极；或者，
    采用选择性外延工艺在所述膜层的被所述第二沟槽露出的端部生长单晶硅，并在单晶硅的生长过程中采用原位掺杂法进行掺杂，得到由掺杂的单晶硅形成的第三导电层。
  7. 根据权利要求5所述的3D堆叠的半导体器件的制造方法，其中，所述在所述柱的半导体区域侧壁形成环绕型的栅极绝缘层和和栅电极包括：
    在得到所述电容器之后，刻蚀去除所述第一沟槽侧壁上的所述第一绝缘层，形成栅极槽；
    在所述栅极槽的内壁上沉积栅极绝缘层，以及在所述栅极槽中填充栅电极层；
    刻蚀去除沿所述第一方向分布的相邻两个所述半导体柱之间的部分所述栅电极层，仅保留该两个半导体柱侧壁上的所述栅电极层，得到栅电极。
  8. 根据权利要求5所述的3D堆叠的半导体器件的制造方法，还包括，在去除所述第一沟槽内的所述虚拟位线层之后，形成所述第三沟槽之前，进行下述步骤：
    对所述第一沟槽内两侧的所述膜层的第一导电区域进行回刻，形成延伸进入所述膜层的第一导电区域并且沿所述第一方向延伸的位线槽，在所述位线槽中沉积位线。
  9. 根据权利要求8所述的3D堆叠的半导体器件的制造方法，还包括，在去除所述第一沟槽内的所述虚拟位线层之后，形成所述位线槽之前，进行下述步骤：
    对所述第一沟槽两侧的所述第一绝缘层进行回刻，形成延伸进入所述第一绝缘层并且沿所述第一方向延伸的支撑槽，在所述支撑槽中沉积第二绝缘层形成支撑层。
  10. 根据权利要求8或9所述的3D堆叠的半导体器件的制造方法，还包括，在形成位线之后，形成所述第三沟槽之前，进行下述步骤：
    在所述第一沟槽中沉积第三绝缘层，所述第三绝缘层将位于同一个所述第一沟槽内的相邻两条位线间隔开。
  11. 一种3D堆叠的半导体器件，包括：
    分布于不同层、沿着垂直于衬底的方向堆叠且周期性分布的多个存储单元，每一层包括沿第一方向和第二方向阵列分布的多个存储单元；
    每个所述存储单元包括一个晶体管；所述晶体管包括沿所述第二方向延 伸的柱和环绕所述柱的侧壁的栅电极，所述柱依次包括第一导电区域、半导体区域和第二导电区域；
    其中，所述半导体区域包含所述柱的主体材料，所述第一导电区域包含第一掺杂材料，所述第二导电区域包含第二掺杂材料；所述第一掺杂材料在所述第一导电区域中均匀分布，所述第二掺杂材料在所述第二导电区域中均匀分布。
  12. 根据权利要求11所述的3D堆叠的半导体器件，其中，所述主体材料为单晶硅、单晶锗、单晶碳化硅或单晶砷化镓。
  13. 根据权利要求11所述的3D堆叠的半导体器件，其中，
    所述主体材料为单晶硅，所述主体材料中不含有锗元素；或者，
    所述主体材料为单晶锗，所述主体材料中不含有硅元素。
  14. 根据权利要求11所述的3D堆叠的半导体器件，还包括：
    沿所述第一方向延伸且在垂直于所述衬底的方向上间隔设置的多条位线，所述柱的第一导电区域与所述位线连接；和/或，
    沿垂直于所述衬底的方向延伸的多条字线，所述字线环绕所述柱的侧壁。
  15. 根据权利要求14所述的3D堆叠的半导体器件，其中，位于同一层且沿所述第一方向分布的多个存储单元的晶体管的所述柱与同一条位线连接，并且与同一条位线连接的相邻两个所述柱之间通过连接部相连接，并且所述柱与所述连接部为一体式结构。
  16. 根据权利要求15所述的3D堆叠的半导体器件，其中，与同一条位线连接的各所述柱的一端和所述连接部形成沿所述第一方向延伸的膜层，所述膜层与所述位线连接，并且所述膜层在所述衬底上的正投影与所述位线在所述衬底上的正投影相交叠。
  17. 根据权利要求14所述的3D堆叠的半导体器件，其中，所述字线的横截面在所述字线的延伸方向不同位置的外轮廓是相同的。
  18. 根据权利要求11至17中任一项所述的3D堆叠的半导体器件，其中，所述存储单元还包括电容器，所述电容器与所述柱的一端连接，所述电容器包括与所述柱的所述第二导电区域连接的第三电极、第四电极以及设置在所 述第三电极和所述第四电极之间的介电质层；其中，
    沿垂直于所述衬底的方向分布且在第二方向上间隔分布的两列存储单元的电容器的所述第四电极为共用电极；所述两列存储单元的晶体管和电容器镜像分布。
  19. 根据权利要求18所述的3D堆叠的半导体器件，其中，所述第三电极在所述柱的第二导电区域上采用外延工艺形成，所述第三电极的材料为单晶硅，所述第三电极与所述柱的第一导电区域、第二导电区域、半导体区域的截面相同。
  20. 一种电子设备，包括根据权利要求11至19中任一所述的3D堆叠的半导体器件。
PCT/CN2023/093997 2023-03-09 2023-05-12 3d堆叠的半导体器件及其制造方法、电子设备 Ceased WO2024183153A1 (zh)

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