WO2023035528A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2023035528A1
WO2023035528A1 PCT/CN2022/071594 CN2022071594W WO2023035528A1 WO 2023035528 A1 WO2023035528 A1 WO 2023035528A1 CN 2022071594 W CN2022071594 W CN 2022071594W WO 2023035528 A1 WO2023035528 A1 WO 2023035528A1
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layer
contact
dielectric
material layer
dielectric layer
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PCT/CN2022/071594
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English (en)
French (fr)
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郭帅
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长鑫存储技术有限公司
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Publication of WO2023035528A1 publication Critical patent/WO2023035528A1/zh
Priority to US18/195,309 priority Critical patent/US20230276617A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a semiconductor structure and a manufacturing method thereof.
  • Dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM) is a semiconductor memory commonly used in electronic equipment such as computers, which is composed of multiple storage units.
  • the storage unit includes: a storage capacitor, and a transistor electrically connected to the storage capacitor.
  • a transistor includes a gate, a source region and a drain region. The gate of the transistor is used to electrically connect with the word line.
  • the source area of the transistor is used to form a bit line contact area to be electrically connected to the bit line through the bit line contact structure.
  • the drain region of the transistor is used to form a storage node contact region to be electrically connected to the storage capacitor through the storage node contact structure.
  • Some embodiments of the present application provide a method for manufacturing a semiconductor structure, which includes the following steps.
  • a substrate is provided, and a shallow trench isolation structure is formed on the substrate.
  • the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate.
  • a plurality of transistor accommodating grooves are formed in the active area, and there is an interval between the transistor accommodating grooves and the shallow trench isolation structure.
  • a columnar structure is formed in the transistor accommodating groove.
  • the columnar structure includes a source, a conductive channel and a drain arranged in sequence along a direction away from the substrate. Etching removes the active area located in the space and the active area between the adjacent columnar structures located in the same active area, so as to form the bit line trench.
  • a bitline trench surrounds the source.
  • a bitline is formed in the bitline trench surrounding the contact source.
  • forming the columnar structure in the transistor accommodating groove includes the following steps.
  • the semiconductor material is filled in the transistor accommodating groove to form the source.
  • a semiconductor material is deposited on the substrate to form a semiconductor film covering the source. Pattern the semiconductor film to form the drain and conductive channel. Both the orthographic projection of the drain on the substrate and the orthographic projection of the conductive channel on the substrate overlap with the orthographic projection of the source on the substrate.
  • the etching removes the active region located in the spacer and the active region between adjacent columnar structures located in the same active region to form bit line trenches, including the following steps.
  • a first sacrificial layer covering the exposed surface of the column structure and the exposed surface of the substrate is formed.
  • the first sacrificial layer is patterned, and based on the pattern etching of the first sacrificial layer, the active area located in the interval and the active area located between adjacent columnar structures located in the same active area are removed.
  • the first sacrificial layer is removed.
  • the manufacturing method of the semiconductor structure before forming the bit line trench, further includes: forming a contact plug on the drain.
  • the manufacturing method of the semiconductor structure further includes the following steps.
  • a first dielectric material layer covering the bit line, the conductive channel, the drain and the contact plug is formed.
  • a surrounding gate word line corresponding to surrounding the conducting channel is formed on the surface of the first dielectric material layer away from the conducting channel.
  • a second dielectric material layer covering the wraparound gate word line is formed on the surface of the first dielectric material layer away from the contact plug. Etching the second dielectric material layer and the first dielectric material layer to obtain the first dielectric layer and the second dielectric layer. The first dielectric layer and the second dielectric layer expose the contact plugs.
  • forming a wrap-around gate word line corresponding to the conductive channel on the surface of the first dielectric material layer away from the conductive channel includes the following steps.
  • Metal material is deposited on the first layer of dielectric material. Etching the metal material until the upper surface of the metal material is flush with the upper surface of the columnar structure, or the upper surface of the metal material is lower than the upper surface of the columnar structure, to obtain a metal pattern layer.
  • a second sacrificial layer covering the exposed surface of the first dielectric material layer and the metal pattern layer is formed. The second sacrificial layer is patterned, and the metal pattern layer is etched based on the pattern of the second sacrificial layer to obtain surrounding gate word lines corresponding to surrounding conductive channels. The second sacrificial layer is removed.
  • the metallic material includes tungsten metal.
  • the manufacturing method of the semiconductor structure before etching the second dielectric material layer and the first dielectric material layer, the manufacturing method of the semiconductor structure further includes: forming a third dielectric material layer on the second dielectric material layer; A plurality of contact windows are formed in the layer to obtain a third dielectric layer.
  • etching the second dielectric material layer and the first dielectric material layer to obtain the first dielectric layer and the second dielectric layer, the first dielectric layer and the second dielectric layer exposing the contact plug includes: etching based on the contact window Etching the second dielectric material layer and the first dielectric material layer to obtain the first dielectric layer and the second dielectric layer, the first dielectric layer and the second dielectric layer expose the contact plugs.
  • the manufacturing method of the semiconductor structure further includes : A contact pad to be in contact with a contact plug is formed within the contact window.
  • forming a contact pad in contact with the contact plug within the contact window includes the following steps.
  • a pad material layer is formed in the contact window and on the surface of the third dielectric layer.
  • the pad material layer located on the surface of the third dielectric layer is removed by a chemical mechanical grinding process, and the pad material layer remaining in the contact window is the contact pad.
  • the material of the bit line and/or the contact plug includes bismuth metal.
  • the material of the columnar structures includes molybdenum disulfide.
  • the semiconductor structure includes a substrate, a transistor accommodating groove, a columnar structure and a bit line.
  • a shallow trench isolation structure is formed on the substrate, and the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate.
  • the transistor accommodating groove is located in the active area and has a space between the shallow trench isolation structure.
  • the columnar structure is located in the transistor accommodating groove, and the columnar structure includes: a source, a conductive channel and a drain arranged in sequence along a direction away from the substrate.
  • a bit line is located within the space and surrounds the contact source.
  • the material of the columnar structures includes molybdenum disulfide. And/or, the material of the bit line includes bismuth metal.
  • the semiconductor structure further includes: a contact plug, a first dielectric layer, a surrounding gate word line, and a second dielectric layer.
  • a contact plug is located on a surface of the drain facing away from the conductive channel.
  • the first dielectric layer covers the bit line and is located on the sidewalls of the conductive channel, the drain and the contact plug.
  • the surrounding gate word line is located on the surface of the first dielectric layer away from the conduction channel and surrounds the conduction channel.
  • the second dielectric layer is located on the surface of the first dielectric layer away from the contact plug, and covers the surrounding gate word line. There is an air gap between adjacent wraparound gate word lines.
  • the semiconductor structure further includes: a third dielectric layer and a contact pad.
  • the third dielectric layer has a contact window and at least covers the second dielectric layer.
  • the contact pad is located in the contact window and is in contact with the contact plug.
  • the material of the contact plug includes bismuth metal.
  • FIG. 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment
  • FIG. 2 is a flow chart of another method for preparing a semiconductor structure provided in an embodiment
  • FIG. 3 is a flowchart of another method for preparing a semiconductor structure provided in an embodiment
  • FIG. 4a is a schematic cross-sectional view of the structure obtained in step S100 along a first direction provided in an embodiment; wherein, the first direction is the extending direction of the wraparound gate word line;
  • 4b is a schematic cross-sectional view of the structure obtained in step S100 along the second direction provided in an embodiment; wherein, the second direction is the extending direction of the bit line;
  • FIG. 5a is a schematic cross-sectional view of the structure obtained in step S200 along the first direction provided in an embodiment
  • FIG. 5b is a schematic cross-sectional view of the structure obtained in step S200 along the second direction provided in an embodiment
  • FIG. 6 is a flowchart of step S300 provided in an embodiment
  • Fig. 7a is a schematic cross-sectional view of the structure obtained in step S301 along the first direction provided in an embodiment
  • Fig. 7b is a schematic cross-sectional view of the structure obtained in step S301 along the second direction provided in an embodiment
  • Fig. 8a is a schematic cross-sectional view of the structure obtained in step S302 along the first direction provided in an embodiment
  • Fig. 8b is a schematic cross-sectional view of the structure obtained in step S302 along the second direction provided in an embodiment
  • Fig. 9a is a schematic cross-sectional view along a first direction of a structure obtained after forming a contact plug material layer provided in an embodiment
  • Fig. 9b is a schematic cross-sectional view of the structure obtained after forming the contact plug material layer according to an embodiment along the second direction;
  • Fig. 10a is a schematic cross-sectional view of the structure obtained in step S303 along the first direction provided in an embodiment
  • Fig. 10b is a schematic cross-sectional view of the structure obtained in step S303 along the second direction provided in an embodiment
  • FIG. 11 is a flowchart of step S400 provided in an embodiment
  • Fig. 12a is a schematic cross-sectional view of the structure obtained in step S401 along the first direction provided in an embodiment
  • Fig. 12b is a schematic cross-sectional view of the structure obtained in step S401 along the second direction provided in an embodiment
  • Fig. 13a is a schematic cross-sectional view of the structure obtained in step S402 along the first direction provided in an embodiment
  • Fig. 13b is a schematic cross-sectional view of the structure obtained in step S402 along the second direction provided in an embodiment
  • Fig. 14a is a schematic cross-sectional view of the structure obtained in step S501 along the first direction provided in an embodiment
  • Fig. 14b is a schematic cross-sectional view of the structure obtained in step S501 along the second direction provided in an embodiment
  • Fig. 15a is a schematic cross-sectional view of the structure obtained in step S502 along the first direction provided in an embodiment
  • Fig. 15b is a schematic cross-sectional view of the structure obtained in step S502 along the second direction provided in an embodiment
  • Fig. 16a is a schematic cross-sectional view of the structure obtained in step S403 along the first direction provided in an embodiment
  • Fig. 16b is a schematic cross-sectional view of the structure obtained in step S403 along the second direction provided in an embodiment
  • Fig. 17a is a schematic cross-sectional view of the structure obtained in step S600 along the first direction provided in an embodiment
  • Fig. 17b is a schematic cross-sectional view of the structure obtained in step S600 along the second direction provided in an embodiment
  • FIG. 18 is a flowchart of step S700 provided in an embodiment
  • Fig. 19a is a schematic cross-sectional view of the structure obtained in step S701 along the first direction provided in an embodiment
  • Fig. 19b is a schematic cross-sectional view of the structure obtained in step S701 along the second direction provided in an embodiment
  • Fig. 20a is a schematic cross-sectional view of the structure obtained in step S702 along the first direction provided in an embodiment
  • Fig. 20b is a schematic cross-sectional view of the structure obtained in step S702 along the second direction provided in an embodiment
  • Fig. 21a is a schematic cross-sectional view of the structure obtained in step S703 along the first direction provided in an embodiment
  • Fig. 21b is a schematic cross-sectional view of the structure obtained in step S703 along the second direction provided in an embodiment
  • Fig. 22a is a schematic cross-sectional view of the structure obtained in step S704 along the first direction provided in an embodiment
  • Fig. 22b is a schematic cross-sectional view of the structure obtained in step S704 along the second direction provided in an embodiment
  • Fig. 23a is a schematic cross-sectional view of the structure obtained in step S705 along the first direction provided in an embodiment
  • Fig. 23b is a schematic cross-sectional view of the structure obtained in step S705 along the second direction provided in an embodiment
  • Fig. 24a is a schematic cross-sectional view of the structure obtained in step S800 along the first direction provided in an embodiment
  • Fig. 24b is a schematic cross-sectional view of the structure obtained in step S800 along the second direction provided in an embodiment
  • Fig. 25a is a schematic cross-sectional view of the structure obtained in step S850 along the first direction provided in an embodiment
  • Fig. 25b is a schematic cross-sectional view of the structure obtained in step S850 along the second direction provided in an embodiment
  • Fig. 26a is a schematic cross-sectional view of the structure obtained in step S860 along the first direction provided in an embodiment
  • Fig. 26b is a schematic cross-sectional view of the structure obtained in step S860 along the second direction provided in an embodiment
  • Fig. 27a is a schematic cross-sectional view of the structure obtained in step S900 along the first direction provided in an embodiment
  • Fig. 27b is a schematic cross-sectional view of the structure obtained in step S900 along the second direction provided in an embodiment
  • FIG. 28 is a flowchart of step S1000 provided in an embodiment
  • Fig. 29a is a schematic cross-sectional view along the first direction of the structure obtained in step S1001 provided in an embodiment
  • Fig. 29b is a schematic cross-sectional view of the structure obtained in step S1001 along the second direction provided in an embodiment
  • FIG. 30a is a schematic cross-sectional view of the structure obtained in step S1002 provided in an embodiment along the first direction; and FIG. 30a is also a schematic cross-sectional view of the semiconductor structure provided in an embodiment along the first direction;
  • FIG. 30b is a schematic cross-sectional view of the structure obtained in step S1002 along the second direction provided in an embodiment; and FIG. 30b is also a schematic cross-sectional view of the semiconductor structure provided in an embodiment along the second direction;
  • Fig. 31 is a schematic cross-sectional view of GAA provided in an embodiment.
  • first, second, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
  • Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention such that variations in the shapes shown as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • embodiments of the invention should not be limited to the particular shapes of regions shown herein but are to include deviations in shapes that result, for example, from manufacturing techniques.
  • the regions shown in the figures are schematic in nature and their shapes do not indicate the actual shape of a region of a device and are not intended to limit the scope of the invention.
  • the Gate All Around transistor (GAA transistor for short) has more advantages in terms of scalability, high performance and low power consumption, and is considered to be the key core technology of the next generation of integrated circuits.
  • the transistor Taking the vertical surround gate transistor as an example, the transistor has more integration freedom in the vertical direction, which can effectively reduce the plane area occupied by it, and it is also easier to achieve vertical stacking between multi-layer devices, and through a new Wiring methods to further increase the integration density.
  • MIGS Metal-Induced Gap States
  • some embodiments of the present application provide a method for fabricating a semiconductor structure, which includes the following steps.
  • the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate.
  • the columnar structure includes a source, a conductive channel and a drain arranged in sequence along a direction away from the substrate.
  • bitline trench surrounds the source.
  • a transistor accommodating groove is provided in the active region isolated by the shallow trench isolation structure, and there is a gap between the transistor accommodating groove and the shallow trench isolation structure.
  • the columnar structure can be formed in the transistor accommodation groove first, and then the active area located in the aforementioned interval and the active area between the adjacent columnar structures in the same active area can be removed to obtain the bit line trench.
  • the bit line surrounds the source electrode, which can make the contact area between the bit line and the source electrode larger, thereby reducing the contact resistance between the bit line and the source electrode. That is, the contact resistance between the bit line and the transistor to improve the electrical performance of the semiconductor structure.
  • the preparation method in the embodiment of the present application is easy to operate, which is beneficial to the large-scale production of semiconductor structures.
  • the material of the pillar structures includes molybdenum disulfide (MoS 2 ), and the material of the bit lines includes bismuth (Bi) metal.
  • MoS 2 molybdenum disulfide
  • Bi bismuth
  • the two-dimensional crystal structure of the columnar structure is not easily damaged due to its contact with the bit line, and the contact resistance between the bit line and the transistor can be further reduced to ensure that the transistor has better low power consumption performance and high frequency performance. Therefore, the electrical performance of the semiconductor structure is further improved.
  • the material of the columnar structure can also be other two-dimensional semiconductor materials, and the material of the bit line can also be other materials that are not easy to form an alloy with the two-dimensional semiconductor material to destroy the two-dimensional crystal structure.
  • the material of the columnar structure is: molybdenum selenide (MoSe 2 ), tungsten disulfide (WS 2 ), tungsten diselenide (WSe 2 ) or bismuth selenide (Bi 2 Se 3 ).
  • the material of the bit line is: chromium (Cr), cadmium (Cd), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te) or tungsten (W).
  • the method for manufacturing the semiconductor structure before performing S400 , that is, forming bit line trenches, the method for manufacturing the semiconductor structure further includes: forming a contact plug on the drain.
  • step S300 further includes: forming contact plugs on the pillar structures.
  • the material of the contact plug includes bismuth (Bi) metal.
  • the material of the contact plug may also be: chromium (Cr), cadmium (Cd), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te) or tungsten (W). This ensures that there is also a low contact resistance between the contact plug and the transistor.
  • the manufacturing method of the semiconductor structure further includes the following steps.
  • an air gap is provided between adjacent surrounding gate word lines, and the gate word lines can be effectively isolated by using the air gap, so as to ensure the electrical performance of the semiconductor structure.
  • the method for manufacturing the semiconductor structure before performing step S900 , that is, etching the second dielectric material layer and the first dielectric material layer, the method for manufacturing the semiconductor structure further includes the following steps.
  • step S900 the second dielectric material layer and the first dielectric material layer are etched to obtain the first dielectric layer and the second dielectric layer, and the first dielectric layer and the second dielectric layer expose the contact plug, including: The second dielectric material layer and the first dielectric material layer are etched based on the contact window to obtain the first dielectric layer and the second dielectric layer, and the first dielectric layer and the second dielectric layer expose the contact plug.
  • the semiconductor structure is prepared.
  • the method also includes the following steps.
  • the contact pad is formed in contact with the contact plug in the contact window.
  • the structure of the contact pad can be selected and set according to actual requirements.
  • the contact pads are metal pads, such as tungsten pads. Thereby, a lower resistance value of the contact pad and higher stability can be ensured.
  • the contact plug and the contact pad can jointly form a storage node contact structure, and are used to contact the storage capacitor to form a storage unit. This embodiment of the present application does not limit this.
  • step S100 referring to S100 in FIGS. 1 to 3 and FIGS. 4 a and 4 b , a substrate 1 is provided, and a shallow trench isolation structure 11 is formed on the substrate 1 .
  • the shallow trench isolation structure 11 isolates a plurality of active regions arranged at intervals in the substrate 1 .
  • the substrate 1 includes but not limited to a silicon substrate or a silicon-based substrate.
  • the substrate 1 is a sapphire substrate, a silicon substrate or a silicon carbide substrate.
  • the material of the active region is, for example, polysilicon (poly).
  • the shallow trench isolation structure 11 is, for example, a silicon oxide (SiO 2 ) isolation structure.
  • the arrangement of the active regions can be understood according to related technologies, which is not limited in the embodiments of the present application.
  • step S200 please refer to S200 in FIGS. There is an interval L.
  • the shape and size of the transistor accommodating groove 12 and the size of the interval L can be selected and set according to actual needs, which is not limited in this embodiment of the present application.
  • the transistor accommodating groove 12 is, for example, a columnar groove.
  • step S300 referring to FIG. 1 , FIG. 2 , FIG. 3 and FIG. 6 , execute S300 , that is, form a columnar structure in the transistor accommodating groove, including the following steps.
  • step S301 referring to S301 in FIG. 4 and FIG. 7 a , FIG. 7 b , semiconductor material is filled in the transistor accommodating groove 12 to form the source 21 .
  • the semiconductor material is a two-dimensional semiconductor material, such as a transition metal dichalcogenide.
  • the semiconductor material is molybdenum disulfide (MoS 2 ), molybdenum selenide (MoSe 2 ), tungsten disulfide (WS 2 ), tungsten diselenide (WSe 2 ), or bismuth selenide (Bi 2 Se 3 ).
  • step S302 referring to S302 in FIG. 4 and FIG. 8 a , FIG. 8 b , a semiconductor material is deposited on the substrate 1 to form a semiconductor thin film 20 covering the source 21 .
  • the semiconductor material used to form the semiconductor thin film 20 may be the same as the semiconductor material used to form the source electrode 21 in S301 , so as to ensure that the semiconductor thin film 20 can be well bonded to the source electrode 21 .
  • the thickness of the semiconductor thin film 20 can be determined according to the height of the columnar structure to be formed later.
  • the semiconductor material deposition process includes, but is not limited to, physical vapor deposition (Physical Vapor Deposition, PVD for short), chemical vapor deposition (Chemical Vapor Deposition, CVD for short), or atomic layer deposition (Atomic Layer Deposition, ALD for short).
  • the manufacturing method of the semiconductor structure further includes: depositing a contact plug material layer 30 on the semiconductor thin film 20 .
  • the contact plug material layer 30 includes a bismuth metal layer.
  • the material of the contact plug material layer 30 may also be chromium (Cr), cadmium (Cd), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te) or tungsten (W) etc.
  • the deposition process of the contact plug material layer 30 includes but is not limited to physical vapor deposition (Physical Vapor Deposition, PVD for short), chemical vapor deposition (Chemical Vapor Deposition, CVD for short) or atomic layer deposition (Atomic Layer Deposition, Abbreviated as ALD).
  • PVD Physical Vapor Deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • step S303 referring to S303 in FIG. 4 and FIG. 10 a , FIG. 10 b , the semiconductor film 20 is patterned to form the drain 23 and the conductive channel 22 . Both the orthographic projection of the drain 23 on the substrate 1 and the orthographic projection of the conductive channel 22 on the substrate 1 overlap with the orthographic projection of the source 21 on the substrate 1 . In this way, the drain electrode 23 , the conductive channel 22 and the source electrode 21 are arranged in a columnar shape, forming the columnar structure 2 together.
  • the source electrode 21 and the drain electrode 23 can be obtained by ion implantation of semiconductor material, which is not specifically described in this embodiment of the present application.
  • the contact plug material layer 30 is formed on the semiconductor film 20, after the semiconductor film 20 is patterned, the contact plug material layer 30 can also be patterned synchronously to form the contact plug 3 on the columnar structure 2, such as shown in Figures 10a and 10b.
  • step S400 please refer to FIG. 1, FIG. 2, FIG. 3 and FIG. 11, perform S400, that is, etch and remove the active region located in the spacer and the active region between adjacent columnar structures located in the same active region , to form bit line trenches, including the following steps.
  • step S401 referring to S401 in FIG. 11 and FIG. 12 a , FIG. 12 b , a first sacrificial layer 40 covering the exposed surface of the columnar structure 2 and the exposed surface of the substrate 1 is formed.
  • the first sacrificial layer 40 is formed using a deposition process.
  • the material of the first sacrificial layer 40 is, for example, silicon nitride.
  • step S402 referring to S402 in FIG. 11 and FIG. 13a and FIG. 13b, the first sacrificial layer 40 is patterned, and based on the pattern etching of the first sacrificial layer 40, the active region located in the interval L and the Active regions between adjacent columnar structures 2 in the same active region to form bit line trenches 41 .
  • the bit line trench 41 surrounds the source 21 .
  • the process of patterning the first sacrificial layer 40 is, for example, a wet etching process.
  • the etching of the active region to be removed may be based on the pattern of the first sacrificial layer 40, using a self-aligned double patterning (Self-Aligned Double Patterning, referred to as SADP) process or a self-aligned quadruple patterning (Self-Aligned Quadruple Patterning, referred to as SAQP) process implementation.
  • SADP Self-Aligned Double Patterning
  • SAQP Self-Aligned Quadruple Patterning
  • step S403 may be executed after step S500 is executed, and this embodiment of the present application takes this as an example as follows.
  • step S500 referring to FIG. 14 a , FIG. 14 b , FIG. 15 a and FIG. 15 b , a bit line 5 surrounding and contacting the source 21 is formed in the bit line trench 41 , including the following steps.
  • bit line material layer 50 that fills up the bit line trench 41 and covers the exposed surface of the first sacrificial layer 40 .
  • bit line material layer 50 includes a bismuth metal layer.
  • S502 please refer to FIG. 15 a and FIG. 15 b , pattern the bit line material layer 50 to form the bit line 5 located in the bit line trench 41 and surrounding the contact source 21 .
  • the patterning of the bit line material layer 50 can be based on the pattern of the first sacrificial layer 40, using a self-aligned double patterning (Self-Aligned Double Patterning, referred to as SADP) process or a self-aligned quadruple patterning (Self-Aligned Quadruple Patterning, referred to as SAQP) process implementation.
  • SADP Self-Aligned Double Patterning
  • SAQP Self-Aligned Quadruple Patterning
  • step S403 referring to S403 in FIG. 11 and FIG. 16a, FIG. 16b, the first sacrificial layer 40 is removed.
  • step S600 referring to FIG. 2 , FIG. 3 and FIG. 17 a , FIG. 17 b , a first dielectric material layer 610 covering the bit line 5 , the conductive channel 22 , the drain 23 and the contact plug 3 is formed.
  • step S700 please refer to FIG. 2, FIG. 3 and FIG. 18, and execute S700, that is, form a surrounding gate word line corresponding to surrounding the conductive channel on the surface of the first dielectric material layer away from the conductive channel, including the steps as follows.
  • step S701 referring to S701 in FIG. 18 and FIGS. 19 a and 19 b , a metal material 70 is deposited on the first dielectric material layer 610 .
  • metallic material 70 includes tungsten metal.
  • the metal material 70 is other metal materials with good electrical conductivity, such as molybdenum (Mo), aluminum (Al), or titanium (Ti).
  • step S702 referring to S702 in FIG. 18 and FIG. 20a and FIG. 20b, the metal material 70 is etched until the upper surface of the metal material 70 is flush with the upper surface of the columnar structure 2, or the upper surface of the metal material 70 is lower. On the upper surface of the columnar structure 2, a metal pattern layer 71 is obtained.
  • step S703 referring to S703 in FIG. 18 and FIG. 21 a , FIG. 21 b , a second sacrificial layer 80 covering the exposed surface of the first dielectric material layer 610 and the metal pattern layer 71 is formed.
  • the second sacrificial layer 80 is formed by a spin coating process.
  • the second sacrificial layer 80 is, for example, a photoresist layer.
  • step S704 referring to S704 in FIG. 18 and FIG. 22a and FIG. 22b, the second sacrificial layer 80 is patterned, and the metal pattern layer 71 is etched based on the pattern of the second sacrificial layer 80 to obtain a corresponding surrounding conductive channel. 22 Wrap-around Gate Word Line 7. There is an air gap G between adjacent surrounding gate word lines 7 .
  • the process of patterning the second sacrificial layer 80 is, for example, a wet etching process.
  • step S705 please refer to S705 in FIG. 18 and FIG. 23a, FIG. 23b, the second sacrificial layer 80 is removed.
  • step S800 referring to FIG. 2, FIG. 3 and FIG. 24a, FIG. 24b, a second dielectric material layer covering the surrounding gate word line 7 is formed on the surface of the first dielectric material layer 610 facing away from the contact plug 3 620.
  • the material of the second dielectric material layer 620 may be the same as that of the first dielectric material layer 610 , for example, both are silicon oxide. Therefore, it is convenient to etch through a subsequent patterning process.
  • the second dielectric material layer 620 can be formed by a deposition process.
  • step S850 referring to FIG. 3 and FIG. 25 a , FIG. 25 b , a third dielectric material layer 630 is formed on the second dielectric material layer 620 .
  • the material of the third dielectric material layer 630 may be different from that of the second dielectric material layer 620 , for example, the material of the third dielectric material layer 630 is silicon nitride.
  • the third dielectric material layer 630 can be formed by a deposition process, and the deposition thickness of the third dielectric material layer 630 can be selectively set according to the height and dimension of the contact pad to be formed later.
  • step S860 referring to FIG. 3 and FIG. 26 a , FIG. 26 b , a plurality of contact windows K are formed in the third dielectric material layer 630 to obtain a third dielectric layer 63 .
  • the contact window K is used to accommodate the contact pads, and the shape and distribution of the contact window K can be determined according to the shape and distribution of the contact pads to be formed later.
  • step S900 referring to FIG. 3 and FIG. 27a, FIG. 27b, based on the contact window K, the second dielectric material layer 620 and the first dielectric material layer 610 are etched to obtain the first dielectric layer 61 and the second dielectric layer 62 .
  • the first dielectric layer 61 and the second dielectric layer 62 expose the contact plug 3 .
  • step S1000 referring to FIG. 3 and FIG. 28 , executing S1000 , that is, forming a contact pad in contact with a contact plug in the contact window includes the following steps.
  • step S1002 please refer to S1002 in FIG. 28 and FIG. 30a, FIG. 30b, the pad material layer 90 located on the surface of the third dielectric layer 63 is removed by chemical mechanical polishing process, and the pad material layer remaining in the contact window K That is, the contact pad 9 .
  • the chemical mechanical grinding process is used to form the contact pad 9, which can ensure that the surface of the contact pad 9 is flat, so as to facilitate the subsequent formation of other electrical devices such as storage capacitors on the surface of the contact pad 9, and ensure that the contact pad 9 is flat. 9 can be in good contact with electrical devices, thereby ensuring the electrical contact performance of the contact pad 9 .
  • Some embodiments of the present application also provide a semiconductor structure, which is prepared by using the preparation method in some of the above embodiments.
  • the semiconductor structure includes a substrate 1 , a transistor accommodating groove 12 , a columnar structure 2 and a bit line 5 .
  • a shallow trench isolation structure 11 is formed on the substrate 1 , and the shallow trench isolation structure 11 isolates a plurality of active regions arranged at intervals in the substrate 1 .
  • the transistor accommodating groove 12 is located in the active region, and has a distance from the shallow trench isolation structure 11 .
  • the columnar structure 2 is located in the transistor accommodating groove 12 , and the columnar structure 2 includes: a source 21 , a conductive channel 22 and a drain 23 arranged in sequence along a direction away from the substrate 1 .
  • the bit line 5 is located in the interval L and surrounds the contact source 21 .
  • the substrate 1 includes but not limited to a silicon substrate or a silicon-based substrate.
  • the substrate 1 is a sapphire substrate, a silicon substrate or a silicon carbide substrate.
  • the material of the active region is, for example, polysilicon (poly).
  • the shallow trench isolation structure 11 is, for example, a silicon oxide (SiO 2 ) isolation structure.
  • the material of the columnar structure 2 includes molybdenum disulfide.
  • the material of the bit line 5 includes bismuth metal.
  • the material of the columnar structure can also be other two-dimensional semiconductor materials, and the material of the bit line can also be other materials that are not easy to form an alloy with the two-dimensional semiconductor material to destroy the two-dimensional crystal structure.
  • the material of the columnar structure is: molybdenum selenide (MoSe 2 ), tungsten disulfide (WS 2 ), tungsten diselenide (WSe 2 ) or bismuth selenide (Bi 2 Se 3 ).
  • the material of the bit line is: chromium (Cr), cadmium (Cd), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te) or tungsten (W).
  • the material of the pillar structure 2 includes molybdenum disulfide (MoS 2 ), and the material of the bit line 5 includes bismuth (Bi) metal.
  • MoS 2 molybdenum disulfide
  • Bi bismuth
  • the two-dimensional crystal structure of the columnar structure 2 is not easily damaged due to its contact with the bit line 5, and the contact resistance between the bit line 5 and the GAA transistor can be further reduced to ensure that the GAA transistor has better low power consumption performance. and high-frequency performance, thereby further improving the electrical performance of the semiconductor structure.
  • the semiconductor structure further includes: a contact plug 3 , a first dielectric layer 61 , a surrounding gate word line 7 and a second dielectric layer 62 .
  • the contact plug 3 is located on the surface of the drain 23 facing away from the conductive channel 22 .
  • the first dielectric layer 61 covers the bit line 5 and is located on the sidewalls of the conductive channel 22 , the drain 23 and the contact plug 3 .
  • the surrounding gate word line 7 is located on the surface of the first dielectric layer 61 away from the conductive channel 22 and surrounds the conductive channel 22 .
  • the second dielectric layer 62 is located on the surface of the first dielectric layer 61 away from the contact plug 3 and covers the surrounding gate word line 7 . There is an air gap G between adjacent surrounding gate word lines 7 .
  • the material of the contact plug 3 includes bismuth (Bi) metal.
  • the material of the contact plug 3 may also be: chromium (Cr), cadmium (Cd), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te) or tungsten (W). This ensures that there is also a low contact resistance between the contact plug and the transistor.
  • the first dielectric layer 61 is an oxide layer with a high dielectric constant, such as a silicon oxide layer.
  • the material of the second dielectric layer 62 may be the same as that of the first dielectric layer 61 .
  • the material of the wraparound gate word line 7 is tungsten (W), molybdenum (Mo), aluminum (Al), or titanium (Ti).
  • the semiconductor structure further includes: a third dielectric layer 63 and a contact pad 9 .
  • the third dielectric layer 63 has a contact window K and at least covers the second dielectric layer 62 .
  • the contact pad 9 is located in the contact window K and is in contact with the contact plug 3 .
  • the material of the third dielectric layer 63 may be different from that of the second dielectric layer 62 , for example, the material of the third dielectric layer 63 is silicon nitride.
  • the contact pads 9 are tungsten pads.

Abstract

本申请涉及一种半导体结构及其制备方法。所述半导体结构的制备方法包括：提供衬底，衬底上形成有浅沟槽隔离结构；在有源区内形成多个晶体管容置槽，晶体管容置槽与浅沟槽隔离结构之间具有间隔；在晶体管容置槽内形成柱状结构，柱状结构包括沿远离衬底的方向依次设置的源极、导电沟道和漏极；刻蚀去除位于前述间隔内的有源区及位于同一有源区内的相邻柱状结构之间的有源区，以形成位线沟槽，位线沟槽环绕源极；在位线沟槽内形成环绕接触源极的位线。

Description

半导体结构及其制备方法
相关申请的交叉引用
本申请要求于2021年09月07日提交中国专利局、申请号为202111044659.3、发明名称为“半导体结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体集成电路制造技术领域，特别是涉及一种半导体结构及其制备方法。
技术背景
动态随机存储器(Dynamic Random Access Memory，简称DRAM)是计算机等电子设备中常用的半导体存储器，其由多个存储单元构成。其中，存储单元包括：存储电容器、以及与存储电容器电连接的晶体管。晶体管包括栅极、源区和漏区。晶体管的栅极用于与字线电连接。晶体管的源区用于构成位线接触区，以通过位线接触结构与位线电连接。晶体管的漏区用于构成存储节点接触区，以通过存储节点接触结构与存储电容器电连接。
然而，随着DRAM的尺寸越来越小，晶体管采用垂直型环绕式栅极晶体管(Vertical Gate All Around transistor，简称VGAA transistor)可以有效缩减DRAM的尺寸，但也容易在线宽尺寸不断缩小的情况下，使得金属材料与半导体材料的接触因肖特基势垒以及金属-诱导-间隙态(Metal-Induced Gap States，简称MIGS)而具有过大的接触电阻，从而导致晶体管的输出电流难以满足DRAM的工作需求，对DRAM的电学性能造成不良影响。
发明内容
根据本申请的示意性实施例，提供了一种半导体结构及其制备方法。
本申请一些实施例提供了一种半导体结构的制备方法，其包括的步骤如下。
提供衬底，衬底上形成有浅沟槽隔离结构。浅沟槽隔离结构在衬底内隔离出多个间隔排布的有源区。在有源区内形成多个晶体管容置槽，晶体管容置槽与浅沟槽隔离结构之间具有间隔。在晶体管容置槽内形成柱状结构。柱状结构包括沿远离衬底的方向依次设置的源极、导电沟道和漏极。刻蚀去除位于前述间隔内的有源区及位于同一有源区内的相邻柱状结构之间的有源区，以形成位线沟槽。位线沟槽环绕源极。在位线沟槽内形成环绕接触源极的位线。
在一些实施例中，在晶体管容置槽内形成柱状结构，包括步骤如下。
在晶体管容置槽内填充半导体材料，形成源极。在衬底上沉积半导体材料，形成覆盖源极的半导体薄膜。将半导体薄膜图形化，形成漏极和导电沟道。漏极在衬底上的正投影和导电沟道在衬底上的正投影均与源极在衬底上的正投影重叠。
在一些实施例中，刻蚀去除位于间隔内的有源区及位于同一有源区内的相邻柱状结构之间的有源区，以形成位线沟槽，包括步骤如下。
形成覆盖柱状结构裸露表面和衬底裸露表面的第一牺牲层。将第一牺牲层图形化，并基于第一牺牲层的图形刻蚀去除位于间隔内的有源区及位于同一有源区内的相邻柱状结构之间的有源区。去除第一牺牲层。
在一些实施例中，在形成位线沟槽之前，半导体结构的制备方法还包括：在漏极上形成接触插塞。
相应的，在位线沟槽内形成环绕接触源极的位线之后，半导体结构的制备方法还包括如下步骤。
形成覆盖位线、导电沟道、漏极和接触插塞的第一介质材料层。在第一介质材料层的背离导电沟道的表面上形成对应环绕导电沟道的环绕式栅极字线。相邻的环绕式栅极字线之间具有气隙。在第一介质材料层的背离接触插塞的表面上形成覆盖环绕式栅极字线的第二介质材料层。刻蚀第二介质材料层和第一介质材料层，以得到第一介质层及第二介质层。第一介质层和第二介质层暴露出接触插塞。
在一些实施例中，在第一介质材料层的背离导电沟道的表面上形成对应环绕导电沟道的环绕式栅极字线，包括步骤如下。
在第一介质材料层上沉积金属材料。刻蚀金属材料，直至金属材料的上表面与柱状结构的上表面平齐，或金属材料的上表面低于柱状结构的上表面，获得金属图案层。形成覆盖第一介质材料层裸露表面和金属图案层的第二牺牲层。将第二牺牲层图形化，并基于第二牺牲层的图形刻蚀金属图案层，获得对应环绕导电沟道的环绕式栅极字线。去除第二牺牲层。
在一些实施例中，金属材料包括钨金属。
在一些实施例中，在刻蚀第二介质材料层和第一介质材料层之前，半导体结构的制备方法还包括：在第二介质材料层上形成第三介质材料层；并在第三介质材料层中形成多个接触窗口，以得到第三介质层。
相应的，刻蚀第二介质材料层和第一介质材料层，以得到第一介质层及第二介质层，第一介质层和第二介质层暴露出接触插塞，包括：基于接触窗口刻蚀第二介质材料层和第一介质材料层，以得到第一介质层及第二介质层，第一介质层和所述第二介质层暴露出接触插塞。
在刻蚀第二介质材料层和第一介质材料层，以得到第一介质层及第二介质层，第一介质层和第二介质层暴露出接触插塞之后，半导体结构的制备方法还包括：在接触窗口内形成与接触插塞接触的接触焊盘。
在一些实施例中，在接触窗口内形成与接触插塞接触的接触焊盘包括步骤如下。
在接触窗口内及第三介质层的表面形成焊盘材料层。采用化学机械研磨工艺去除位于第三介质层表面的焊盘材料层，保留于接触窗口内的焊盘材料层即为接触焊盘。
在一些实施例中，位线和/或接触插塞的材料包括铋金属。
在一些实施例中，柱状结构的材料包括二硫化钼。
本申请一些实施例还提供了一种半导体结构，采用如上一些实施例中的制备方法制备获得。半导体结构包括衬底、晶体管容置槽、柱状结构以及位线。衬底上形成有浅沟槽隔离结构，浅沟槽隔离结构在衬底内隔离出多个间隔排布的有源区。晶体管容置槽位于有源区内，且与浅沟槽隔离结构之间具有间隔。柱状结构位于晶体管容置槽内，柱状结构包括：沿远离衬底的方向依次设置的源极、导电沟道和漏极。位线位于所述间隔内，且环绕接触源极。
在一些实施例中，柱状结构的材料包括二硫化钼。和/或，位线的材料包括铋金属。
在一些实施例中，半导体结构还包括：接触插塞、第一介质层、环绕式栅极字线和第二介质层。接触插塞位于漏极的背离导电沟道的表面。第一介质层覆盖位线，且位于导电沟道、漏极和接触插塞的侧壁。环绕式栅极字线位于第一介质层的背离导电沟道的表面，且环绕导电沟道。第二介质层位于第一介质层的背离接触插塞的表面，且覆盖环绕式栅极字线。相邻的环绕式栅极字线之间具有气隙。
在一些实施例中，半导体结构还包括：第三介质层和接触焊盘。第三介质层具有接触窗口，且至少覆盖第二介质层。接触焊盘位于接触窗口内，并与接触插塞接触。在一些实施例中，接触插塞的材料包括铋金属。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中提供的一种半导体结构的制备方法的流程图；
图2为一实施例中提供的另一种半导体结构的制备方法的流程图；
图3为一实施例中提供的又一种半导体结构的制备方法的流程图；
图4a为一实施例中提供的步骤S100中所得结构沿第一方向的剖面示意图；其中，第一方向为环绕式栅极字线的延伸方向；
图4b为一实施例中提供的步骤S100中所得结构沿第二方向的剖面示意图；其中，第二方向为位线的延伸方向；
图5a为一实施例中提供的步骤S200中所得结构沿第一方向的剖面示意图；
图5b为一实施例中提供的步骤S200中所得结构沿第二方向的剖面示意图；
图6为一实施例中提供的步骤S300的流程图；
图7a为一实施例中提供的步骤S301中所得结构沿第一方向的剖面示意图；
图7b为一实施例中提供的步骤S301中所得结构沿第二方向的剖面示意图；
图8a为一实施例中提供的步骤S302中所得结构沿第一方向的剖面示意图；
图8b为一实施例中提供的步骤S302中所得结构沿第二方向的剖面示意图；
图9a为一实施例中提供的形成接触插塞材料层后所得结构沿第一方向的剖面示意图；
图9b为一实施例中提供的形成接触插塞材料层后所得结构沿第二方向的剖面示意图；
图10a为一实施例中提供的步骤S303中所得结构沿第一方向的剖面示意图；
图10b为一实施例中提供的步骤S303中所得结构沿第二方向的剖面示意图；
图11为一实施例中提供的步骤S400的流程图；
图12a为一实施例中提供的步骤S401中所得结构沿第一方向的剖面示意图；
图12b为一实施例中提供的步骤S401中所得结构沿第二方向的剖面示意图；
图13a为一实施例中提供的步骤S402中所得结构沿第一方向的剖面示意图；
图13b为一实施例中提供的步骤S402中所得结构沿第二方向的剖面示意图；
图14a为一实施例中提供的步骤S501中所得结构沿第一方向的剖面示意图；
图14b为一实施例中提供的步骤S501中所得结构沿第二方向的剖面示意图；
图15a为一实施例中提供的步骤S502中所得结构沿第一方向的剖面示意图；
图15b为一实施例中提供的步骤S502中所得结构沿第二方向的剖面示意图；
图16a为一实施例中提供的步骤S403中所得结构沿第一方向的剖面示意图；
图16b为一实施例中提供的步骤S403中所得结构沿第二方向的剖面示意图；
图17a为一实施例中提供的步骤S600中所得结构沿第一方向的剖面示意图；
图17b为一实施例中提供的步骤S600中所得结构沿第二方向的剖面示意图；
图18为一实施例中提供的步骤S700的流程图；
图19a为一实施例中提供的步骤S701中所得结构沿第一方向的剖面示意图；
图19b为一实施例中提供的步骤S701中所得结构沿第二方向的剖面示意图；
图20a为一实施例中提供的步骤S702中所得结构沿第一方向的剖面示意图；
图20b为一实施例中提供的步骤S702中所得结构沿第二方向的剖面示意图；
图21a为一实施例中提供的步骤S703中所得结构沿第一方向的剖面示意图；
图21b为一实施例中提供的步骤S703中所得结构沿第二方向的剖面示意图；
图22a为一实施例中提供的步骤S704中所得结构沿第一方向的剖面示意图；
图22b为一实施例中提供的步骤S704中所得结构沿第二方向的剖面示意图；
图23a为一实施例中提供的步骤S705中所得结构沿第一方向的剖面示意图；
图23b为一实施例中提供的步骤S705中所得结构沿第二方向的剖面示意图；
图24a为一实施例中提供的步骤S800中所得结构沿第一方向的剖面示意图；
图24b为一实施例中提供的步骤S800中所得结构沿第二方向的剖面示意图；
图25a为一实施例中提供的步骤S850中所得结构沿第一方向的剖面示意图；
图25b为一实施例中提供的步骤S850中所得结构沿第二方向的剖面示意图；
图26a为一实施例中提供的步骤S860中所得结构沿第一方向的剖面示意图；
图26b为一实施例中提供的步骤S860中所得结构沿第二方向的剖面示意图；
图27a为一实施例中提供的步骤S900中所得结构沿第一方向的剖面示意图；
图27b为一实施例中提供的步骤S900中所得结构沿第二方向的剖面示意图；
图28为一实施例中提供的步骤S1000的流程图；
图29a为一实施例中提供的步骤S1001所得结构沿第一方向的剖面示意图；
图29b为一实施例中提供的步骤S1001所得结构沿第二方向的剖面示意图；
图30a为一实施例中提供的步骤S1002所得结构沿第一方向的剖面示意图；并且，图30a亦为一实施例中提供的半导体结构在第一方向的剖面示意图；
图30b为一实施例中提供的步骤S1002所得结构沿第二方向的剖面示意图；并且，图30b亦为一实施例中提供的半导体结构在第二方向的剖面示意图；
图31为一实施例中提供的GAA的剖面示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。
应当明白，尽管可使用术语第一、第二等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本发明的范围。
环绕式栅极晶体管(Gate All Around transistor，简称GAA transistor)在可微缩、高性能以及低功耗等方面更具优势，被认为是下一代集成电路关键核心技术。以垂直型环绕式栅极晶体管为例，该晶体管在垂直方向上具有更多的集成自由度，可以有效减少其所占平面面积，也更易于实现多层器件间的垂直堆叠，以及通过全新的布线方式来进一步增加集成密度。
然而，在线宽尺寸不断缩小的情况下，在半导体结构中设置GAA晶体管，容易使得金属材料与半导体材料的接触因肖特基势垒以及金属-诱导-间隙态(Metal-Induced Gap States，简称MIGS)而具有过大的接触电阻。
基于此，请参阅图1，本申请一些实施例提供了一种半导体结构的制备方法，其包括的步骤如下。
S100，提供衬底，衬底上形成有浅沟槽隔离结构。浅沟槽隔离结构在衬底内隔离出多个间隔排布的有源区。
S200，在有源区内形成多个晶体管容置槽，晶体管容置槽与浅沟槽隔离结构之间具有间隔。
S300，在晶体管容置槽内形成柱状结构。柱状结构包括沿远离衬底的方向依次设置的源极、导电沟道和漏极。
S400，刻蚀去除位于前述间隔内的有源区及位于同一有源区内的相邻柱状结构之间的有源区，以形成位线沟槽。位线沟槽环绕源极。
S500，在位线沟槽内形成环绕接触源极的位线。
本申请实施例在浅沟槽隔离结构隔离出的有源区内设置晶体管容置槽，并使得晶体管容置槽与浅沟槽隔离结构之间具有间隔。这样可以先在该晶体管容置槽内形成柱状结构，再去除位于前述间隔内的有源区、以及同一有源区内相邻柱状结构之间的有源区，获得位线沟槽。基于此，在位线沟槽内形成位线之后，位线环绕接触源极，可以使得位线与源极之间具有较大的接触面积，从而降低位线与源极之间的接触电阻，也即位线与晶体管之间的接触电阻，以提升半导体结构的电学性能。并且，本申请实施例中的制备方法易于操作，有利于半导体结构的规模化生产。
在一些实施例中，柱状结构的材料包括二硫化钼(MoS 2)，位线的材料包括铋(Bi)金属。这样柱状结构的二维结晶结构并不易因其与位线的接触而被破坏，可以进一步降低位线与晶体管之间的接触电阻，以确保晶体管具有较好的低功耗性能和高频性能，从而进一步提升半导体结构的电学性能。
当然，柱状结构的材料也可以为其他二维半导体材料，位线的材料也可以为其他不易于与二维半导体材料形成合金以破坏二维结晶结构的材料。例如，柱状结构的材料为：硒化钼(MoSe 2)、二硫化钨(WS 2)、二硒化钨(WSe 2)或硒化铋(Bi 2Se 3)。位线的材料为：铬(Cr)、镉(Cd)、铱(Ir)、铌(Nb)、钽(Ta)、碲(Te)或钨(W)。
请参阅图2，在一些实施例中，在执行S400，即形成位线沟槽之前，半导体结构的制备方法还包括：在漏极上形成接触插塞。
在一些实施例中，接触插塞与柱状结构中的导电沟道、漏极通过一次构图工艺形成。也即，步骤S300还包括：在柱状结构上形成接触插塞。
在一些实施例中，接触插塞的材料包括铋(Bi)金属。或者，接触插塞的材料也可以为：铬(Cr)、镉(Cd)、铱(Ir)、铌(Nb)、钽(Ta)、碲(Te)或钨(W)。这样可以确保接触插塞与晶体管之间也具有较低的接触电阻。
基于此，在执行S500即在位线沟槽内形成环绕接触源极的位线之后，半导体结构的制备方法还包括如下步骤。
S600，形成覆盖位线、导电沟道、漏极和接触插塞的第一介质材料层。
S700，在第一介质材料层的背离导电沟道的表面上形成对应环绕导电沟道的环绕式栅极字线。相邻的环绕式栅极字线之间具有气隙。
S800，在第一介质材料层的背离接触插塞的表面上形成覆盖环绕式栅极字线的第二介质材料层。
S900，刻蚀第二介质材料层和第一介质材料层，以得到第一介质层及第二介质层。第一介质层和第二介质层暴露出接触插塞。
本申请实施例，在相邻的环绕式栅极字线之间设置气隙，可以利用气隙有效隔离栅极字线，以确保半导体结构的电学性能。
请参阅图3，在一些实施例中，在执行步骤S900，即刻蚀第二介质材料层和第一介质材料层之前，半导体结构的制备方法还包括步骤如下。
S850，在第二介质材料层上形成第三介质材料层。
S860，在第三介质材料层中形成多个接触窗口，以得到第三介质层。
基于此，步骤S900中，刻蚀第二介质材料层和第一介质材料层，以得到第一介质层及第二介质层，第一介质层和第二介质层暴露出接触插塞，包括：基于接触窗口刻蚀第二介质材料层和第一介质材料层，以得到第一介质层及第二介质层，第一介质层和第二介质层暴露出接触插塞。
在执行S900，即刻蚀第二介质材料层和第一介质材料层，以得到第一介质层及第二介质层，第一介质层和第二介质层暴露出接触插塞之后，半导体结构的制备方法还包括步骤如下。
S1000，在接触窗口内形成与接触插塞接触的接触焊盘。接触焊盘的结构可以根据实际需求选择设置。在一些实施例中，接触焊盘为金属焊盘，例如钨焊盘。从而可以确保接触焊盘具有较低电阻值，以及较高稳定性。
此外，在一些实施例中，接触插塞和接触焊盘可以共同构成存储节点接触结构，并用于接触存储电容，以构成存储单元。本申请实施例对此不做限定。
上述一些实施例示例性的给出了半导体结构的制备方法中的一些流程，其对应的具体实施方式详述于 以下一些实施例中。请结合上述一些流程理解以下内容。
在步骤S100中，请参阅图1～图3中的S100及图4a、图4b，提供衬底1，衬底1上形成有浅沟槽隔离结构11。浅沟槽隔离结构11在衬底1内隔离出多个间隔排布的有源区。
在一个示例中，衬底1包括但不仅限于硅衬底或硅基衬底。在一些实施例中，衬底1为蓝宝石衬底、硅衬底或碳化硅衬底。
在一个示例中，有源区的材料例如为多晶硅(poly)。浅沟槽隔离结构11例如为氧化硅(SiO 2)隔离结构。此外，有源区的排布方式，可以根据相关技术理解，本申请实施例对此不作限定。
在步骤S200中，请参阅图1～图3中的S200及图5a、图5b，在有源区内形成多个晶体管容置槽12，晶体管容置槽12与浅沟槽隔离结构11之间具有间隔L。
此处，晶体管容置槽12的形状及尺寸、以及间隔L的尺寸，可以根据实际需求选择设置，本申请实施例对此不做限定。在一个示例中，晶体管容置槽12例如为柱状凹槽。
在步骤S300中，请参阅图1、图2、图3及图6，执行S300，即在晶体管容置槽内形成柱状结构，包括步骤如下。
S301，在晶体管容置槽内填充半导体材料，形成源极。
S302，在衬底上沉积半导体材料，形成覆盖源极的半导体薄膜。
S303，将半导体薄膜图形化，形成漏极和导电沟道。漏极在衬底上的正投影和导电沟道在衬底上的正投影均与源极在衬底上的正投影重叠。
在步骤S301中，请参阅图4中的S301及图7a、图7b，在晶体管容置槽12内填充半导体材料，形成源极21。
在一个示例中，半导体材料为二维半导体材料，例如为过渡金属二硫化物。在一些实施例中，半导体材料为二硫化钼(MoS 2)、硒化钼(MoSe 2)、二硫化钨(WS 2)、二硒化钨(WSe 2)或硒化铋(Bi 2Se 3)。
在步骤S302中，请参阅图4中的S302及图8a、图8b，在衬底1上沉积半导体材料，形成覆盖源极21的半导体薄膜20。
此处，用于形成半导体薄膜20的半导体材料与S301中形成源极21的半导体材料可以相同，以确保半导体薄膜20可以与源极21良好键合。
此外，半导体薄膜20的厚度可以根据后续待形成的柱状结构的高度确定。
在一个示例中，半导体材料的沉积工艺包括但不限于物理气相沉积(Physical Vapor Deposition，简称PVD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)或原子层沉积(Atomic Layer Deposition，简称ALD)。
在一些实施例中，请结合图2理解，接触插塞与柱状结构中的导电沟道、漏极可以通过一次构图工艺形成。基于此，请参阅图9a和图9b，在形成半导体薄膜20之后，半导体结构的制备方法还包括：在半导体薄膜20上沉积接触插塞材料层30。
在一些实施例中，接触插塞材料层30包括铋金属层。此外，在一些实施例中，接触插塞材料层30的材料也可以为铬(Cr)、镉(Cd)、铱(Ir)、铌(Nb)、钽(Ta)、碲(Te)或钨(W)等。
在一个示例中，接触插塞材料层30的沉积工艺包括但不限于物理气相沉积(Physical Vapor Deposition，简称PVD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)或原子层沉积(Atomic Layer Deposition，简称ALD)。
在步骤S303中，请参阅图4中的S303及图10a、图10b，将半导体薄膜20图形化，形成漏极23和导电沟道22。漏极23在衬底1上的正投影和导电沟道22在衬底1上的正投影均与源极21在衬底1上的正投影重叠。如此，漏极23、导电沟道22和源极21呈柱状设置，共同构成柱状结构2。
可以理解的是，源极21和漏极23可以通过对半导体材料进行离子注入获得，本申请实施例对此不做具体阐述。
基于接触插塞材料层30形成于半导体薄膜20上，因此在将半导体薄膜20图形化之后，接触插塞材料层30也可同步图形化，以形成位于柱状结构2上的接触插塞3，如图10a和图10b中所示。
在步骤S400中，请参阅图1、图2、图3及图11，执行S400，即刻蚀去除位于间隔内的有源区及位于同一有源区内的相邻柱状结构之间的有源区，以形成位线沟槽，包括步骤如下。
S401，形成覆盖柱状结构裸露表面和衬底裸露表面的第一牺牲层。
S402，将第一牺牲层图形化，并基于第一牺牲层的图形刻蚀去除位于间隔内的有源区及位于同一有源区内的相邻柱状结构之间的有源区。
S403，去除第一牺牲层。
在步骤S401中，请参阅图11中的S401及图12a、图12b，形成覆盖柱状结构2裸露表面和衬底1裸露表面的第一牺牲层40。
在一个示例中，第一牺牲层40采用沉积工艺形成。第一牺牲层40的材料例如为氮化硅。
在步骤S402中，请参阅图11中的S402及图13a、图13b，将第一牺牲层40图形化，并基于第一牺牲层40的图形刻蚀去除位于间隔L内的有源区及位于同一有源区内的相邻柱状结构2之间的有源区，以形成位线沟槽41。位线沟槽41环绕源极21。
在一个示例中，将第一牺牲层40图形化的工艺例如为湿法刻蚀工艺。
在一个示例中，待去除有源区的刻蚀，可以基于第一牺牲层40的图形，采用自对准双重图案化(Self-Aligned Double Patterning，简称SADP)工艺或自对准四重图案化(Self-Aligned Quadruple Patterning，简称SAQP)工艺实现。
可以理解的是，在一些实施例中，步骤S403的执行可以在执行步骤S500之后进行，本申请实施例以此为例进行了示意如下。
在步骤S500中，请参阅图14a、图14b、图15a和图15b所示，在位线沟槽41内形成环绕接触源极21的位线5，包括步骤如下。
S501，请参阅图14a和图14b，形成填平位线沟槽41且覆盖第一牺牲层40裸露表面的位线材料层50。
在一些实施例中，位线材料层50包括铋金属层。
S502，请参阅图15a和图15b，将位线材料层50图形化，形成位于位线沟槽41内且环绕接触源极21的位线5。
在一个示例中，位线材料层50的图形化，可以基于第一牺牲层40的图形，采用自对准双重图案化(Self-Aligned Double Patterning，简称SADP)工艺或自对准四重图案化(Self-Aligned Quadruple Patterning，简称SAQP)工艺实现。
在步骤S403中，请参阅图11中的S403及图16a、图16b，去除第一牺牲层40。
在步骤S600中，请参阅图2、图3以及图17a、图17b，形成覆盖位线5、导电沟道22、漏极23和接触插塞3的第一介质材料层610。
在一个示例中，第一介质材料层610包括高介电常数的氧化物层，例如氧化硅层。第一介质材料层610可以采用沉积工艺形成。
在步骤S700中，请参阅图2、图3及图18，执行S700，即在第一介质材料层的背离导电沟道的表面上形成对应环绕导电沟道的环绕式栅极字线，包括步骤如下。
S701，在第一介质材料层上沉积金属材料。
S702，刻蚀金属材料，直至金属材料的上表面与柱状结构的上表面平齐，或金属材料的上表面低于柱状结构的上表面，获得金属图案层。
S703，形成覆盖第一介质材料层裸露表面和金属图案层的第二牺牲层。
S704，将第二牺牲层图形化，并基于第二牺牲层的图形刻蚀金属图案层，获得对应环绕导电沟道的环绕式栅极字线。
S705，去除第二牺牲层。
在步骤S701中，请参阅图18中的S701及图19a、图19b，在第一介质材料层610上沉积金属材料70。
在一些实施例中，金属材料70包括钨金属。或者，金属材料70为其他导电性能良好的金属材料，例如钼(Mo)、铝(Al)或钛(Ti)等。
在步骤S702中，请参阅图18中的S702及图20a、图20b，刻蚀金属材料70，直至金属材料70的上表面与柱状结构2的上表面平齐，或金属材料70的上表面低于柱状结构2的上表面，获得金属图案层71。
在步骤S703中，请参阅图18中的S703及图21a、图21b，形成覆盖第一介质材料层610裸露表面和金属图案层71的第二牺牲层80。
在一个示例中，第二牺牲层80采用旋涂工艺形成。第二牺牲层80例如为光刻胶层。
在步骤S704中，请参阅图18中的S704及图22a、图22b，将第二牺牲层80图形化，并基于第二牺牲层80的图形刻蚀金属图案层71，获得对应环绕导电沟道22的环绕式栅极字线7。相邻的环绕式栅极字线7之间具有气隙G。
在一个示例中，将第二牺牲层80图形化的工艺例如为湿法刻蚀工艺。
在步骤S705中，请参阅图18中的S705及图23a、图23b，去除第二牺牲层80。
在步骤S800中，请参阅图2、图3及图24a、图24b，在第一介质材料层610的背离接触插塞3的表面上形成覆盖环绕式栅极字线7的第二介质材料层620。
此处，第二介质材料层620的材料可以与第一介质材料层610的材料相同，例如均为氧化硅。从而方便于后续通过一次构图工艺刻蚀。此外，第二介质材料层620可以采用沉积工艺形成。
在步骤S850中，请参阅图3及图25a、图25b，在第二介质材料层620上形成第三介质材料层630。
此处，第三介质材料层630的材料可以与第二介质材料层620的材料不同，例如第三介质材料层630的材料为氮化硅。此外，第三介质材料层630可以采用沉积工艺形成，第三介质材料层630的沉积厚度可以根据后续待形成接触焊盘的高度尺寸选择设置。
在步骤S860中，请参阅图3及图26a、图26b，在第三介质材料层630中形成多个接触窗口K，以得到第三介质层63。
此处，接触窗口K用于容置接触焊盘，接触窗口K的形状及其分布可以根据后续待形成接触焊盘的形状及分布确定。
在步骤S900中，请参阅图3及图27a、图27b，基于接触窗口K，刻蚀第二介质材料层620和第一介质材料层610，以得到第一介质层61及第二介质层62。第一介质层61和第二介质层62暴露出接触插塞3。
在步骤S1000中，请参阅图3及图28，执行S1000，即在接触窗口内形成与接触插塞接触的接触焊盘包括步骤如下。
S1001，在接触窗口内及第三介质层的表面形成焊盘材料层。
S1002，采用化学机械研磨工艺去除位于第三介质层表面的焊盘材料层，保留于接触窗口内的焊盘材料层即为接触焊盘。
在步骤S1001中，请参阅图28中的S1001及图29a、图29b，在接触窗口K内及第三介质层63的表面形成焊盘材料层90。在一些实施例中，焊盘材料层90为钨金属层。
在步骤S1002中，请参阅图28中的S1002及图30a、图30b，采用化学机械研磨工艺去除位于第三介质层63表面的焊盘材料层90，保留于接触窗口K内的焊盘材料层即为接触焊盘9。
本申请实施例中，采用化学机械研磨工艺形成接触焊盘9，可以确保接触焊盘9的表面平坦，以便于后续在接触焊盘9的表面形成存储电容等其他电学器件，并确保接触焊盘9可以与电学器件良好接触，从而确保接触焊盘9的电接触性能。
本申请一些实施例还提供了一种半导体结构，采用如上一些实施例中的制备方法制备获得。
请参阅图30a、图30b和图31，半导体结构包括衬底1、晶体管容置槽12、柱状结构2以及位线5。衬底1上形成有浅沟槽隔离结构11，浅沟槽隔离结构11在衬底1内隔离出多个间隔排布的有源区。晶体管容置槽12位于有源区内，且与浅沟槽隔离结构11之间具有间隔。柱状结构2位于晶体管容置槽12内，柱状结构2包括：沿远离衬底1的方向依次设置的源极21、导电沟道22和漏极23。位线5位于所述间隔L内，且环绕接触源极21。
在一个示例中，衬底1包括但不仅限于硅衬底或硅基衬底。在一些实施例中，衬底1为蓝宝石衬底、硅衬底或碳化硅衬底。
在一个示例中，有源区的材料例如为多晶硅(poly)。浅沟槽隔离结构11例如为氧化硅(SiO 2)隔离结构。
在一些实施例中，柱状结构2的材料包括二硫化钼。和/或，位线5的材料包括铋金属。当然，柱状结构的材料也可以为其他二维半导体材料，位线的材料也可以为其他不易于与二维半导体材料形成合金以破坏二维结晶结构的材料。例如，柱状结构的材料为：硒化钼(MoSe 2)、二硫化钨(WS 2)、二硒化钨(WSe 2)或硒化铋(Bi 2Se 3)。位线的材料为：铬(Cr)、镉(Cd)、铱(Ir)、铌(Nb)、钽(Ta)、碲(Te)或钨(W)。
本申请实施例中，位线5环绕接触源极21，可以使得位线5与源极21之间具有较大的接触面积，从而降低位线5与源极21之间的接触电阻，也即位线5与GAA晶体管之间的接触电阻，以提升半导体结构的电学性能。
在一些实施例中，柱状结构2的材料包括二硫化钼(MoS 2)，位线5的材料包括铋(Bi)金属。这样柱状结构2的二维结晶结构并不易因其与位线5的接触而被破坏，可以进一步降低位线5与GAA晶体管之间的接触电阻，以确保GAA晶体管具有较好的低功耗性能和高频性能，从而进一步提升半导体结构的电学性能。
在一些实施例中，半导体结构还包括：接触插塞3、第一介质层61、环绕式栅极字线7和第二介质层62。接触插塞3位于漏极23的背离导电沟道22的表面。第一介质层61覆盖位线5，且位于导电沟道22、漏极23和接触插塞3的侧壁。环绕式栅极字线7位于第一介质层61的背离导电沟道22的表面，且环绕导电沟道22。第二介质层62位于第一介质层61的背离接触插塞3的表面，且覆盖环绕式栅极字线7。相邻的环绕式栅极字线7之间具有气隙G。
在一些实施例中，接触插塞3的材料包括铋(Bi)金属。或者，接触插塞3的材料也可以为：铬(Cr)、镉(Cd)、铱(Ir)、铌(Nb)、钽(Ta)、碲(Te)或钨(W)。这样可以确保接触插塞与晶体管之间也具有较低的接触电阻。
在一些实施例中，第一介质层61为高介电常数的氧化物层，例如氧化硅层。第二介质层62的材料可以与第一介质层61的材料相同。
在一些实施例中，环绕式栅极字线7的材料为钨(W)、钼(Mo)、铝(Al)或钛(Ti)等。
在一些实施例中，半导体结构还包括：第三介质层63和接触焊盘9。第三介质层63具有接触窗口K，且至少覆盖第二介质层62。接触焊盘9位于接触窗口K内，并与接触插塞3接触。
在一些实施例中，第三介质层63的材料可以与第二介质层62的材料不同，例如第三介质层63的材料为氮化硅。
在一些实施例中，接触焊盘9为钨焊盘。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体结构的制备方法，包括：
    提供衬底，所述衬底上形成有浅沟槽隔离结构，所述浅沟槽隔离结构在所述衬底内隔离出多个间隔排布的有源区；
    在所述有源区内形成多个晶体管容置槽，所述晶体管容置槽与所述浅沟槽隔离结构之间具有间隔；
    在所述晶体管容置槽内形成柱状结构，所述柱状结构包括沿远离所述衬底的方向依次设置的源极、导电沟道和漏极；
    刻蚀去除位于所述间隔内的所述有源区及位于同一所述有源区内的相邻所述柱状结构之间的所述有源区，以形成位线沟槽，所述位线沟槽环绕所述源极；
    在所述位线沟槽内形成环绕接触所述源极的位线。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，所述在所述晶体管容置槽内形成柱状结构，包括：
    在所述晶体管容置槽内填充半导体材料，形成所述源极；
    在所述衬底上沉积所述半导体材料，形成覆盖所述源极的半导体薄膜；
    将所述半导体薄膜图形化，形成所述漏极和所述导电沟道；所述漏极在所述衬底上的正投影和所述导电沟道在所述衬底上的正投影均与所述源极在所述衬底上的正投影重叠。
  3. 根据权利要求1所述的半导体结构的制备方法，其中，所述刻蚀去除位于所述间隔内的所述有源区及位于同一所述有源区内的相邻所述柱状结构之间的所述有源区，以形成位线沟槽，包括：
    形成覆盖所述柱状结构裸露表面和所述衬底裸露表面的第一牺牲层；
    将所述第一牺牲层图形化，并基于所述第一牺牲层的图形刻蚀去除位于所述间隔内的所述有源区及位于同一所述有源区内的相邻所述柱状结构之间的所述有源区；
    去除所述第一牺牲层。
  4. 根据权利要求1所述的半导体结构的制备方法，其中，在形成所述位线沟槽之前还包括：在所述漏极上形成接触插塞；
    在所述位线沟槽内形成环绕接触所述源极的位线之后还包括：
    形成覆盖所述位线、所述导电沟道、所述漏极和所述接触插塞的第一介质材料层；
    在所述第一介质材料层的背离所述导电沟道的表面上形成对应环绕所述导电沟道的环绕式栅极字线；相邻的所述环绕式栅极字线之间具有气隙；
    在所述第一介质材料层的背离所述接触插塞的表面上形成覆盖所述环绕式栅极字线的第二介质材料层；
    刻蚀所述第二介质材料层和所述第一介质材料层，以得到第一介质层及第二介质层，所述第一介质层和所述第二介质层暴露出所述接触插塞。
  5. 根据权利要求4所述的半导体结构的制备方法，其中，所述在所述第一介质材料层的背离所述导电沟道的表面上形成对应环绕所述导电沟道的环绕式栅极字线，包括：
    在所述第一介质材料层上沉积金属材料；
    刻蚀所述金属材料，直至所述金属材料的上表面与所述柱状结构的上表面平齐，或所述金属材料的上表面低于所述柱状结构的上表面，获得金属图案层；
    形成覆盖所述第一介质材料层裸露表面和所述金属图案层的第二牺牲层；
    将所述第二牺牲层图形化，并基于所述第二牺牲层的图形刻蚀所述金属图案层，获得对应环绕所述导电沟道的环绕式栅极字线；
    去除所述第二牺牲层。
  6. 根据权利要求5所述的半导体结构的制备方法，其中，所述金属材料包括钨金属。
  7. 根据权利要求4所述的半导体结构的制备方法，其中，
    在刻蚀所述第二介质材料层和所述第一介质材料层之前还包括：在所述第二介质材料层上形成第三介质材料层；并在所述第三介质材料层中形成多个接触窗口，以得到第三介质层；
    所述刻蚀所述第二介质材料层和所述第一介质材料层，以得到第一介质层及第二介质层，所述第一介质层和所述第二介质层暴露出所述接触插塞包括：基于所述接触窗口刻蚀所述第二介质材料层和所述第一介质材料层，以得到所述第一介质层及所述第二介质层，所述第一介质层和所述第二介质层暴露出所述接触插塞；
    所述刻蚀所述第二介质材料层和所述第一介质材料层，以得到第一介质层及第二介质层，所述第一介质层和所述第二介质层暴露出所述接触插塞之后还包括：在所述接触窗口内形成与所述接触插塞接触的接触焊盘。
  8. 根据权利要求7所述的半导体结构的制备方法，其中，所述在所述接触窗口内形成与所述接触插塞接触的接触焊盘包括：
    在所述接触窗口内及所述第三介质层的表面形成焊盘材料层；
    采用化学机械研磨工艺去除位于所述第三介质层表面的所述焊盘材料层，保留于所述接触窗口内的所述焊盘材料层即为所述接触焊盘。
  9. 根据权利要求4所述的半导体结构的制备方法，其中，所述位线和/或所述接触插塞的材料包括铋金属。
  10. 根据权利要求1～9中任一项所述的半导体结构的制备方法，其中，所述柱状结构的材料包括二硫化钼。
  11. 一种半导体结构，其中，包括：
    衬底，所述衬底上形成有浅沟槽隔离结构，所述浅沟槽隔离结构在所述衬底内隔离出多个间隔排布的有源区；
    晶体管容置槽，位于所述有源区内，且与所述浅沟槽隔离结构之间具有间隔；
    柱状结构，位于所述晶体管容置槽内，包括：沿远离所述衬底的方向依次设置的源极、导电沟道和漏极；
    以及，位线，位于所述间隔内，且环绕接触所述源极。
  12. 根据权利要求11所述的半导体结构，其中，
    所述柱状结构的材料包括二硫化钼；
    和/或，所述位线的材料包括铋金属。
  13. 根据权利要求11所述的半导体结构，其中，所述半导体结构还包括：
    接触插塞，位于所述漏极的背离所述导电沟道的表面；
    第一介质层，覆盖所述位线，且位于所述导电沟道、所述漏极和所述接触插塞的侧壁；
    环绕式栅极字线，位于所述第一介质层的背离所述导电沟道的表面，且环绕所述导电沟道；
    第二介质层，位于所述第一介质层的背离所述接触插塞的表面，且覆盖所述环绕式栅极字线；
    其中，相邻的所述环绕式栅极字线之间具有气隙。
  14. 根据权利要求13所述的半导体结构，其中，所述半导体结构还包括：
    第三介质层，具有接触窗口，且至少覆盖所述第二介质层；
    接触焊盘，位于所述接触窗口内，并与所述接触插塞接触。
  15. 根据权利要求13所述的半导体结构，其中，所述接触插塞的材料包括铋金属。
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