WO2024176864A1 - エッチング方法及びプラズマ処理装置 - Google Patents

エッチング方法及びプラズマ処理装置 Download PDF

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Publication number
WO2024176864A1
WO2024176864A1 PCT/JP2024/004407 JP2024004407W WO2024176864A1 WO 2024176864 A1 WO2024176864 A1 WO 2024176864A1 JP 2024004407 W JP2024004407 W JP 2024004407W WO 2024176864 A1 WO2024176864 A1 WO 2024176864A1
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Prior art keywords
layer
containing layer
metal
silicon
gas
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Ceased
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English (en)
French (fr)
Japanese (ja)
Inventor
隆宏 米澤
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Priority to KR1020257030371A priority Critical patent/KR20250154414A/ko
Priority to JP2025502273A priority patent/JPWO2024176864A1/ja
Priority to CN202480012643.XA priority patent/CN120693684A/zh
Publication of WO2024176864A1 publication Critical patent/WO2024176864A1/ja
Priority to US19/298,198 priority patent/US20250372381A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32174—Circuits specially adapted for controlling the RF discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/3244—Gas supply means
    • H01J37/32449—Gas control, e.g. control of the gas flow
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H10P76/2043—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/332—Coating
    • H01J2237/3321—CVD [Chemical Vapor Deposition]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching
    • H01J2237/3343—Problems associated with etching
    • H01J2237/3346—Selectivity

Definitions

  • An exemplary embodiment of the present disclosure relates to an etching method and a plasma processing apparatus.
  • Patent Document 1 discloses a method for manufacturing a semiconductor device in which a substrate on which a patterned layer is deposited by a lithography process is exposed to plasma to deposit a layer containing silicon on the patterned layer.
  • the plasma is generated from a mixed gas containing SiCl4 and one or more of argon, helium, nitrogen, and hydrogen.
  • This disclosure provides an etching method and plasma processing apparatus that can improve the etching selectivity ratio.
  • a technique is provided that can improve the etching selectivity.
  • FIG. 1 is a diagram for explaining an example of the configuration of a plasma processing system.
  • FIG. 2 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.
  • FIG. 3 is a flow chart of an etching method according to one exemplary embodiment.
  • 4A to 4D are schematic cross-sectional views for explaining the etching method of FIG.
  • Each of (a) and (b) of FIG. 5 is a schematic cross-sectional view for explaining a method of forming a resist layer according to one exemplary embodiment.
  • FIG. 6 is a flow chart of a method for forming a resist layer.
  • FIG. 7A is a schematic cross-sectional view for explaining surface treatment of the silicon-containing layer, and FIG.
  • FIG. 7B is a schematic cross-sectional view for explaining trim etching of the silicon-containing layer.
  • FIG. 8 is a flow chart of a method for forming a silicon-containing layer.
  • FIG. 9A is a schematic cross-sectional view for explaining the surface treatment of the metal-containing layer
  • FIG. 9B is a schematic cross-sectional view for explaining the trim etching of the metal-containing layer.
  • FIG. 10 is a flow chart of a method for forming a metal-containing layer.
  • FIG. 11A is a schematic cross-sectional view for explaining a method for producing a deposition layer according to a first modified example
  • FIG. 11B is a schematic cross-sectional view for explaining etching according to the first modified example.
  • FIG. 11A is a schematic cross-sectional view for explaining a method for producing a deposition layer according to a first modified example
  • FIG. 11B is a schematic cross-sectional view for explaining etching according to the first modified example.
  • FIG. 12(a) is a schematic cross-sectional view for explaining the etching related to the second modified example
  • FIG. 12(b) is a schematic cross-sectional view for explaining the method of generating a deposition layer related to the second modified example
  • FIG. 12(c) is a schematic cross-sectional view for explaining the etching related to the second modified example.
  • Each of (a) and (b) of FIG. 13 is a schematic cross-sectional view for explaining a method for producing a metal-containing layer according to a third modified example.
  • an etching method includes the steps of: (a) providing a substrate including a first layer and a second layer having a pattern on the first layer; (b) forming a silicon-containing layer on a surface of the third layer in preference to a surface of the first layer; (c) forming a metal-containing layer on a surface of the silicon-containing layer; and (d) etching the exposed first layer using the second layer, the silicon-containing layer, and the metal-containing layer as a mask.
  • a plasma processing apparatus in another exemplary embodiment, includes a chamber, a substrate support provided in the chamber and having a temperature control module, a gas supply configured to supply a processing gas into the chamber, a plasma generation unit configured to generate plasma from the processing gas in the chamber, and a control unit.
  • the control unit is configured to control the temperature control module, the gas supply unit, and the plasma generation unit so that, in a state in which a substrate including a first layer and a second layer having a pattern on the first layer is supported by the substrate support unit, a silicon-containing layer is formed on a surface of the second layer in preference to a surface of the first layer, a metal-containing layer is formed on a surface of the silicon-containing layer, and the exposed first layer is etched using the second layer, the silicon-containing layer, and the metal-containing layer as a mask.
  • FIG. 1 is a diagram for explaining an example of the configuration of a plasma processing system.
  • the plasma processing system includes a plasma processing device 1 and a control unit 2.
  • the plasma processing system is an example of a substrate processing system
  • the plasma processing device 1 is an example of a substrate processing device.
  • the plasma processing device 1 includes a plasma processing chamber 10, a substrate support unit 11, and a plasma generation unit 12.
  • the plasma processing chamber 10 has a plasma processing space.
  • the plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space, and at least one gas exhaust port for exhausting gas from the plasma processing space.
  • the gas supply port is connected to a gas supply unit 20 described later, and the gas exhaust port is connected to an exhaust system 40 described later.
  • the substrate support unit 11 is disposed in the plasma processing space, and has a substrate support surface for supporting a substrate.
  • the plasma generating unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space.
  • the plasma formed in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), ECR plasma (Electron-Cyclotron-resonance plasma), Helicon wave excited plasma (HWP), or surface wave plasma (SWP), etc.
  • various types of plasma generating units may be used, including AC (Alternating Current) plasma generating units and DC (Direct Current) plasma generating units.
  • the AC signal (AC power) used in the AC plasma generating unit has a frequency in the range of 100 kHz to 10 GHz.
  • AC signals include RF (Radio Frequency) signals and microwave signals.
  • the RF signal has a frequency in the range of 100 kHz to 150 MHz.
  • the control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform the various steps described in this disclosure.
  • the control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform the various steps described herein. In one embodiment, a part or all of the control unit 2 may be included in the plasma processing apparatus 1.
  • the control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3.
  • the control unit 2 is realized, for example, by a computer 2a.
  • the processing unit 2a1 may be configured to perform various control operations by reading a program from the storage unit 2a2 and executing the read program. This program may be stored in the storage unit 2a2 in advance, or may be acquired via a medium when necessary.
  • the acquired program is stored in the storage unit 2a2 and is read from the storage unit 2a2 by the processing unit 2a1 and executed.
  • the medium may be various storage media readable by the computer 2a, or may be a communication line connected to the communication interface 2a3.
  • the processing unit 2a1 may be a CPU (Central Processing Unit).
  • the memory unit 2a2 may include a RAM (Random Access Memory), a ROM (Read Only Memory), a HDD (Hard Disk Drive), a SSD (Solid State Drive), or a combination of these.
  • the communication interface 2a3 may communicate with the plasma processing device 1 via a communication line such as a LAN (Local Area Network).
  • FIG. 1 is a diagram for explaining a configuration example of a capacitively coupled plasma processing device.
  • the capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply 30, and an exhaust system 40.
  • the plasma processing apparatus 1 also includes a substrate support unit 11 and a gas inlet unit.
  • the gas inlet unit is configured to introduce at least one processing gas into the plasma processing chamber 10.
  • the gas inlet unit includes a shower head 13.
  • the substrate support unit 11 is disposed in the plasma processing chamber 10.
  • the shower head 13 is disposed above the substrate support unit 11. In one embodiment, the shower head 13 constitutes at least a part of the ceiling of the plasma processing chamber 10.
  • the plasma processing chamber 10 has a plasma processing space 10s defined by the shower head 13, the sidewall 10a of the plasma processing chamber 10, and the substrate support unit 11.
  • the plasma processing chamber 10 is grounded.
  • the shower head 13 and the substrate support unit 11 are electrically insulated from the housing of the plasma processing chamber 10. Note that a process that does not use plasma can be performed in the plasma processing space 10s. In other words, the processes carried out in the plasma processing space 10s may include processes in which plasma is not used.
  • the substrate support 11 includes a main body 111 and a ring assembly 112.
  • the main body 111 has a central region 111a for supporting the substrate W and an annular region 111b for supporting the ring assembly 112.
  • a wafer is an example of a substrate W.
  • the annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view.
  • the substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111.
  • the central region 111a is also called a substrate support surface for supporting the substrate W
  • the annular region 111b is also called a ring support surface for supporting the ring assembly 112.
  • the ring assembly 112 may be made of an inorganic material or an organic material depending on the intended processing.
  • the main body 111 includes a base 1110 and an electrostatic chuck 1111.
  • the base 1110 includes a conductive member.
  • the conductive member of the base 1110 may function as a lower electrode.
  • the electrostatic chuck 1111 is disposed on the base 1110.
  • the electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a.
  • the ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that other members surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck, an annular insulating member, etc., may have the annular region 111b.
  • the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member.
  • at least one RF/DC electrode coupled to an RF power source 31 and/or a DC power source 32 described later may be disposed in the ceramic member 1111a.
  • the at least one RF/DC electrode functions as a lower electrode.
  • the RF/DC electrode is also called a bias electrode.
  • the conductive member of the base 1110 and the at least one RF/DC electrode may function as multiple lower electrodes.
  • the electrostatic electrode 1111b may function as a lower electrode.
  • the substrate support 11 includes at least one lower electrode.
  • the ring assembly 112 includes one or more annular members.
  • the one or more annular members include one or more edge rings and at least one cover ring.
  • the edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.
  • the substrate support 11 may include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature.
  • the temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof.
  • a heat transfer fluid such as brine or a gas flows through the flow passage 1110a.
  • the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111.
  • the substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the back surface of the substrate W and the central region 111a.
  • the target temperature is greater than or equal to -80°C and less than or equal to 50°C.
  • the shower head 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s.
  • the shower head 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas inlets 13c.
  • the processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the multiple gas inlets 13c.
  • the shower head 13 also includes at least one upper electrode.
  • the gas introduction unit may include, in addition to the shower head 13, one or more side gas injectors (SGI) attached to one or more openings formed in the side wall 10a.
  • SGI side gas injectors
  • the gas supply unit 20 is a member that supplies the above-mentioned processing gas into the plasma processing chamber 10, and may include at least one gas source 21 and at least one flow controller 22.
  • the gas supply unit 20 is configured to supply at least one processing gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22.
  • Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller.
  • the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of the at least one processing gas.
  • the power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit.
  • the RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and/or at least one upper electrode. This causes a plasma to be formed from at least one processing gas supplied to the plasma processing space 10s.
  • the RF power supply 31 can function as at least a part of the plasma generating unit 12.
  • a bias RF signal to at least one lower electrode, a bias potential is generated on the substrate W, and ion components in the formed plasma can be attracted to the substrate W.
  • the RF power supply 31 includes a first RF generator 31a and a second RF generator 31b.
  • the first RF generator 31a is configured to generate a source RF signal (source RF power) for plasma generation.
  • the first RF generator 31a is coupled to at least one lower electrode and/or at least one upper electrode via at least one impedance matching circuit.
  • the upper electrode may have a top plate such as a silicon top plate.
  • the source RF signal has a frequency in the range of 10 MHz to 150 MHz.
  • the first RF generator 31a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and/or at least one upper electrode.
  • the second RF generator 31b is coupled to at least one lower electrode via at least one impedance matching circuit and configured to generate a bias RF signal (bias RF power).
  • the frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal.
  • the bias RF signal has a frequency lower than the frequency of the source RF signal.
  • the bias RF signal has a frequency in the range of 100 kHz to 60 MHz.
  • the second RF generator 31b may be configured to generate multiple bias RF signals having different frequencies.
  • the generated one or more bias RF signals are provided to at least one lower electrode. Also, in various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.
  • the power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10.
  • the DC power supply 32 includes a first DC generator 32a and a second DC generator 32b.
  • the first DC generator 32a is connected to at least one lower electrode and configured to generate a first DC signal.
  • the generated first DC signal is applied to the at least one lower electrode.
  • the second DC generator 32b is connected to at least one upper electrode and configured to generate a second DC signal.
  • the generated second DC signal is applied to the at least one upper electrode.
  • the first and second DC signals may be pulsed.
  • a sequence of voltage pulses is applied to at least one lower electrode and/or at least one upper electrode.
  • the voltage pulses may have a rectangular, trapezoidal, triangular or combination thereof pulse waveform.
  • a waveform generator for generating a sequence of voltage pulses from the DC signal is connected between the first DC generator 32a and at least one lower electrode.
  • the first DC generator 32a and the waveform generator constitute a voltage pulse generator.
  • the second DC generator 32b and the waveform generator constitute a voltage pulse generator
  • the voltage pulse generator is connected to at least one upper electrode.
  • the voltage pulses may have a positive polarity or a negative polarity.
  • the sequence of voltage pulses may also include one or more positive polarity voltage pulses and one or more negative polarity voltage pulses within one period.
  • the first and second DC generating units 32a and 32b may be provided in addition to the RF power source 31, or the first DC generating unit 32a may be provided in place of the second RF generating unit 31b.
  • the exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10.
  • the exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s is adjusted by the pressure regulating valve.
  • the vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.
  • FIG. 3 is a flow chart of an etching method according to one exemplary embodiment.
  • Each of (a) to (d) of FIG. 4 is a schematic cross-sectional view for explaining the etching method of FIG. 3.
  • the etching method MT1 shown in FIG. 3 (hereinafter referred to as "method MT1") can be performed by the plasma processing apparatus 1 of the above embodiment.
  • Method MT1 can be applied to the substrate W shown in (a) of FIG. 4.
  • the substrate W may be a member used in the manufacture of a semiconductor device.
  • the semiconductor device includes, for example, a semiconductor memory device such as a DRAM or a 3D-NAND flash memory.
  • the substrate W includes a base layer BL, an underlayer UML (first layer), and a resist layer RL (second layer) having a pattern on the underlayer UML.
  • the base layer BL may be, for example, an organic film, a dielectric film, a metal film, or a semiconductor film formed on a silicon wafer, or a laminated film thereof.
  • the base layer BL may include silicon oxide, carbon-doped oxide, porous oxide, silicon nitride, silicon oxynitride, silicon, titanium nitride, titanium, tantalum nitride, tantalum, or the like.
  • the underlayer UML may be a film that is etched using the resist layer RL as a mask.
  • the underlayer UML may function as a mask for the base layer BL.
  • the underlayer UML is, for example, a spin-on-glass (SOG) film, a SiON film, a silicon-containing antireflective coating (SiARC), or an organic film.
  • the resist layer RL is a layer that can function as part of an etching mask for the underlayer UML, and can be a metal-containing resist film that contains a metal.
  • the metal may include at least one metal selected from the group consisting of Sn, Hf, and Ti.
  • the resist layer RL contains Sn and may include tin oxide (SnO).
  • the resist layer RL may include an organic material.
  • a photoresist film containing a metal is formed on the underlayer UML that has been subjected to adhesion treatment, etc.
  • the photoresist film may be formed by a dry process, a wet process, or both a dry process and a wet process.
  • the photoresist film is subjected to a heating process such as pre-baking. After the heating process, the photoresist film is irradiated with EUV (extreme ultraviolet light) using an exposure device and an exposure mask (reticle).
  • EUV extreme ultraviolet light
  • an exposed first region RM1 and an unexposed second region RM2 are formed.
  • the first region RM1 is an EUV exposed region corresponding to an opening provided in the exposure mask.
  • the second region RM2 is an EUV unexposed region corresponding to a pattern provided in the exposure mask.
  • the EUV has a wavelength in the range of, for example, 10 to 20 nm. EUV can have a wavelength in the range of 11-14 nm, with one example having a wavelength of 13.5 nm.
  • the second region RM2 is selectively removed in a development process.
  • a resist layer RL having a pattern derived from the first region RM1 is formed on the underlayer UML.
  • a part of the first region RM1 may also be removed.
  • the second region RM2 is removed with a first selectivity ratio with respect to the first region RM1.
  • the "selectivity ratio" in this development process is also called the development contrast, and corresponds to the ratio of the development speed of the second region RM2 to the development speed of the first region RM1.
  • the development process may be a dry process, a wet process, or both a dry process and a wet process.
  • the development process uses a first process gas such as a halogen-containing gas.
  • the halogen-containing gas may be a gas containing a halogen-containing inorganic acid, and may be an inorganic acid gas containing Br, Cl, or the like.
  • the gas containing a halogen-containing inorganic acid is at least one selected from the group consisting of HBr gas, BCl 3 gas, HCl, and HF.
  • the first process gas may be a gas containing an organic acid.
  • the gas containing an organic acid may be, for example, a gas containing at least one selected from the group consisting of a carboxylic acid, a ⁇ -dicarbonyl compound, and an alcohol.
  • the carboxylic acid in one example, may be formic acid (HCOOH), acetic acid (CH 3 COOH), trichloroacetic acid (CCl 3 COOH), monofluoroacetic acid (CFH 2 COOH), difluoroacetic acid (CF 2 HCOOH), trifluoroacetic acid (CF 3 COOH) chloro-difluoroacetic acid (CClF 2 COOH), sulfur-containing acetic acid, thioacetic acid (CH 3 COSH), thioglycolic acid (HSCH 2 COOH), trifluoroacetic anhydride ((CF 3 CO) 2 O), acetic anhydride ((CH 3 CO) 2 O).
  • HCOOH formic acid
  • acetic acid CH 3 COOH
  • CCl 3 COOH trichloroacetic acid
  • monofluoroacetic acid CFH 2 COOH
  • difluoroacetic acid CF 2 HCOOH
  • trifluoroacetic acid CF 3 COOH
  • the ⁇ -dicarbonyl compound in one example, can be acetylacetone (CH 3 C(O)CH 2 C(O)CH 3 ), trichloroacetylacetone (CCl 3 C(O)CH 2 C(O)CH 3 ), hexachloroacetylacetone (CCl 3 C(O)CH 2 C(O)CCl 3 ), trifluoroacetylacetone CF 3 C(O)CH 2 C(O)CH 3 ), or hexafluoroacetylacetone (HFAc, CF 3 C(O)CH 2 C(O)CF 3 ).
  • the alcohol in one example, can be nonafluoro-tert-butyl alcohol ((CF 3 ) 3 COH).
  • the first process gas includes trifluoroacetic acid. In one embodiment, the first process gas includes a halogenated organic acid vapor.
  • the first process gas includes at least one selected from the group consisting of trifluoroacetic anhydride, acetic anhydride, trichloroacetic acid, CFH 2 COOH, CF 2 HCOOH, chloro-difluoroacetic acid, sulfur-containing acetic acid, and thioacetic acid and thioglycolic acid. In one embodiment, the first process gas is a mixture of a carboxylic acid and a hydrogen halide or a mixture of acetic acid and formic acid.
  • FIG. 5 is a schematic cross-sectional view showing an example after the development process.
  • scum (residues) S1 to S3 that cannot be completely removed are generated on the substrate W.
  • Scum S1 is resist or its by-products that has scattered from the second region RM2 and adhered to the resist layer RL.
  • Each of scums S2 and S3 is a portion that remains in the second region RM2 without being removed.
  • Each of scums S2 and S3 may be a convex portion on the surface of the resist layer RL and/or the underlayer UML.
  • Scums S1 to S3 may have various shapes and sizes. At least one of scums S1 to S3 may be generated after the development process.
  • the scum may be removed by the following descum process.
  • all of the scum S1 to S3 on the substrate W may be removed by plasma generated from the second process gas.
  • the second process gas is supplied from the gas supply unit 20 into the plasma processing space 10s.
  • a source RF signal is supplied to the upper electrode or the lower electrode. This generates a high-frequency electric field in the plasma processing space 10s, and plasma is generated from the second process gas.
  • a bias signal may be supplied to the lower electrode of the substrate support unit 11.
  • the scum S1 to S3 are removed by the plasma generated from the second process gas.
  • the descum process may be performed if at least one of the scums S1 to S3 occurs.
  • the second process gas may include at least one selected from the group consisting of a helium-containing gas, a hydrogen-containing gas, a bromine-containing gas, and a chlorine-containing gas.
  • the second process gas may include at least one selected from the group consisting of helium gas, hydrogen gas, hydrogen bromide gas, and boron trichloride gas.
  • the second process gas may further include a noble gas such as Ar gas, or an inert gas such as N2 gas.
  • Step ST11 Providing a substrate
  • a substrate W including an underlayer UML and a resist layer RL having a pattern on the underlayer UML is provided in a plasma processing chamber 10 (step ST11).
  • the substrate W is provided on a substrate support 11.
  • the substrate W is supported by the substrate support 11.
  • FIG. 6 is a flowchart of a forming method of a resist layer. As shown in FIG. 6, first, a resist layer RL having a pattern is formed on the underlayer UML (step ST11A).
  • step ST11A for example, a resist layer RL having a pattern is formed by photolithography or the like (see FIG. 5A). Then, scum S1 to S3 (see FIG. 5B) adhering to the resist layer RL and the underlayer UML are removed (step ST11B, descum step). If the predetermined conditions are satisfied after step ST11B (step ST11C: YES), the following step ST12 is performed. On the other hand, if the predetermined conditions are not satisfied after step ST11B (step ST11C: NO), steps ST11A and ST11B are performed again.
  • the predetermined conditions include at least one of the pattern shape of the resist layer RL, the thickness of the resist layer RL, the number of scum, etc. Note that from the second step onwards, either one of steps ST11A and ST11B may not be performed.
  • Step ST12 Formation of silicon-containing layer
  • the silicon-containing layer SL is formed by utilizing plasma generated from a third processing gas supplied into the plasma processing chamber 10.
  • the third processing gas is supplied from the gas supply unit 20 into the plasma processing space 10s.
  • a source RF signal is supplied to the upper electrode or the lower electrode. This generates a high-frequency electric field in the plasma processing space 10s, and plasma is generated from the third processing gas.
  • radicals containing silicon contained in the plasma are deposited on the surface of the resist layer RL.
  • the temperature (target temperature) of the substrate W may be adjusted by a temperature control module of the substrate support unit 11.
  • Forming the silicon-containing layer SL preferentially on the surface of the resist layer RL rather than on the surface of the underlayer UML may correspond to selectively forming the silicon-containing layer SL on the surface of the resist layer RL.
  • the silicon-containing layer SL may be formed only on the surface of the resist layer RL, or the silicon-containing layer SL may be formed on both the surface of the resist layer RL and the surface of the underlayer UML. In the latter case, the thickness of the portion provided on the surface of the resist layer RL may be significantly greater than the thickness of the portion provided on the surface of the underlayer UML.
  • the silicon-containing layer SL is a layer that can function as part of an etching mask for the underlayer UML.
  • the silicon-containing layer SL is a deposit of an amorphous material containing silicon.
  • the silicon-containing layer SL has a first portion P1 located on a top surface TF of the resist layer RL and a second portion P2 located on a side surface SF of the resist layer RL.
  • the thickness T1 of the first portion P1 is greater than the thickness T2 of the second portion P2.
  • the thickness T1 may be 1 to 10 times the thickness T2.
  • the thickness T1 is, for example, 5 nm to 20 nm.
  • the silicon-containing layer SL may have the first portion P1 without the second portion P2. In other words, the silicon-containing layer SL may have only the first portion P1.
  • the third process gas includes a source gas including a silicon-containing gas and a diluent gas such as argon, helium, or nitrogen.
  • the third process gas may also include at least one additive gas selected from the group consisting of a halogen-containing gas such as Cl2 and a hydrogen-containing gas such as H2 , CH4 , or CHxF4 -X .
  • the silicon-containing gas may be silicon tetrafluoride ( SiF4 ), silicon tetrachloride ( SiCl4 ), Si2Cl6 , SIH4 , or Si2H6 .
  • the frequency of the source RF signal in step ST12 may be in the high frequency range (e.g., 10 MHz to 1 GHz) or in the low frequency range (e.g., 100 Hz to 100 kHz).
  • the RF power is, for example, 100 W to 1.5 kW.
  • the flow rate of the source gas contained in the third process gas is, for example, 2 sccm to 250 sccm.
  • the pressure in the plasma processing chamber 10 is, for example, 5 mTorr to 250 mTorr, and the temperature of the substrate W is 0°C to 120°C.
  • step ST12 the surface of the resist layer RL is first activated, and then silane is bonded to the surface. Silicon is then bonded to itself to form the silicon-containing layer SL on the surface of the resist layer RL in preference to the surface of the underlayer UML.
  • silane is then bonded to itself to form the silicon-containing layer SL on the surface of the resist layer RL in preference to the surface of the underlayer UML.
  • the silicon-containing layer SL may be formed without generating plasma in the plasma processing chamber 10.
  • the silicon-containing layer SL is formed by supplying a silicon-containing gas into the plasma processing chamber 10.
  • the silicon-containing layer SL is formed by, for example, a chemical vapor deposition method (CVD method).
  • CVD method chemical vapor deposition method
  • the silicon-containing layer SL may be exposed to a plasma PL generated from a gas containing hydrogen before performing the next step ST13.
  • a plasma PL generated from a gas containing hydrogen
  • the surface of the silicon-containing layer SL may be treated. Specifically, Si-H bonds are generated on the surface of the silicon-containing layer SL. In this case, metal is more likely to be deposited on the surface of the silicon-containing layer SL in the next step ST13.
  • gas containing hydrogen examples include hydrocarbons such as CH 4 and C 2 H 6 , hydrofluorocarbons such as CH 2 F 2 and CHF 3 , nitrogen-containing gases such as NH 3 , halogen-containing gases such as HF, HCl, HBr, and HI, and hydrogen.
  • hydrocarbons such as CH 4 and C 2 H 6
  • hydrofluorocarbons such as CH 2 F 2 and CHF 3
  • nitrogen-containing gases such as NH 3
  • halogen-containing gases such as HF, HCl, HBr, and HI
  • the silicon-containing layer SL may have a first deposition portion SL1 deposited on the surface of the resist layer RL and a second deposition portion SL2 deposited on the surface of the underlayer UML.
  • a part of the silicon-containing layer SL may be removed before performing the next step ST13.
  • trim etching is performed to remove the second deposition portion SL2 deposited on the surface of the underlayer UML.
  • step ST12A the silicon-containing layer SL is formed on the surface of the resist layer RL.
  • step ST12B the second deposition portion SL2 of the silicon-containing layer SL is removed.
  • step ST12B a part of the first deposition portion SL1 may be removed. Trim etching is, for example, plasma etching using fluorocarbon, fluorine, chlorine, or hydrogen bromide as an etchant. If the predetermined condition is satisfied after step ST12B (step ST12C: YES), the following step ST13 is performed.
  • steps ST12A and ST12B are performed again.
  • the predetermined condition is at least one of the thickness and shape of the first deposition portion SL1 of the silicon-containing layer SL. Note that from the second time onwards, either one of steps ST11B and ST12B may not be performed.
  • Step ST13 Formation of metal-containing layer 4C
  • a metal-containing layer ML is formed on the surface of the silicon-containing layer SL (step ST13).
  • the metal-containing layer ML is formed from a fourth process gas supplied into the plasma processing chamber 10.
  • the metal-containing layer ML is a layer that can function as an etching mask for the underlayer UML, and contains at least a metal.
  • the metal may contain at least one of tungsten and molybdenum.
  • the metal-containing layer ML contains at least one of W, WSi x , Mo, and MoSi x F Y (each of X and Y is a positive number).
  • the metal-containing layer ML may contain at least one of F and Cl as a trace element.
  • the trace element in the metal-containing layer ML may be an element whose content (mass ratio) is smaller than the content (mass ratio) of the metal in the metal-containing layer ML.
  • the thickness of the metal-containing layer ML may be uniform or non-uniform.
  • the metal-containing layer ML may be a layer in which a part of the silicon-containing layer SL is metal silicided, or may be a new layer formed on the silicon-containing layer SL. In the former case, the boundary between the metal-containing layer ML and the silicon-containing layer SL may be clear or unclear. In the latter case, the metal-containing layer ML is a layered deposit that includes a metal.
  • the metal-containing layer ML may be provided only on the surface of the silicon-containing layer SL, or may be provided on both the surface of the silicon-containing layer SL and the surface of the underlayer UML. In the latter case, the metal-containing layer ML may be formed preferentially on the surface of the silicon-containing layer SL rather than on the surface of the underlayer UML. In this case, the thickness of the portion provided on the surface of the silicon-containing layer SL may be significantly greater than the thickness of the portion provided on the surface of the underlayer UML. Forming the metal-containing layer ML preferentially on the surface of the silicon-containing layer SL rather than on the surface of the underlayer UML may correspond to selectively forming the metal-containing layer ML on the surface of the silicon-containing layer SL.
  • the fourth process gas includes a source gas containing a metal and a dilution gas such as argon, helium, or nitrogen.
  • the source gas may include fluorine.
  • the source gas may include at least one of tungsten hexafluoride (WF 6 ) gas, tungsten hexachloride (WCl 6 ) gas, and molybdenum pentafluoride (MoF 5 ) gas, for example.
  • the metal compound included in the source gas may include at least one of tungsten hexafluoride (WF 6 ), tungsten hexachloride (WCl 6 ), and molybdenum pentafluoride (MoF 5 ).
  • the fourth process gas may include H 2 or the like.
  • the metal-containing layer ML is formed by chemical vapor deposition (CVD) without generating plasma.
  • CVD chemical vapor deposition
  • the fourth process gas is supplied from the gas supply unit 20 into the plasma processing space 10s.
  • the substrate W is heated to 60° C. or higher by the temperature control module of the substrate support unit 11.
  • silicon located on the surface of the silicon-containing layer SL reacts thermochemically with the metal contained in the fourth process gas.
  • the silicon and the metal are bonded to form silicide.
  • the metal-containing layer ML derived from the silicide is formed.
  • the source RF signal may not be input in step ST13.
  • the RF power may be 0.
  • the DC voltage may be 0 V.
  • the flow rate of the source gas contained in the fourth process gas is, for example, 2 sccm to 250 sccm.
  • the pressure in the plasma processing chamber 10 is, for example, 10 mTorr to 250 mTorr, and the temperature of the substrate W is 60° C. to 130° C.
  • a metal-containing layer ML is formed by atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the metal-containing layer ML may be formed conformally or subconformally.
  • the ALD method is performed by repeating a cycle including the following first to fourth steps.
  • a precursor gas is supplied to the substrate W.
  • the plasma processing chamber 10 housing the substrate W is purged.
  • a reactive gas is supplied to the substrate W.
  • a plasma may be generated from the reactive gas.
  • the plasma processing chamber 10 is purged.
  • the cycle is, for example, 60 cycles or more and 100 cycles or less.
  • the precursor gas may be a source gas containing a metal, or may be the same as the fourth processing gas.
  • the reactive gas may include at least an oxygen-containing gas (e.g., oxygen radicals).
  • the reactive gas may include a dilution gas.
  • the source RF signal may not be input in step ST13. In this case, the RF power may be 0.
  • the DC voltage may be 0 V.
  • the flow rates of the precursor gas and the reactive gas are, for example, 2 sccm to 250 sccm.
  • the pressure in the plasma processing chamber 10 is, for example, 100 mTorr to 400 mTorr, and the temperature of the substrate W is 60° C. to 130° C.
  • the metal-containing layer ML is formed by plasma CVD.
  • a fourth processing gas is supplied from the gas supply unit 20 into the plasma processing space 10s.
  • a source RF signal is supplied to the upper electrode or the lower electrode. This generates a high-frequency electric field in the plasma processing space 10s, and plasma is generated from the fourth processing gas.
  • radicals containing the metal contained in the plasma are deposited on the surface of the silicon-containing layer SL.
  • the flow rate of the source gas contained in the fourth processing gas is, for example, 2 sccm or more and 250 sccm.
  • the metal-containing layer ML may be exposed to plasma PL generated from a gas containing hydrogen. This subjects the metal-containing layer ML to a surface treatment. In one example, the surface of the metal-containing layer ML is subjected to a reduction treatment. This may cause halogens to be released from the surface of the metal-containing layer ML.
  • the metal-containing layer ML may have a first deposition portion ML1 deposited on the surface of the silicon-containing layer SL and a second deposition portion ML2 deposited on the surface of the underlayer UML.
  • the second deposition portion SL2 tends to be formed.
  • a part of the metal-containing layer ML may be removed before performing step ST15 described later. For example, trim etching is performed to remove the second deposition portion ML2 deposited on the surface of the underlayer UML.
  • FIG. 10 is a flowchart of the method for forming the metal-containing layer.
  • the metal-containing layer ML is formed on the surface of the silicon-containing layer SL (step ST13A).
  • the second deposition portion SL2 of the metal-containing layer ML is removed (step ST13B).
  • a part of the first deposition portion ML1 may be removed.
  • the trim etching is, for example, plasma etching using fluorocarbon, fluorine, chlorine, or hydrogen bromide as an etchant.
  • step ST13C YES
  • step ST13C NO
  • steps ST13A and ST13B are performed again.
  • the above-mentioned predetermined condition is at least one of the thickness, shape, etc. of the first deposition portion ML1 of the metal-containing layer ML. Note that, from the second time onwards, either one of the steps ST13A and ST13B may not be performed.
  • step ST15 described below is performed.
  • steps ST12 and ST13 are performed again. This allows the underlayer UML to be etched well in step ST15 described below.
  • the predetermined condition is at least one of the thickness, shape, etc. of the structure including the resist layer RL, the silicon-containing layer SL, and the metal-containing layer ML.
  • Step ST15 Etching of Underlayer UML
  • the underlayer UML is etched using the resist layer RL, the silicon-containing layer SL, and the metal-containing layer ML as a mask (step ST15).
  • plasma is generated from a fifth processing gas supplied into the plasma processing chamber 10. Then, the part of the underlayer UML exposed from the resist layer RL, the silicon-containing layer SL, and the metal-containing layer ML is exposed to the plasma. This forms the underlayer UML having a pattern, and exposes a part of the base layer BL.
  • step ST15 the part of the base layer BL exposed from the underlayer UML may be etched in the plasma processing chamber 10, or may be etched by an etching device different from the different plasma processing device 1.
  • step ST15 not only the underlayer UML but also the metal-containing layer ML may be etched.
  • step ST15 the temperature (target temperature) of the substrate W may be adjusted by a temperature control module of the substrate support 11.
  • the fifth process gas includes, for example, a fluorine-based etchant, a chlorine-based etchant, or the like.
  • the fifth process gas includes, for example, a fluorocarbon gas, a hydrogen bromide gas, an oxygen gas, a carbon dioxide gas, a carbon monoxide gas, or the like.
  • the etching using plasma generated from the fifth process gas may be anisotropic etching.
  • the control unit 2 controls at least one of the temperature control module, gas supply unit 20, and plasma generation unit 12 of the substrate support unit 11 to form a silicon-containing layer SL on the surface of the resist layer RL in preference to the surface of the base layer UML.
  • the control unit 2 controls the temperature control module and gas supply unit 20 of the substrate support unit 11 to form a metal-containing layer ML on the surface of the silicon-containing layer SL.
  • the control unit 2 controls at least one of the temperature control module, gas supply unit 20, and plasma generation unit 12 of the substrate support unit 11 to etch the exposed base layer UML using the resist layer RL, silicon-containing layer SL, and metal-containing layer ML as a mask.
  • the method MT1 can improve the etching selectivity ratio. More specifically, the etching selectivity ratio of the underlayer UML to the mask including the resist layer RL, the silicon-containing layer SL, and the metal-containing layer ML can be improved. For example, when the outermost surface of the mask is the metal-containing layer ML, the etching resistance of the mask to the fifth process gas can be improved compared to when the outermost surface of the mask is the silicon-containing layer SL.
  • the metal-containing layer ML may be formed by chemical vapor deposition without generating plasma.
  • the metal-containing layer ML can be selectively formed on the silicon-containing layer SL. Therefore, the process of removing unnecessary metal-containing layer ML can be omitted.
  • the temperature of the substrate is controlled to 60°C or higher in step ST13, so that the thermochemical reaction occurs well.
  • the metal-containing layer ML may be formed by atomic layer deposition without generating plasma.
  • the thickness of the metal-containing layer ML can be controlled in atomic layer units. Therefore, the pattern of the underlayer UML can be formed with high precision.
  • the temperature of the substrate is controlled to 60°C or higher in step ST13, which makes it easier to form the metal-containing layer ML.
  • a resist layer RL is formed on the undercoat layer UML, and if at least one of the scums S1 to S3 is present on the substrate W after the resist layer RL is formed, the scums S1 to S3 on the substrate W may be removed. In this case, the occurrence of process defects caused by the scum can be suppressed.
  • the silicon-containing layer SL may be exposed to a plasma PL generated from a gas containing hydrogen.
  • the metal-containing layer ML is more likely to be formed on the surface of the silicon-containing layer SL.
  • a portion of the silicon-containing layer SL may be removed after step ST12 and before step ST13.
  • the portion of the underlayer UML that is not covered by the resist layer RL can be reliably exposed before step ST13.
  • the metal-containing layer ML may be exposed to plasma PL generated from a gas containing hydrogen. In this case, the etching resistance of the metal-containing layer ML can be improved.
  • a portion of the metal-containing layer ML may be removed after step ST13 and before step ST15.
  • the portion of the underlayer UML that is not covered by the resist layer RL and the silicon-containing layer SL can be reliably exposed before step S14.
  • the first modification is different from the above-described exemplary embodiment in that an additional film is formed between step ST13 and step ST15.
  • a deposition layer DL is formed on the surface of the metal-containing layer ML after step ST13 and before step ST15.
  • the deposition layer DL is, for example, a deposition of an amorphous material containing silicon, similar to the silicon-containing layer SL.
  • the deposition layer DL is formed by utilizing plasma generated from a third processing gas supplied into the plasma processing chamber 10.
  • the silicon-containing layer SL may be formed preferentially on the surface of the metal-containing layer ML rather than on the surface of the underlayer UML.
  • the deposition layer DL may be formed only on the surface of the metal-containing layer ML, or the deposition layer DL may be formed on both the surface of the metal-containing layer ML and the surface of the underlayer UML. In the latter case, a part of the deposition layer DL may be removed until the underlayer UML is exposed. In other words, in the latter case, trim etching may be performed.
  • step ST15 is performed.
  • the base layer UML is etched using the resist layer RL, the silicon-containing layer SL, the metal-containing layer ML, and the deposition layer DL as a mask.
  • the deposition layer DL is also etched.
  • the entire deposition layer DL may be etched.
  • the first modified example described above also achieves the same effects as the exemplary embodiment.
  • the mask can reliably function during step ST15, making etching defects less likely to occur.
  • a metal-containing layer may be formed on the surface of the deposition layer DL.
  • the metal-containing layer is formed in the same manner as in step ST13.
  • a further deposition layer may be formed.
  • a cycle of steps ST12 and ST13 may be repeatedly performed. The cycle is, for example, 60 cycles or more and 100 cycles or less.
  • the second modified example differs from the above exemplary embodiment in that a process other than the etching of the underlayer UML is performed in step ST15.
  • a process other than the etching of the underlayer UML is performed in step ST15.
  • step ST15 is interrupted and a deposition layer DL is formed on the surface of the metal-containing layer ML.
  • the deposition layer DL is formed in the same manner as in the first modified example. After the deposition layer DL is formed, step ST15 is resumed. As a result, the underlayer UML may be etched as shown in FIG. 12(c).
  • the second modified example described above also achieves the same effects as the exemplary embodiment described above. In addition, it is possible to suppress the occurrence of pattern formation defects after process ST15.
  • the second modified example and the first modified example may be combined.
  • the deposition layer DL and the metal-containing layer ML may be formed after interrupting step ST15.
  • a cycle of steps ST12 and ST13 may be performed after interrupting step ST15.
  • the cycle may be performed multiple times.
  • the third modification is different from the above exemplary embodiment in that a sputtering method is used in step ST13.
  • the surface of the Si top plate TP included in the upper electrode is cleaned (see FIG. 13(a)).
  • the surface of the Si top plate TP is cleaned by performing ion sputtering.
  • the surface of the Si top plate TP is cleaned by introducing a reducing gas such as hydrogen fluoride into the plasma processing space 10s. This removes an oxide film (not shown) that may be formed on the surface of the Si top plate TP, and cleans the surface.
  • a signal may be input to the first RF generating unit 31a, or a voltage may be applied to the second DC generating unit 32b.
  • the cleaning of the surface of the Si top plate TP may be performed instead of step ST12, and may also serve as the formation of a silicon-containing layer in step ST12.
  • a metal layer MAL is formed on the Si top plate TP.
  • a source gas containing a metal is introduced into the plasma processing space 10s. This causes a thermochemical reaction to form a metal layer MAL, which is an atomic layer of the metal, on the surface of the Si top plate TP.
  • a source gas containing a metal is introduced into the plasma processing space 10s. This causes a thermochemical reaction to form a metal layer MAL, which is an atomic layer of the metal, on the surface of the Si top plate TP.
  • the metal layer MAL is ion sputtered to form a metal-containing layer ML on the substrate W.
  • a signal is input to the first RF generating unit 31a, or a voltage is applied to the second DC generating unit 32b, to collide ions with the metal layer MAL in the plasma processing space 10s.
  • the metal-containing layer ML is formed on the surface of the silicon-containing layer SL included in the substrate W.
  • a cycle of the metal layer MAL formation process and the metal-containing layer ML formation process may be repeatedly performed. This allows the thickness of the metal-containing layer ML to be adjusted.
  • the above cycle is, for example, 60 cycles or more and 100 cycles or less.
  • the trim etching may be performed. After the above steps, step S14 is performed.
  • the third modified example described above also achieves the same effects as the above exemplary embodiment.
  • the ratio of metal contained in the metal-containing layer ML can be increased, the etching resistance of the metal-containing layer ML can be improved.
  • the thickness of the metal-containing layer ML can be precisely adjusted.
  • method MT may be performed using a plasma processing apparatus different from plasma processing apparatus 1.
  • [E1] (a) providing a substrate comprising a first layer and a second layer having a pattern on the first layer; (b) forming a silicon-containing layer on a surface of the second layer in preference to a surface of the first layer; (c) forming a metal-containing layer on a surface of the silicon-containing layer; (d) etching the exposed first layer using the second layer, the silicon-containing layer, and the metal-containing layer as a mask; An etching method comprising:
  • the silicon-containing layer has a first portion located on a top surface of the second layer and a second portion located on a side surface of the second layer;
  • the etching method according to any one of [E1] to [E11], wherein the thickness of the first portion is greater than the thickness of the second portion.
  • the metal-containing layer includes at least one of W, WSi x , Mo, and MoSi x F Y ;
  • a chamber a substrate support provided in the chamber and having a temperature control module; a gas supply configured to supply a process gas into the chamber; a plasma generating unit configured to generate a plasma from the process gas in the chamber; A control unit; Equipped with The control unit, in a state where a substrate including a first layer and a second layer having a pattern on the first layer is supported by the substrate support unit, forming a silicon-containing layer on a surface of the second layer in preference to a surface of the first layer; forming a metal-containing layer on a surface of the silicon-containing layer; etching the exposed first layer using the second layer, the silicon-containing layer, and the metal-containing layer as a mask; A configuration is provided to control the temperature control module, the gas supply unit, and the plasma generation unit. Plasma processing equipment.
  • 1...plasma processing apparatus 2...control section, 10...plasma processing chamber, 11...substrate support section, 12...plasma generation section, 20...gas supply section, DL...deposition layer, ML...metal-containing layer, P1...first portion, P2...second portion, RL...resist layer, SF...side surface, SL...silicon-containing layer, TF...top surface, UML...undercoat layer.

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PCT/JP2024/004407 2023-02-21 2024-02-08 エッチング方法及びプラズマ処理装置 Ceased WO2024176864A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005012159A (ja) * 2003-06-20 2005-01-13 Hynix Semiconductor Inc 半導体素子のゲート電極形成方法
US20210183656A1 (en) * 2019-12-17 2021-06-17 Tokyo Electron Limited Methods of patterning small features
JP2022542089A (ja) * 2019-07-31 2022-09-29 ラム リサーチ コーポレーション Ｍｒａｍパターニングのための不揮発性材料の化学エッチング
WO2023282191A1 (ja) * 2021-07-05 2023-01-12 東京エレクトロン株式会社 基板処理方法及び基板処理装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005012159A (ja) * 2003-06-20 2005-01-13 Hynix Semiconductor Inc 半導体素子のゲート電極形成方法
JP2022542089A (ja) * 2019-07-31 2022-09-29 ラム リサーチ コーポレーション Ｍｒａｍパターニングのための不揮発性材料の化学エッチング
US20210183656A1 (en) * 2019-12-17 2021-06-17 Tokyo Electron Limited Methods of patterning small features
WO2023282191A1 (ja) * 2021-07-05 2023-01-12 東京エレクトロン株式会社 基板処理方法及び基板処理装置

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