WO2024176641A1 - 固体撮像装置及び電子機器 - Google Patents

固体撮像装置及び電子機器 Download PDF

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Publication number
WO2024176641A1
WO2024176641A1 PCT/JP2024/000469 JP2024000469W WO2024176641A1 WO 2024176641 A1 WO2024176641 A1 WO 2024176641A1 JP 2024000469 W JP2024000469 W JP 2024000469W WO 2024176641 A1 WO2024176641 A1 WO 2024176641A1
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WIPO (PCT)
Prior art keywords
substrate
pixel
imaging device
transistor
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/JP2024/000469
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English (en)
French (fr)
Japanese (ja)
Inventor
貴志 町田
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to EP24759949.1A priority Critical patent/EP4672339A1/en
Priority to JP2025502155A priority patent/JPWO2024176641A1/ja
Priority to CN202480012507.0A priority patent/CN120693990A/zh
Priority to KR1020257030702A priority patent/KR20250154420A/ko
Publication of WO2024176641A1 publication Critical patent/WO2024176641A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/809—Constructional details of image sensors of hybrid image sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/53—Control of the integration time
    • H04N25/532—Control of the integration time by controlling global shutters in CMOS SSIS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections

Definitions

  • This disclosure relates to solid-state imaging devices and electronic devices.
  • Solid-state imaging devices using photodiodes are widely used.
  • this potential difference is applied to the transistors of the pixel circuit on the same substrate.
  • the transistor size must be increased, but this results in a problem of increasing the area occupied by the transistors in the layout.
  • problems such as a deterioration in reliability and hot carrier emission occur.
  • one of the non-limiting problems that the embodiments of the present disclosure aim to solve is to make the ground potential different in an imaging device formed from stacked semiconductors.
  • the problems that the embodiments of the present disclosure aim to solve can also be, as some further non-limiting examples, problems that correspond to the effects described in the embodiments.
  • a problem that corresponds to at least one of the effects described in the description of the embodiments of the present disclosure can be considered to be a problem that the present disclosure aims to solve.
  • a solid-state imaging device includes a first substrate and a second substrate.
  • the first substrate is A light receiving element that outputs a signal based on the intensity of the received light
  • the ground potential is a first ground potential.
  • the second substrate is a transistor that outputs a signal based on a signal output from the light receiving element;
  • the ground potential is a second ground potential different from the first ground potential.
  • the second ground potential may be a more positive potential than the first ground potential.
  • the first ground potential may be a negative bias potential.
  • the second ground potential may be 0 [V].
  • the second substrate may include an amplifier transistor that amplifies the signal output by the light receiving element.
  • the thickness of the gate oxide film of the transistor provided on the second substrate may be thinner than the thickness of the gate oxide film provided on the first substrate.
  • the first substrate and the second substrate may be electrically connected via a metal.
  • the metal may be copper.
  • the distance between the wirings on the second substrate may be shorter than the distance between the wirings on the first substrate.
  • the first substrate and the second substrate may be formed by stacking them.
  • the device may further include a third substrate, which may form a pixel unit together with the first substrate and the second substrate.
  • the signal acquired by the light receiving element may be converted into an image signal using a charge domain type global shutter method.
  • the signal acquired by the light receiving element may be converted into an image signal using a voltage domain type global shutter method.
  • the signal acquired by the light receiving element may be converted to a digital signal by an analog-to-digital conversion circuit provided for each light receiving element.
  • the amplifying transistor may have a well potential and a source potential that are equal and different from the second ground potential.
  • the solid-state imaging device includes any of the solid-state imaging devices described above.
  • FIG. 1 is a block diagram illustrating an example of a functional configuration of an imaging apparatus according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic plan view illustrating a schematic configuration of the imaging device illustrated in FIG. Schematic diagram showing the cross-sectional structure along line III-III' shown in Figure 2.
  • FIG. 2 is an equivalent circuit diagram of the pixel sharing unit shown in FIG. 4 is a diagram showing an example of a connection mode between a plurality of pixel sharing units and a plurality of vertical signal lines; 4 is a schematic cross-sectional view illustrating an example of a specific configuration of the imaging device illustrated in FIG. 3.
  • 7 is a schematic diagram showing an example of a planar configuration of a main part of the first substrate shown in FIG. 6.
  • 7B is a schematic diagram showing a planar configuration of a pad portion together with a main portion of the first substrate shown in FIG. 7A.
  • 7 is a schematic diagram showing an example of a planar configuration of a pixel circuit and a main part of a first substrate together with the first wiring layer shown in FIG. 6.
  • 7 is a schematic diagram illustrating an example of a planar configuration of the first wiring layer and the second wiring layer illustrated in FIG. 6.
  • 7 is a schematic diagram illustrating an example of a planar configuration of the second wiring layer and the third wiring layer illustrated in FIG. 6.
  • FIG. 7 is a schematic diagram illustrating an example of a planar configuration of a third wiring layer and a fourth wiring layer illustrated in FIG. 6.
  • 4 is a schematic diagram for explaining a path of an input signal to the imaging device shown in FIG. 3.
  • 4 is a schematic diagram for explaining a signal path of a pixel signal in the imaging device shown in FIG. 3.
  • 16 is a schematic diagram showing a planar configuration of a first wiring layer and a main part of a first substrate together with the pixel circuit shown in FIG. 15.
  • 17 is a schematic diagram showing an example of a planar configuration of a second wiring layer together with the first wiring layer shown in FIG. 16.
  • FIG. 18 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 17.
  • 19 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 18.
  • FIG. 7B is a schematic diagram illustrating a modified example of the planar configuration of the first substrate shown in FIG. 7A.
  • 22 is a schematic diagram showing an example of a planar configuration of a first wiring layer together with the pixel circuit shown in FIG. 21.
  • FIG. 23 is a schematic diagram showing an example of a planar configuration of a second wiring layer together with the first wiring layer shown in FIG. 22.
  • 24 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 23.
  • 25 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 24.
  • 21 is a schematic diagram illustrating another example of the planar configuration of the first substrate shown in FIG. 20.
  • 28 is a schematic diagram showing an example of a planar configuration of a first wiring layer together with the pixel circuit shown in FIG.
  • FIG. 29 is a schematic diagram showing an example of a planar configuration of a second wiring layer together with the first wiring layer shown in FIG. 28.
  • 30 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 29.
  • 31 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 30.
  • 4 is a schematic cross-sectional view illustrating another example of the imaging device illustrated in FIG. 3.
  • 33 is a schematic diagram for explaining a path of an input signal to the imaging device shown in FIG. 32.
  • 33 is a schematic diagram for explaining a signal path of a pixel signal in the imaging device shown in FIG. 32.
  • FIG. 7 is a schematic cross-sectional view illustrating another example of the imaging device illustrated in FIG. 6.
  • FIG. 5 is a diagram illustrating another example of the equivalent circuit shown in FIG.
  • FIG. 7B is a schematic plan view illustrating another example of the pixel separating portion shown in FIG. 7A etc.
  • FIG. 2 is a diagram illustrating an example of an equivalent circuit according to an embodiment.
  • FIG. 2 is a diagram illustrating an example of an equivalent circuit according to an embodiment.
  • FIG. 2 is a diagram illustrating an example of an equivalent circuit according to an embodiment.
  • FIG. 2 is a diagram illustrating a potential diagram of an equivalent circuit according to an embodiment.
  • FIG. 13 is a diagram illustrating an example of a substrate configuration when a ground potential is changed according to an embodiment.
  • FIG. 13 is a diagram illustrating an example of a substrate configuration when a ground potential is changed according to an embodiment.
  • FIG. 13 is a diagram illustrating an example of a substrate configuration when a ground potential is changed according to an embodiment.
  • FIG. 13 is a diagram illustrating an example of a substrate configuration when a ground potential is changed according to an embodiment.
  • FIG. 2 is a diagram illustrating an example of a substrate configuration when a ground potential is changed according to an embodiment.
  • FIG. 2 is a diagram illustrating an example of the configuration of an equivalent circuit according to an embodiment.
  • FIG. 2 is a diagram illustrating an example of the configuration of an equivalent circuit according to an embodiment.
  • FIG. 2 is a diagram illustrating an example of the configuration of an equivalent circuit according to an embodiment.
  • FIG. 2 is a diagram illustrating an example of the configuration of an equivalent circuit according to an embodiment.
  • FIG. 2 is a diagram illustrating an example of the configuration of an equivalent circuit according to an embodiment.
  • FIG. 2 is a diagram illustrating an example of the configuration of an equivalent circuit according to an embodiment.
  • FIG. 2 is a diagram illustrating an example of the configuration of an equivalent circuit according to an embodiment.
  • FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging system including an imaging device according to the above embodiment and its modified example.
  • 54 is a diagram showing an example of an imaging procedure of the imaging system shown in FIG. 53.
  • FIG. 1 is a block diagram showing an example of a schematic configuration of a vehicle control system.
  • FIG. 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.
  • FIG. 1 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.
  • FIG. 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU.
  • imaging device can also be interpreted as, for example, a solid-state imaging device.
  • Embodiment Image capture device having a stacked structure of three substrates
  • Modification 1 Plant Configuration Example 1
  • Modification 2 Plant Configuration Example 2)
  • Modification 3 Plant Configuration Example 3)
  • Modification 4 Example in which a contact part between substrates is provided in the center of the pixel array part
  • Modification 5 Example having planar type transfer transistor
  • Modification 6 Example in which one pixel is connected to one pixel circuit
  • Modification 7 Example of the configuration of the pixel separation unit
  • Modification 8 (Configuration Example 1 of Ground Potential of Board) 10.
  • Modification 9 Example of the structure in the cross section of the substrate)
  • Modification 10 Configuration Example 2 of Ground Potential of Board
  • Application Examples Imaging Systems
  • FIG. 1 is a block diagram showing an example of a functional configuration of an imaging device (imaging device 1) according to an embodiment of the present disclosure.
  • the imaging device 1 in FIG. 1 includes, for example, an input section 510A, a row driver section 520, a timing control section 530, a pixel array section 540, a column signal processing section 550, an image signal processing section 560, and an output section 510B.
  • pixels 541 are repeatedly arranged in an array. More specifically, pixel sharing units 539 each including a plurality of pixels are repeated in an array having row and column directions. For convenience, the row direction may be referred to as the H direction and the column direction perpendicular to the row direction as the V direction in this specification.
  • one pixel sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, 541D). Each of pixels 541A, 541B, 541C, 541D has a photodiode PD (shown in FIG. 6, etc., described later).
  • the pixel sharing unit 539 is a unit that shares one pixel circuit (pixel circuit 210 in FIG. 3, described later).
  • each of the four pixels has one pixel circuit (pixel circuit 210, described below).
  • the pixel signals of each of the pixels 541A, 541B, 541C, 541D are sequentially read out.
  • the pixels 541A, 541B, 541C, 541D are arranged, for example, in 2 rows x 2 columns.
  • the pixel array section 540 is provided with the pixels 541A, 541B, 541C, 541D as well as a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column readout lines) 543.
  • the row driving signal line 542 drives the pixels 541 included in each of the pixel sharing units 539 arranged in a row in the pixel array section 540.
  • the row driving signal line 542 drives each pixel arranged in a row in the pixel sharing unit 539.
  • the pixel sharing unit 539 is provided with a plurality of transistors. To drive each of the plurality of transistors, a plurality of row driving signal lines 542 are connected to one pixel sharing unit 539.
  • the pixel sharing unit 539 is connected to a vertical signal line (column readout line) 543. Pixel signals are read out from each of the pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539 via the vertical signal line (column readout line) 543.
  • the row driver 520 includes, for example, a row address control section that determines the position of the row for driving the pixels, in other words, a row decoder section, and a row driver circuit section that generates signals for driving the pixels 541A, 541B, 541C, and 541D.
  • the column signal processing unit 550 includes, for example, a load circuit unit connected to the vertical signal line 543 and forming a source follower circuit with the pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539).
  • the column signal processing unit 550 may include an amplifier circuit unit that amplifies a signal read out from the pixel sharing unit 539 via the vertical signal line 543.
  • the column signal processing unit 550 may include a noise processing unit. In the noise processing unit, for example, a system noise level is removed from the signal read out from the pixel sharing unit 539 as a result of photoelectric conversion.
  • the column signal processing unit 550 has, for example, an analog-digital converter (ADC).
  • ADC analog-digital converter
  • the ADC includes, for example, a comparator unit and a counter unit.
  • the comparator unit the analog signal to be converted is compared with a reference signal to be compared with the analog signal.
  • the counter unit the time until the comparison result in the comparator unit is inverted is measured.
  • the column signal processing unit 550 may include a horizontal scanning circuit unit that controls scanning of the readout column.
  • the timing control unit 530 supplies signals that control timing to the row driving unit 520 and column signal processing unit 550 based on the reference clock signal and timing control signal input to the device.
  • the image signal processing unit 560 is a circuit that performs various signal processing on the data obtained as a result of photoelectric conversion, in other words, the data obtained as a result of the imaging operation in the imaging device 1.
  • the image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit.
  • the image signal processing unit 560 may also include a processor unit.
  • One example of signal processing executed in the image signal processing unit 560 is a tone curve correction process that gives the AD converted imaging data more gradation when the data is of a dark subject, and less gradation when the data is of a bright subject.
  • the input section 510A is for inputting, for example, the above-mentioned reference clock signal, timing control signal, characteristic data, etc. from outside the device to the imaging device 1.
  • the timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal.
  • the characteristic data is, for example, for storage in the data holding section of the image signal processing section 560.
  • the input section 510A includes, for example, an input terminal 511, an input circuit section 512, an input amplitude change section 513, an input data conversion circuit section 514, and a power supply section (not shown).
  • the input terminal 511 is an external terminal for inputting data.
  • the input circuit section 512 is for taking in the signal input to the input terminal 511 into the inside of the imaging device 1.
  • the input amplitude change section 513 changes the amplitude of the signal taken in by the input circuit section 512 to an amplitude that is easily usable inside the imaging device 1.
  • the input data conversion circuit section 514 changes the arrangement of the data string of the input data.
  • the input data conversion circuit section 514 is, for example, configured with a serial-parallel conversion circuit. In this serial-parallel conversion circuit, a serial signal received as input data is converted into a parallel signal. Note that the input amplitude change section 513 and the input data conversion circuit section 514 may be omitted from the input section 510A.
  • the power supply section supplies power set to various voltages required inside the imaging device 1 based on power supplied from the outside to the imaging device 1.
  • the input section 510A may be provided with a memory interface circuit that receives data from the external memory device.
  • the external memory device may be, for example, a flash memory, an SRAM, or a DRAM.
  • the output section 510B outputs image data to the outside of the device.
  • This image data is, for example, image data captured by the imaging device 1 and image data that has been signal-processed by the image signal processing section 560.
  • the output section 510B includes, for example, an output data conversion circuit section 515, an output amplitude change section 516, an output circuit section 517, and an output terminal 518.
  • the output data conversion circuit section 515 is, for example, configured with a parallel-serial conversion circuit, and the output data conversion circuit section 515 converts the parallel signal used inside the imaging device 1 into a serial signal.
  • the output amplitude change section 516 changes the amplitude of the signal used inside the imaging device 1. The signal with the changed amplitude becomes easier to use in an external device connected to the outside of the imaging device 1.
  • the output circuit section 517 is a circuit that outputs data from inside the imaging device 1 to the outside of the device, and the output circuit section 517 drives wiring outside the imaging device 1 connected to the output terminal 518.
  • the output terminal 518 outputs data from the imaging device 1 to the outside of the device.
  • the output data conversion circuit section 515 and the output amplitude change section 516 may be omitted.
  • the output section 510B may be provided with a memory interface circuit that outputs data to the external memory device.
  • the external memory device may be, for example, a flash memory, an SRAM, or a DRAM.
  • FIG. 2 shows a schematic planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300
  • FIG. 3 shows a schematic cross-sectional configuration of the first substrate 100, the second substrate 200, and the third substrate 300 stacked together.
  • FIG. 3 corresponds to the cross-sectional configuration along line III-III' shown in FIG. 2.
  • the imaging device 1 is a three-dimensional imaging device formed by bonding together three substrates (the first substrate 100, the second substrate 200, and the third substrate 300).
  • the first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T.
  • the second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T.
  • the third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T.
  • the wiring layer (100T, 200T, 300T) provided on each substrate (the first substrate 100, the second substrate 200, and the third substrate 300).
  • the first substrate 100, the second substrate 200, and the third substrate 300 are laminated in this order, and the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S are arranged in this order along the lamination direction.
  • the specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later.
  • the arrows shown in FIG. 3 indicate the direction of incidence of light L into the imaging device 1.
  • the light incident side of the imaging device 1 may be called “bottom", “lower side”, or “lower”, and the opposite side to the light incident side may be called “upper", "upper side", or "upper”.
  • the wiring layer side may be called the front side
  • the semiconductor layer side may be called the back side. Note that the description in the specification is not limited to the above-mentioned nomenclature.
  • the imaging device 1 is, for example, a back-illuminated imaging device in which light is incident from the back side of a first substrate 100 having a photodiode.
  • the pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are both configured using both the first substrate 100 and the second substrate 200.
  • the first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, 541D of the pixel sharing unit 539.
  • Each of these pixels 541 has a photodiode (photodiode PD, described below) and a transfer transistor (transfer transistor TR, described below).
  • the second substrate 200 is provided with a pixel circuit (pixel circuit 210, described below) of the pixel sharing unit 539.
  • the pixel circuit reads out pixel signals transferred from the photodiodes of the pixels 541A, 541B, 541C, 541D via the transfer transistor, or resets the photodiodes.
  • the second substrate 200 has a plurality of row driving signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction.
  • the second substrate 200 further has a power supply line 544 extending in the row direction.
  • the third substrate 300 has, for example, an input section 510A, a row driving section 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B.
  • the row driving section 520 is provided, for example, in an area that partially overlaps with the pixel array section 540 in the stacking direction (hereinafter simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row driver section 520 is provided in a region overlapping the vicinity of the end of the pixel array section 540 in the H direction in the stacking direction ( FIG. 2 ).
  • the column signal processor section 550 is provided, for example, in a region partially overlapping the pixel array section 540 in the stacking direction. More specifically, the column signal processor section 550 is provided in a region overlapping the vicinity of the end of the pixel array section 540 in the V direction in the stacking direction ( FIG. 2 ).
  • the input section 510A and the output section 510B may be disposed in a portion other than the third substrate 300, for example, on the second substrate 200.
  • the input section 510A and the output section 510B may be provided on the back surface (light incident surface) side of the first substrate 100.
  • the pixel circuits provided on the second substrate 200 are also referred to as pixel transistor circuits, pixel transistor groups, pixel transistors, pixel readout circuits, or readout circuits. In this specification, they are referred to as pixel circuits.
  • the first substrate 100 and the second substrate 200 are electrically connected by, for example, through electrodes (through electrodes 120E, 121E in FIG. 6 described below).
  • the second substrate 200 and the third substrate 300 are electrically connected by, for example, contact portions 201, 202, 301, 302.
  • the second substrate 200 is provided with contact portions 201, 202, and the third substrate 300 is provided with contact portions 301, 302.
  • the contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300.
  • the second substrate 200 has a contact region 201R in which a plurality of contact portions 201 are provided, and a contact region 202R in which a plurality of contact portions 202 are provided.
  • the third substrate 300 has a contact region 301R in which a plurality of contact portions 301 are provided, and a contact region 302R in which a plurality of contact portions 302 are provided.
  • the contact regions 201R, 301R are provided between the pixel array section 540 and the row driver section 520 in the stacking direction ( FIG. 3 ).
  • the contact regions 201R, 301R are provided, for example, in a region where the row driver section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap in the stacking direction, or in a region adjacent thereto.
  • the contact regions 201R, 301R are disposed, for example, at the ends of such regions in the H direction (FIG. 2).
  • the contact region 301R is provided at a position overlapping a part of the row driver 520, specifically the end of the row driver 520 in the H direction (FIGS. 2 and 3).
  • the contact sections 201, 301 connect, for example, the row driver 520 provided on the third substrate 300 to the row driver line 542 provided on the second substrate 200.
  • the contact sections 201, 301 may connect, for example, the input section 510A provided on the third substrate 300 to the power supply line 544 and the reference potential line (reference potential line VSS, described later).
  • the contact regions 202R, 302R are provided between the pixel array section 540 and the column signal processing section 550 in the stacking direction (FIG. 3).
  • the contact regions 202R, 302R are provided, for example, in a region where the column signal processing section 550 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap in the stacking direction, or in a region adjacent thereto.
  • the contact regions 202R, 302R are disposed, for example, at the end in the V direction of such a region (FIG. 2).
  • the contact region 301R is provided in a position overlapping a part of the column signal processing section 550, specifically, the end in the V direction of the column signal processing section 550 (FIGS. 2 and 3).
  • the contact sections 202, 302 are for connecting pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion in the photodiodes) output from each of the multiple pixel sharing units 539 in the pixel array section 540, for example, to a column signal processing section 550 provided on the third substrate 300.
  • the pixel signals are sent from the second substrate 200 to the third substrate 300.
  • the imaging device 1 has an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300.
  • the contact portions 201, 202, 301, and 302 are formed by electrodes made of a conductive material.
  • the conductive material is made of a metal material such as copper (CU), aluminum (AL), or gold (AU).
  • the contact regions 201R, 202R, 301R, 302R electrically connect the second substrate and the third substrate by, for example, directly joining wiring formed as electrodes, and enable input and/or output of signals between the second substrate 200 and the third substrate 300.
  • the electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided at a desired location. For example, as described as contact regions 201R, 202R, 301R, and 302R in FIG. 3, it may be provided in a region that overlaps with the pixel array section 540 in the stacking direction.
  • the electrical connection portion may also be provided in a region that does not overlap with the pixel array section 540 in the stacking direction. Specifically, it may be provided in a region that overlaps with a peripheral portion disposed outside the pixel array section 540 in the stacking direction.
  • connection holes H1, H2 penetrate the first substrate 100 and the second substrate 200 (FIG. 3).
  • the connection holes H1, H2 are provided outside the pixel array section 540 (or a portion overlapping the pixel array section 540) (FIG. 2).
  • the connection hole H1 is disposed outside the pixel array section 540 in the H direction
  • the connection hole H2 is disposed outside the pixel array section 540 in the V direction.
  • the connection hole H1 reaches the input section 510A provided on the third substrate 300
  • the connection hole H2 reaches the output section 510B provided on the third substrate 300.
  • connection holes H1, H2 may be hollow or may contain a conductive material at least in part.
  • a bonding wire may be connected to an electrode formed as the input section 510A and/or the output section 510B.
  • an electrode formed as the input section 510A and/or the output section 510B may be connected to a conductive material provided in the connection holes H1, H2.
  • the conductive material provided in the connection holes H1, H2 may be embedded in part or all of the connection holes H1, H2, or the conductive material may be formed on the side walls of the connection holes H1, H2.
  • the input section 510A and the output section 510B are provided on the third substrate 300, but the present invention is not limited to this structure.
  • the input section 510A and/or the output section 510B can be provided on the second substrate 200 by sending signals from the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T.
  • the input section 510A and/or the output section 510B can be provided on the first substrate 100 by sending signals from the second substrate 200 to the first substrate 100 via the wiring layers 100T and 200T.
  • FIG 4 is an equivalent circuit diagram showing an example of the configuration of a pixel sharing unit 539.
  • the pixel sharing unit 539 includes a plurality of pixels 541 (in Figure 4, four pixels 541 are shown: pixels 541A, 541B, 541C, and 541D), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210.
  • the pixel circuit 210 includes, for example, four transistors, specifically, an amplifying transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.
  • the pixel sharing unit 539 operates one pixel circuit 210 in a time-division manner, thereby sequentially outputting pixel signals of each of the four pixels 541 (pixels 541A, 541B, 541C, 541D) included in the pixel sharing unit 539 to the vertical signal line 543.
  • a configuration in which one pixel circuit 210 is connected to multiple pixels 541 and the pixel signals of the multiple pixels 541 are output by one pixel circuit 210 in a time-division manner is referred to as "multiple pixels 541 sharing one pixel circuit 210."
  • Pixels 541A, 541B, 541C, and 541D have components in common.
  • the identification number 1 is added to the end of the reference numeral of the component of pixel 541A
  • the identification number 2 is added to the end of the reference numeral of the component of pixel 541B
  • the identification number 3 is added to the end of the reference numeral of the component of pixel 541C
  • the identification number 4 is added to the end of the reference numeral of the component of pixel 541D.
  • the identification numbers at the end of the reference numerals of the components of pixels 541A, 541B, 541C, and 541D are omitted.
  • the pixels 541A, 541B, 541C, and 541D each have, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR.
  • the photodiodes PD (PD1, PD2, PD3, and PD4) have cathodes electrically connected to the sources of the transfer transistors TR, and anodes electrically connected to a reference potential line (for example, ground).
  • the photodiodes PD photoelectrically convert the incident light and generate a charge according to the amount of light received.
  • the transfer transistors TR are, for example, N-type CMOS (Complementary Metal-Oxide-Semiconductor) transistors.
  • the drain is electrically connected to the floating diffusion FD, and the gate is electrically connected to a drive signal line.
  • This drive signal line is one of the multiple row drive signal lines 542 (see Figure 1) connected to one pixel sharing unit 539.
  • the transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion FD.
  • the floating diffusion FD (floating diffusions FD1, FD2, FD3, FD4) are N-type diffusion layer regions formed in a P-type semiconductor layer.
  • the floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is also a charge-voltage conversion means that generates a voltage according to the amount of charge.
  • the four floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) included in one pixel-sharing unit 539 are electrically connected to each other and to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG.
  • the drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line.
  • This drive signal line is one of the multiple row drive signal lines 542 connected to one pixel-sharing unit 539.
  • the drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line.
  • This drive signal line is one of the multiple row drive signal lines 542 connected to one pixel-sharing unit 539.
  • the gate of the amplifying transistor AMP is connected to the floating diffusion FD, the drain of the amplifying transistor AMP is connected to the power supply line VDD, and the source of the amplifying transistor AMP is connected to the drain of the selection transistor SEL.
  • the source of the selection transistor SEL is connected to a vertical signal line 543, and the gate of the selection transistor SEL is connected to a drive signal line.
  • This drive signal line is one of multiple row drive signal lines 542 connected to one pixel sharing unit 539.
  • the transfer transistor TR When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD.
  • the gate (transfer gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and is provided extending from the surface of the semiconductor layer (semiconductor layer 100S in FIG. 6 described later) to a depth reaching the PD, as shown in FIG. 6 described later.
  • the reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD.
  • the selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210.
  • the amplification transistor AMP generates a pixel signal with a voltage corresponding to the level of the charge held in the floating diffusion FD.
  • the amplification transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL.
  • This amplification transistor AMP constitutes a source follower in the column signal processing section 550 together with a load circuit section (see Figure 1) connected to the vertical signal line 543.
  • the selection transistor SEL When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing section 550 via the vertical signal line 543.
  • the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type CMOS transistors.
  • the FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion in the floating diffusion FD.
  • pixel signals are small when shooting in dark places.
  • the pixel signal is large, so if the FD capacitance C is not large, the floating diffusion FD will not be able to receive the charge of the photodiode PD.
  • the FD capacitance C needs to be large so that the V when converted to voltage by the amplifier transistor AMP does not become too large (in other words, to become small).
  • the FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.
  • the pixel circuit 210 is composed of three transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST.
  • the pixel circuit 210 has at least one pixel transistor, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.
  • the selection transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP.
  • the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL.
  • the source of the selection transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (see FIG. 1).
  • the source of the amplifier transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST.
  • the number of pixels 541 sharing one pixel circuit 210 may be other than four. For example, two or eight pixels 541 may share one pixel circuit 210.
  • FIG. 5 shows an example of a connection between multiple pixel sharing units 539 and vertical signal lines 543.
  • four pixel sharing units 539 arranged in a column direction are divided into four groups, and a vertical signal line 543 is connected to each of the four groups.
  • FIG. 5 shows an example in which each of the four groups has one pixel sharing unit 539, but each of the four groups may include multiple pixel sharing units 539.
  • multiple pixel sharing units 539 arranged in a column direction may be divided into groups including one or multiple pixel sharing units 539.
  • each of the groups is connected to a vertical signal line 543 and a column signal processing circuit 550, so that pixel signals can be read out simultaneously from each group.
  • one vertical signal line 543 may be connected to multiple pixel sharing units 539 arranged in a column direction. At this time, pixel signals are read out sequentially in a time-division manner from multiple pixel sharing units 539 connected to one vertical signal line 543.
  • FIG. 6 shows an example of a cross-sectional configuration of the first substrate 100, the second substrate 200, and the third substrate 300 of the imaging device 1 in a direction perpendicular to the main surfaces.
  • FIG. 6 is a schematic representation for easy understanding of the positional relationship of the components, and may differ from the actual cross section.
  • the imaging device 1 further has a light receiving lens 401 on the back side (light incident surface side) of the first substrate 100.
  • a color filter layer (not shown) may be provided between the light receiving lens 401 and the first substrate 100.
  • the light receiving lens 401 is provided, for example, for each of the pixels 541A, 541B, 541C, and 541D.
  • the imaging device 1 is, for example, a back-illuminated imaging device.
  • the imaging device 1 has a pixel array section 540 arranged in the center and a peripheral section 540B arranged outside the pixel array section 540.
  • the first substrate 100 has, in order from the light receiving lens 401 side, an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T.
  • the semiconductor layer 100S is, for example, made of a silicon substrate.
  • the semiconductor layer 100S has, for example, a P-well layer 115 in and near a part of the surface (the surface on the wiring layer 100T side), and has an N-type semiconductor region 114 in the other region (region deeper than the P-well layer 115).
  • a PN junction type photodiode PD is formed by the N-type semiconductor region 114 and the P-well layer 115.
  • the P-well layer 115 is a P-type semiconductor region.
  • FIG. 7A shows an example of the planar configuration of the first substrate 100.
  • FIG. 7A mainly shows the planar configuration of the pixel separation section 117, photodiode PD, floating diffusion FD, VSS contact region 118, and transfer transistor TR of the first substrate 100.
  • the configuration of the first substrate 100 will be explained using FIG. 7A together with FIG. 6.
  • a floating diffusion FD and a VSS contact region 118 are provided near the surface of the semiconductor layer 100S.
  • the floating diffusion FD is composed of an N-type semiconductor region provided in the P-well layer 115.
  • the floating diffusion FD (floating diffusions FD1, FD2, FD3, FD4) of each of the pixels 541A, 541B, 541C, and 541D are provided adjacent to each other, for example, in the center of the pixel sharing unit 539 ( Figure 7A).
  • the four floating diffusions (floating diffusions FD1, FD2, FD3, FD4) included in this shared unit 539 are electrically connected to each other within the first substrate 100 (more specifically, within the wiring layer 100T) via electrical connection means (pad portion 120 described below).
  • the floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via electrical means (through electrode 120E described below).
  • the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG by this electrical means.
  • the VSS contact region 118 is an area electrically connected to the reference potential line VSS and is arranged at a distance from the floating diffusion FD.
  • the floating diffusion FD is arranged at one end of each pixel in the V direction, and the VSS contact region 118 is arranged at the other end ( Figure 7A).
  • the VSS contact region 118 is, for example, composed of a P-type semiconductor region.
  • the VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. This supplies a reference potential to the semiconductor layer 100S.
  • the first substrate 100 is provided with a photodiode PD, a floating diffusion FD, a VSS contact region 118, and a transfer transistor TR.
  • the photodiode PD, the floating diffusion FD, the VSS contact region 118, and the transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D.
  • the transfer transistor TR is provided on the front surface side (the side opposite to the light incident surface, the second substrate 200 side) of the semiconductor layer 100S.
  • the transfer transistor TR has a transfer gate TG.
  • the transfer gate TG includes, for example, a horizontal portion TGB facing the front surface of the semiconductor layer 100S and a vertical portion TGA provided within the semiconductor layer 100S.
  • the vertical portion TGA extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGA contacts the horizontal portion TGB, and the other end is provided within the N-type semiconductor region 114.
  • the horizontal portion TGB of the transfer gate TG extends, for example, in the H direction from a position opposite the vertical portion TGA toward the center of the pixel sharing unit 539 ( Figure 7A). This allows the H direction position of the through electrode (through electrode TGV described below) that reaches the transfer gate TG to be closer to the H direction position of the through electrodes (through electrodes 120E and 121E described below) connected to the floating diffusion FD and the VSS contact region 118.
  • multiple pixel sharing units 539 provided on the first substrate 100 have the same configuration ( Figure 7A).
  • the semiconductor layer 100S is provided with a pixel separator 117 that separates the pixels 541A, 541B, 541C, and 541D from one another.
  • the pixel separator 117 is formed to extend in the normal direction of the semiconductor layer 100S (the direction perpendicular to the surface of the semiconductor layer 100S).
  • the pixel separator 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from one another, and has, for example, a lattice-like planar shape ( Figures 7A and 7B).
  • the pixel separator 117 for example, electrically and optically separates the pixels 541A, 541B, 541C, and 541D from one another.
  • the pixel separation section 117 includes, for example, a light-shielding film 117A and an insulating film 117B.
  • the light-shielding film 117A is made of, for example, tungsten (W).
  • the insulating film 117B is provided between the light-shielding film 117A and the P-well layer 115 or the N-type semiconductor region 114.
  • the insulating film 117B is made of, for example, silicon oxide (SiO).
  • the pixel separation section 117 has, for example, a full trench isolation (FTI) structure and penetrates the semiconductor layer 100S.
  • FTI full trench isolation
  • the pixel separation section 117 is not limited to an FTI structure that penetrates the semiconductor layer 100S.
  • it may have a deep trench isolation (DTI) structure that does not penetrate the semiconductor layer 100S.
  • the pixel separator 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial area of the semiconductor layer 100S.
  • the semiconductor layer 100S is provided with, for example, a first pinning region 113 and a second pinning region 116.
  • the first pinning region 113 is provided near the back surface of the semiconductor layer 100S and is disposed between the N-type semiconductor region 114 and the fixed charge film 112.
  • the second pinning region 116 is provided on the side of the pixel separation section 117, specifically, between the pixel separation section 117 and the P-well layer 115 or the N-type semiconductor region 114.
  • the first pinning region 113 and the second pinning region 116 are formed of, for example, a P-type semiconductor region.
  • a fixed charge film 112 having a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111.
  • a first pinning region 113 of the hole accumulation layer is formed at the interface on the light-receiving surface (back surface) side of the semiconductor layer 100S due to an electric field induced by the fixed charge film 112. This suppresses the generation of dark current due to the interface state on the light-receiving surface side of the semiconductor layer 100S.
  • the fixed charge film 112 is formed, for example, by an insulating film having a negative fixed charge. Examples of materials for this insulating film having a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.
  • a light-shielding film 117A is provided between the fixed charge film 112 and the insulating film 111.
  • This light-shielding film 117A may be provided continuous with the light-shielding film 117A constituting the pixel separation section 117.
  • the light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided, for example, at a position facing the pixel separation section 117 in the semiconductor layer 100S.
  • the insulating film 111 is provided so as to cover this light-shielding film 117A.
  • the insulating film 111 is made of, for example, silicon oxide.
  • the wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 has, from the semiconductor layer 100S side, an interlayer insulating film 119, pad portions 120, 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124, in this order.
  • the horizontal portion TGB of the transfer gate TG is provided, for example, in this wiring layer 100T.
  • the interlayer insulating film 119 is provided over the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S.
  • the interlayer insulating film 119 is made of, for example, a silicon oxide film. Note that the configuration of the wiring layer 100T is not limited to that described above, and may be any configuration having wiring and an insulating film.
  • Figure 7B shows the planar configuration shown in Figure 7A as well as the configuration of pad portions 120, 121.
  • Pad portions 120, 121 are provided in selective regions on interlayer insulating film 119.
  • Pad portion 120 is for connecting the floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) of pixels 541A, 541B, 541C, 541D to each other.
  • Pad portion 120 is disposed, for example, for each pixel sharing unit 539, in the center of pixel sharing unit 539 in planar view ( Figure 7B).
  • the pad section 120 is provided so as to straddle the pixel separation section 117, and is disposed so as to overlap at least a portion of each of the floating diffusions FD1, FD2, FD3, and FD4 (FIGS.
  • the pad section 120 is formed in a region that overlaps, in a direction perpendicular to the surface of the semiconductor layer 100S, with at least a portion of each of the multiple floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) that share the pixel circuit 210, and with at least a portion of the pixel separation section 117 formed between the multiple photodiodes PD (photodiodes PD1, PD2, PD3, and PD4) that share the pixel circuit 210.
  • the interlayer insulating film 119 is provided with connection vias 120C for electrically connecting the pad portion 120 to the floating diffusions FD1, FD2, FD3, and FD4.
  • connection vias 120C are provided in each of the pixels 541A, 541B, 541C, and 541D.
  • a part of the pad portion 120 is embedded in the connection vias 120C, thereby electrically connecting the pad portion 120 to the floating diffusions FD1, FD2, FD3, and FD4.
  • the pad portion 121 is for connecting the multiple VSS contact regions 118 to each other.
  • the VSS contact regions 118 provided in the pixels 541C and 541D of one pixel sharing unit 539 adjacent to each other in the V direction are electrically connected to the VSS contact regions 118 provided in the pixels 541A and 541B of the other pixel sharing unit 539 by the pad portion 121.
  • the pad portion 121 is provided, for example, so as to straddle the pixel separation portions 117, and is disposed so as to overlap at least a portion of each of the four VSS contact regions 118.
  • the pad portion 121 is formed in a region that overlaps at least a portion of each of the multiple VSS contact regions 118 and at least a portion of the pixel separation portions 117 formed between the multiple VSS contacts 118 in a direction perpendicular to the surface of the semiconductor layer 100S.
  • the interlayer insulating film 119 has a connection via 121C for electrically connecting the pad portion 121 and the VSS contact region 118.
  • the connection via 121C is provided in each of the pixels 541A, 541B, 541C, and 541D.
  • a part of the pad portion 121 is embedded in the connection via 121C, thereby electrically connecting the pad portion 121 and the VSS contact region 118.
  • the pad portions 120 and 121 of each of the multiple pixel sharing units 539 aligned in the V direction are arranged at approximately the same position in the H direction ( Figure 7B).
  • the pad section 120 By providing the pad section 120, it is possible to reduce the amount of wiring for connecting each floating diffusion FD to the pixel circuit 210 (e.g., the gate electrode of the amplifying transistor AMP) throughout the chip. Similarly, by providing the pad section 121, it is possible to reduce the amount of wiring for supplying potential to each VSS contact region 118 throughout the chip. This makes it possible to reduce the overall chip area, suppress electrical interference between wiring in miniaturized pixels, and/or reduce costs by reducing the number of components.
  • the pad portions 120, 121 can be provided at desired positions on the first substrate 100 and the second substrate 200. Specifically, the pad portions 120, 121 can be provided on either the wiring layer 100T or the insulating region 212 of the semiconductor layer 200S. When provided on the wiring layer 100T, the pad portions 120, 121 may be in direct contact with the semiconductor layer 100S. Specifically, the pad portions 120, 121 may be directly connected to at least a portion of each of the floating diffusion FD and/or the VSS contact region 118.
  • connection vias 120C, 121C may be provided from each of the floating diffusions FD and/or VSS contact regions 118 connected to the pad portions 120, 121, and the pad portions 120, 121 may be provided at desired positions in the insulating region 211-2 of the wiring layer 100T and the semiconductor layer 200S.
  • the wiring connected to the floating diffusion FD and/or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200S can be reduced.
  • the pixel transistor can be formed large, which contributes to improving image quality by reducing noise, etc.
  • the wiring connecting the first substrate 100 and the second substrate 200 can be significantly reduced.
  • pad section 120 to which multiple floating diffusions FD are connected and pad section 121 to which multiple VSS contacts 118 are connected are alternately arranged in a straight line in the V direction.
  • pad sections 120, 121 are formed in a position surrounded by multiple photodiodes PD, multiple transfer gates TG, and multiple floating diffusions FD. This allows elements other than the floating diffusions FD and VSS contact regions 118 to be freely arranged on the first substrate 100 on which multiple elements are formed, thereby improving the efficiency of the layout of the entire chip. Also, symmetry is ensured in the layout of the elements formed in each pixel sharing unit 539, and variation in the characteristics of each pixel 541 can be suppressed.
  • the pad sections 120, 121 are made of, for example, polysilicon (POLY SI), more specifically, doped polysilicon to which impurities have been added.
  • the pad sections 120, 121 are preferably made of a highly heat-resistant conductive material such as polysilicon, tungsten (W), titanium (TI) and titanium nitride (TIN).
  • W tungsten
  • TI titanium
  • TIN titanium nitride
  • the second manufacturing method it is also conceivable to form the pixel circuits 210 on the second substrate 200 and then bond this to the first substrate 100 (hereinafter referred to as the second manufacturing method).
  • electrodes for electrical connection are formed in advance on each of the surfaces of the first substrate 100 (surface of the wiring layer 100T) and the second substrate 200 (surface of the wiring layer 200T).
  • the electrodes for electrical connection formed on the surfaces of the first substrate 100 and the second substrate 200 come into contact with each other at the same time.
  • an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200.
  • the imaging device 1 by configuring the imaging device 1 using the second manufacturing method, it is possible to manufacture the imaging device using an appropriate process depending on the configuration of each of the first substrate 100 and the second substrate 200, for example, and it is possible to manufacture a high-quality, high-performance imaging device.
  • the first substrate 100 and the second substrate 200 when the first substrate 100 and the second substrate 200 are bonded together, an alignment error may occur due to the manufacturing device used for bonding.
  • the first substrate 100 and the second substrate 200 have a diameter of, for example, several tens of centimeters, and when the first substrate 100 and the second substrate 200 are bonded together, the substrates may expand and contract in microscopic regions of each of the first substrate 100 and the second substrate 200. This expansion and contraction of the substrates is caused by a slight difference in the timing at which the substrates come into contact with each other. Due to such expansion and contraction of the first substrate 100 and the second substrate 200, an error may occur in the position of the electrodes for electrical connection formed on the surface of the first substrate 100 and the surface of the second substrate 200, respectively.
  • the second manufacturing method it is preferable to take measures so that the electrodes of the first substrate 100 and the second substrate 200 contact each other even if such errors occur. Specifically, at least one, and preferably both, of the electrodes of the first substrate 100 and the second substrate 200 are made large in consideration of the above errors. Therefore, when the second manufacturing method is used, for example, the size (size in the substrate planar direction) of the electrode formed on the surface of the first substrate 100 or the second substrate 200 becomes larger than the size of the internal electrode extending in the thickness direction from the inside of the first substrate 100 or the second substrate 200 to the surface.
  • the pad parts 120, 121 from a heat-resistant conductive material, it becomes possible to use the first manufacturing method.
  • the first manufacturing method after forming the first substrate 100 including the photodiode PD and the transfer transistor TR, the first substrate 100 and the second substrate 200 (semiconductor layer 2000S) are bonded together. At this time, the second substrate 200 is in a state in which the patterns of the active elements and wiring layers constituting the pixel circuit 210 have not yet been formed.
  • the second substrate 200 Since the second substrate 200 is in a state before the patterns are formed, even if an error occurs in the bonding position when the first substrate 100 and the second substrate 200 are bonded together, this bonding error will not cause an error in the alignment between the pattern of the first substrate 100 and the pattern of the second substrate 200. This is because the pattern on the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded together.
  • an exposure device for pattern formation uses the pattern formed on the first substrate as a target for alignment when forming the pattern. For the above reasons, errors in the bonding position between the first substrate 100 and the second substrate 200 do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method. For the same reason, errors caused by the expansion and contraction of the substrates in the second manufacturing method do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method.
  • the through electrodes 120E, 121E and the through electrodes TGV are formed.
  • a pattern of the through electrodes is formed from above the second substrate 200 using reduced projection exposure with an exposure device. Because reduced exposure projection is used, even if an error occurs in the alignment between the second substrate 200 and the exposure device, the magnitude of the error in the second substrate 200 is only a fraction of the error in the second manufacturing method described above (the reciprocal of the reduced exposure projection magnification). Therefore, by constructing the imaging device 1 using the first manufacturing method, it becomes easier to align the elements formed on the first substrate 100 and the second substrate 200, making it possible to manufacture a high-quality, high-performance imaging device.
  • An imaging device 1 manufactured using such a first manufacturing method has different characteristics from an imaging device manufactured using the second manufacturing method.
  • the through electrodes 120E, 121E, and TGV have a substantially constant thickness (size in the substrate planar direction) from the second substrate 200 to the first substrate 100.
  • the through electrodes 120E, 121E, and TGV have a tapered shape, they have a tapered shape with a constant inclination.
  • An imaging device 1 having such through electrodes 120E, 121E, and TGVs makes it easier to miniaturize the pixels 541.
  • the active elements are formed on the second substrate 200 after bonding the first substrate 100 and the second substrate 200 (semiconductor layer 200S), so the first substrate 100 is also affected by the heat treatment required for forming the active elements.
  • a conductive material with high heat resistance for the pads 120, 121 provided on the first substrate 100 it is preferable to use a material with a higher melting point (i.e., higher heat resistance) for the pads 120, 121 than at least a part of the wiring material included in the wiring layer 200T of the second substrate 200.
  • a conductive material with high heat resistance such as doped polysilicon, tungsten, titanium, or titanium nitride is used for the pads 120, 121. This makes it possible to manufacture the imaging device 1 by using the first manufacturing method described above.
  • the passivation film 122 is provided over the entire surface of the semiconductor layer 100S so as to cover the pad portions 120, 121 (FIG. 6).
  • the passivation film 122 is made of, for example, a silicon nitride (SIN) film.
  • the interlayer insulating film 123 covers the pad portions 120, 121 with the passivation film 122 in between. This interlayer insulating film 123 is provided over the entire surface of the semiconductor layer 100S.
  • the interlayer insulating film 123 is made of, for example, a silicon oxide (SIO) film.
  • the bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. This bonding film 124 is provided over the entire main surface of the first substrate 100.
  • the bonding film 124 is made of, for example, a silicon nitride film.
  • the light receiving lens 401 faces the semiconductor layer 100S, for example, with the fixed charge film 112 and the insulating film 111 in between ( Figure 6).
  • the light receiving lens 401 is provided in a position facing the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D, for example.
  • the second substrate 200 has, from the first substrate 100 side, a semiconductor layer 200S and a wiring layer 200T, in this order.
  • the semiconductor layer 200S is composed of a silicon substrate.
  • a well region 211 is provided in the semiconductor layer 200S across its thickness.
  • the well region 211 is, for example, a P-type semiconductor region.
  • the second substrate 200 is provided with a pixel circuit 210 arranged for each pixel sharing unit 539. This pixel circuit 210 is provided, for example, on the front side (wiring layer 200T side) of the semiconductor layer 200S.
  • the second substrate 200 is bonded to the first substrate 100 with the back side (semiconductor layer 200S side) of the second substrate 200 facing the front side (wiring layer 100T side) of the first substrate 100.
  • the second substrate 200 is bonded to the first substrate 100 face-to-back.
  • Figures 8 to 12 show a schematic example of the planar configuration of the second substrate 200.
  • Figure 8 shows the configuration of the pixel circuit 210 provided near the surface of the semiconductor layer 200S.
  • Figure 9 shows a schematic example of the configuration of the wiring layer 200T (specifically, the first wiring layer W1 described below) and the semiconductor layer 200S and each part of the first substrate 100 connected to the wiring layer 200T.
  • Figures 10 to 12 show an example of the planar configuration of the wiring layer 200T.
  • the configuration of the second substrate 200 will be explained below using Figures 8 to 12 in addition to Figure 6.
  • the outer shape of the photodiode PD (the boundary between the pixel isolation section 117 and the photodiode PD) is shown by a dashed line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 214 in the portion overlapping the gate electrode of each transistor constituting the pixel circuit 210 is shown by a dotted line.
  • the boundary between the semiconductor layer 200S and the element isolation region 213, and the boundary between the element isolation region 213 and the insulating region 213 are provided on one side of the channel width direction.
  • the second substrate 200 is provided with an insulating region 212 that divides the semiconductor layer 200S, and an element isolation region 213 provided in a part of the thickness direction of the semiconductor layer 200S (Fig. 6).
  • the through electrodes 120E, 121E and through electrodes TGVs (through electrodes TGV1, TGV2, TGV3, TGV4) of two pixel sharing units 539 connected to two pixel circuits 210 adjacent to each other in the H direction are arranged in the insulating region 212 provided between the two pixel circuits 210 (Fig. 9).
  • the insulating region 212 has approximately the same thickness as the semiconductor layer 200S ( Figure 6).
  • the semiconductor layer 200S is divided by this insulating region 212.
  • the through electrodes 120E, 121E and the through electrode TGV are arranged in this insulating region 212.
  • the insulating region 212 is made of, for example, silicon oxide.
  • the through electrodes 120E, 121E are provided penetrating the insulating region 212 in the thickness direction.
  • the upper ends of the through electrodes 120E, 121E are connected to the wiring (first wiring W1, second wiring W2, third wiring W3, and fourth wiring W4 described below) of the wiring layer 200T.
  • the through electrodes 120E, 121E are provided penetrating the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and their lower ends are connected to the pad portions 120, 121 ( Figure 6).
  • the through electrodes 120E are intended to electrically connect the pad portion 120 to the pixel circuit 210.
  • the through electrode 120E electrically connects the floating diffusion FD of the first substrate 100 to the pixel circuit 210 of the second substrate 200.
  • the through electrode 121E is for electrically connecting the pad portion 121 to the reference potential line VSS of the wiring layer 200T. That is, the through electrode 121E electrically connects the VSS contact region 118 of the first substrate 100 to the reference potential line VSS of the second substrate 200.
  • the through electrode TGV is provided so as to penetrate the insulating region 212 in the thickness direction.
  • the upper end of the through electrode TGV is connected to the wiring of the wiring 200T.
  • This through electrode TGV is provided so as to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122 and the interlayer insulating film 119, and its lower end is connected to the transfer gate TG ( Figure 6).
  • Such through electrodes TGV are intended to electrically connect the transfer gates TG (transfer gates TG1, TG2, TG3, TG4) of the pixels 541A, 541B, 541C, 541D to the wiring of the wiring layer 200T (part of the row drive signal line 542, specifically, the wiring TRG1, TRG2, TRG3, TRG4 in Figure 11 described below).
  • the through electrodes TGV electrically connect the transfer gates TG of the first substrate 100 to the wiring TR of the second substrate 200, and send drive signals to each of the transfer transistors TR (transfer transistors TR1, TR2, TR3, TR4).
  • the insulating region 212 is a region for insulating the through electrodes 120E, 121E and through electrodes TGV from the semiconductor layer 200S, for electrically connecting the first substrate 100 and the second substrate 200.
  • the insulating region 212 provided between two pixel circuits 210 (shared units 539) adjacent to each other in the H direction has the through electrodes 120E, 121E and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) connected to the two pixel circuits 210 arranged therein.
  • the insulating region 212 is provided, for example, extending in the V direction ( Figures 8 and 9).
  • the horizontal part TGB of the transfer gate TG is arranged so that the position of the through electrode TGV in the H direction is closer to the position of the through electrodes 120E, 121E in the H direction than the position of the vertical part TGA ( Figures 7A and 9).
  • the through electrode TGV is arranged at approximately the same position as the through electrodes 120E, 121E in the H direction. This allows the through electrodes 120E, 121E and the through electrode TGV to be provided together in the insulating region 212 extending in the V direction.
  • the through electrode TGV is formed approximately directly above the vertical part TGA, and the through electrode TGV is arranged, for example, in approximately the center of each pixel 541 in the H direction and the V direction.
  • the position of the through electrode TGV in the H direction is significantly different from the positions of the through electrodes 120E, 121E in the H direction.
  • an insulating region 212 is provided around the through electrode TGV and the through electrodes 120E, 121E to electrically insulate them from the adjacent semiconductor layer 200S.
  • the position of the through electrode TGV in the H direction is significantly different from the positions of the through electrodes 120E, 121E in the H direction, it is necessary to provide an insulating region 212 independently around each of the through electrodes 120E, 121E, and TGV. This causes the semiconductor layer 200S to be divided into small pieces.
  • a layout in which the through electrodes 120E, 121E and the through electrodes TGV are arranged together in the insulating region 212 extending in the V direction can increase the size of the semiconductor layer 200S in the H direction. This allows a large area to be secured for the semiconductor element formation region in the semiconductor layer 200S. This makes it possible, for example, to increase the size of the amplifying transistor AMP and suppress noise.
  • the pixel sharing unit 539 electrically connects the floating diffusions FD provided in each of the multiple pixels 541, and has a structure in which the multiple pixels 541 share one pixel circuit 210.
  • the electrical connection between the floating diffusions FD is made by a pad portion 120 provided on the first substrate 100 (FIGS. 6 and 7B).
  • the electrical connection portion (pad portion 120) provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200 are electrically connected via one through electrode 120E.
  • the pixel sharing unit 539 is provided with four through electrodes connected to the floating diffusions FD1, FD2, FD3, and FD4, respectively. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the insulating region 212 that insulates the periphery of these through electrodes becomes larger.
  • the structure in which the pad portion 120 is provided on the first substrate 100 ( Figures 6 and 7B) can reduce the number of through electrodes and make the insulating region 212 smaller. This makes it possible to secure a large area for the semiconductor element formation region in the semiconductor layer 200S. This makes it possible, for example, to increase the size of the amplifying transistor AMP and suppress noise.
  • the element isolation region 213 is provided on the surface side of the semiconductor layer 200S.
  • the element isolation region 213 has an STI (Shallow Trench Isolation) structure.
  • the semiconductor layer 200S is dug in the thickness direction (perpendicular to the main surface of the second substrate 200), and an insulating film is embedded in this dug portion.
  • This insulating film is made of, for example, silicon oxide.
  • the element isolation region 213 provides element isolation between the multiple transistors that make up the pixel circuit 210 in accordance with the layout of the pixel circuit 210. Below the element isolation region 213 (deep in the semiconductor layer 200S), the semiconductor layer 200S (specifically, the well region 211) extends.
  • pixel-sharing units 539 are provided across both the first substrate 100 and the second substrate 200.
  • the outer shape of the pixel-sharing unit 539 provided on the first substrate 100 and the outer shape of the pixel-sharing unit 539 provided on the second substrate 200 are different from each other.
  • pixel-sharing unit 539 of first substrate 100 is composed of two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction, and two pixels 541 (pixels 541C and 541D) arranged adjacent to these in the V direction.
  • pixel-sharing unit 539 of first substrate 100 is composed of four adjacent pixels 541 in two rows and two columns, and pixel-sharing unit 539 of first substrate 100 has a substantially square outline shape.
  • such pixel sharing units 539 are arranged adjacent to each other at a pitch of two pixels in the H direction (a pitch equivalent to two pixels 541) and at a pitch of two pixels in the V direction (a pitch equivalent to two pixels 541).
  • the outlines of pixels 541A, 541B, 541C, and 541D are indicated by dashed dotted lines, and the outline shape of pixel-sharing unit 539 is indicated by a thick line.
  • the outline shape of pixel-sharing unit 539 of second substrate 200 is smaller in the H direction than pixel-sharing unit 539 of first substrate 100, and larger in the V direction than pixel-sharing unit 539 of first substrate 100.
  • pixel-sharing unit 539 of second substrate 200 is formed to have a size (area) equivalent to one pixel in the H direction, and a size equivalent to four pixels in the V direction. That is, the pixel sharing unit 539 of the second substrate 200 is formed to a size equivalent to adjacent pixels arranged in one row and four columns, and the pixel sharing unit 539 of the second substrate 200 has an approximately rectangular outer shape.
  • each pixel circuit 210 the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged in this order in the V direction ( Figure 8).
  • the outer shape of each pixel circuit 210 it is possible to arrange four transistors (selection transistor SEL, amplification transistor AMP, reset transistor RST, and FD conversion gain switching transistor FDG) in one direction (V direction in Figure 8). This allows the drain of the amplification transistor AMP and the drain of the reset transistor RST to share a single diffusion region (diffusion region connected to the power supply line VDD).
  • each pixel circuit 210 it is also possible to arrange the formation region of each pixel circuit 210 in an approximately square shape (see Figure 21 described later). In this case, two transistors are arranged along one direction, making it difficult to share a single diffusion region for the drain of the amplification transistor AMP and the drain of the reset transistor RST. Therefore, by providing the formation area of the pixel circuit 210 in a substantially rectangular shape, it becomes easier to arrange the four transistors in close proximity, and the formation area of the pixel circuit 210 can be made smaller. In other words, the pixels can be miniaturized. Furthermore, when it is not necessary to reduce the formation area of the pixel circuit 210, it is possible to increase the formation area of the amplifying transistor AMP and suppress noise.
  • a VSS contact region 218 connected to the reference potential line VSS is provided near the surface of the semiconductor layer 200S.
  • the VSS contact region 218 is, for example, composed of a P-type semiconductor region.
  • the VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring of the wiring layer 200T and the through electrode 121E.
  • This VSS contact region 218 is provided, for example, at a position adjacent to the source of the FD conversion gain switching transistor FDG with the element isolation region 213 in between (FIG. 8).
  • one pixel sharing unit 539 (e.g., the upper side of the paper in FIG. 7B) is connected to one pixel sharing unit 539 of the two pixel sharing units 539 aligned in the H direction on the second substrate 200 (e.g., the left side of the paper in FIG. 8).
  • the other pixel sharing unit 539 e.g., the lower side of the paper in Figure 7B
  • the other pixel sharing unit 539 aligned in the H direction on the second substrate 200 e.g., the right side of the paper in Figure 8.
  • the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is substantially equal to the internal layout of the other pixel sharing unit 539 that is inverted in the V and H directions. The effects obtained by this layout are explained below.
  • each pad portion 120 is disposed in the center of the external shape of the pixel-sharing unit 539, i.e., in the center of the pixel-sharing unit 539 in the V direction and the H direction (FIG. 7B).
  • the pixel-sharing unit 539 of the second substrate 200 has an external shape that is approximately rectangular and long in the V direction as described above, so that, for example, the amplification transistor AMP connected to the pad portion 120 is disposed in a position shifted upward from the center of the pixel-sharing unit 539 in the V direction on the paper.
  • the distance between the amplification transistor AMP of one pixel-sharing unit 539 and the pad portion 120 is relatively short.
  • the distance between the amplifying transistor AMP of the other pixel-sharing unit 539 and the pad section 120 becomes longer. This increases the area of the wiring required to connect this amplifying transistor AMP and the pad section 120, which may complicate the wiring layout of the pixel-sharing unit 539. This may have an impact on the miniaturization of the imaging device 1.
  • the distance between the amplifier transistors AMP and the pad section 120 of both of these two pixel-sharing units 539 can be shortened. This makes it easier to miniaturize the imaging device 1 compared to a configuration in which the internal layouts of the two pixel-sharing units 539 arranged in the H direction of the second substrate 200 are the same. Note that the planar layout of each of the multiple pixel-sharing units 539 on the second substrate 200 is symmetrical within the range shown in FIG. 8, but becomes asymmetrical when the layout of the first wiring layer W1 shown in FIG. 9 described later is included.
  • the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are also inverted relative to each other in the H direction.
  • the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are each connected to the pad portions 120, 121 of the first substrate 100.
  • the pad portions 120, 121 are disposed in the center portions in the H direction of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (between the two pixel sharing units 539 arranged in the H direction).
  • the position of the outline of the pixel sharing unit 539 on the second substrate 200 does not have to be aligned with the position of any of the outlines of the pixel sharing units 539 on the first substrate 100.
  • one pixel sharing unit 539 e.g., the left side of the paper in Figure 9
  • has an outline on one side in the V direction e.g., the upper side of the paper in Figure 9
  • positioned outside one outline in the V direction of the corresponding pixel sharing unit 539 on the first substrate 100 e.g., the upper side of the paper in Figure 7B.
  • the other pixel-sharing unit 539 (e.g., the right side of the paper in FIG. 9) has its outer edge in the V direction (e.g., the bottom side of the paper in FIG. 9) positioned outside the outer edge in the V direction of the corresponding pixel-sharing unit 539 on the first substrate 100 (e.g., the bottom side of the paper in FIG. 7B).
  • the positions of the outer contours of the multiple pixel sharing units 539 on the second substrate 200 do not have to be aligned with each other.
  • two pixel sharing units 539 aligned in the H direction on the second substrate 200 are arranged with their outer contours in the V direction offset from each other. This makes it possible to shorten the distance between the amplifying transistor AMP and the pad section 120. This makes it easier to miniaturize the imaging device 1.
  • the pixel sharing unit 539 of the first substrate 100 has a size equivalent to two pixels 541 in the H direction and a size equivalent to two pixels 541 in the V direction (FIG. 7B).
  • pixel sharing units 539 having a size equivalent to four pixels 541 are repeatedly arranged adjacent to each other at a two pixel pitch (a pitch equivalent to two pixels 541) in the H direction and at a two pixel pitch (a pitch equivalent to two pixels 541) in the V direction.
  • the pixel array section 540 of the first substrate 100 may be provided with a pair of pixel sharing units 539, in which two pixel sharing units 539 are arranged adjacent to each other in the V direction.
  • a pair of pixel sharing units 539 are repeatedly arranged adjacent to each other at a pitch of two pixels in the H direction (a pitch equivalent to two pixels 541) and a pitch of four pixels in the V direction (a pitch equivalent to four pixels 541).
  • the pixel sharing unit 539 of the second substrate 200 has a size of one pixel 541 in the H direction and a size of four pixels 541 in the V direction ( Figure 9).
  • the pixel array section 540 of the second substrate 200 is provided with a pair of pixel sharing units 539, each including two pixel sharing units 539 each having a size equivalent to four pixels 541.
  • the pixel sharing units 539 are arranged adjacent to each other in the H direction and offset in the V direction.
  • a pair of pixel-sharing units 539 are repeatedly arranged adjacent to each other with no gaps at a pitch of two pixels in the H direction (a pitch equivalent to two pixels 541) and at a pitch of four pixels in the V direction (a pitch equivalent to four pixels 541).
  • the amplifying transistor AMP has a three-dimensional structure, for example, a FIN type ( Figure 6). This increases the effective gate width, making it possible to suppress noise.
  • the selection transistor SEL, reset transistor RST and FD conversion gain switching transistor FDG have, for example, a planar structure.
  • the amplifying transistor AMP may have a planar structure.
  • the selection transistor SEL, reset transistor RST or FD conversion gain switching transistor FDG may have a three-dimensional structure.
  • the wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (first wiring layer W1, second wiring layer W2, third wiring layer W3, and fourth wiring layer W4).
  • the passivation film 221 is in contact with, for example, the surface of the semiconductor layer 200S, and covers the entire surface of the semiconductor layer 200S. This passivation film 221 covers the gate electrodes of the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG.
  • the interlayer insulating film 222 is provided between the passivation film 221 and the third substrate 300. This interlayer insulating film 222 separates multiple wirings (first wiring layer W1, second wiring layer W2, third wiring layer W3, and fourth wiring layer W4).
  • the interlayer insulating film 222 is made of, for example, silicon oxide.
  • a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact parts 201, 202 are provided in this order, and these are insulated from each other by an interlayer insulating film 222.
  • an interlayer insulating film 222 a plurality of connection parts are provided to connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to the layers below them.
  • the connection parts are connection holes provided in the interlayer insulating film 222, and a conductive material is filled in the connection holes.
  • connection part 218V is provided to connect the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S.
  • the hole diameter of the connection portion connecting the elements of the second substrate 200 is different from the hole diameter of the through electrodes 120E, 121E and the through electrode TGV.
  • the hole diameter of the connection hole connecting the elements of the second substrate 200 is smaller than the hole diameter of the through electrodes 120E, 121E and the through electrode TGV. The reason for this will be explained below.
  • the depth of the connection portion (connection portion 218V, etc.) provided in the wiring layer 200T is smaller than the depth of the through electrodes 120E, 121E and the through electrode TGV.
  • connection hole it is easier to fill the connection hole with a conductive material in the connection portion than in the through electrodes 120E, 121E and the through electrode TGV.
  • hole diameter of this connection By making the hole diameter of this connection smaller than the hole diameters of the through electrodes 120E, 121E and the through electrode TGV, it becomes easier to miniaturize the imaging device 1.
  • the first wiring layer W1 connects the through electrode 120E to the gate of the amplifying transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, a connection hole reaching the source of the FD conversion gain switching transistor FDG).
  • the first wiring layer W1 connects, for example, the through electrode 121E to the connection part 218V, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S to the VSS contact region 118 of the semiconductor layer 100S.
  • Figure 10 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2.
  • Figure 11 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3.
  • Figure 12 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4.
  • the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending in the H direction (row direction) ( Figure 11). These wirings correspond to the row drive signal lines 542 described with reference to Figure 4.
  • the wirings TRG1, TRG2, TRG3, and TRG4 are for sending drive signals to the transfer gates TG1, TG2, TG3, and TG4, respectively.
  • the wirings TRG1, TRG2, TRG3, and TRG4 are connected to the transfer gates TG1, TG2, TG3, and TG4, respectively, via the second wiring layer W2, the first wiring layer W1, and the through electrodes 120E.
  • the wiring SELL is for sending drive signals to the gate of the selection transistor SEL
  • the wiring RSTL is for sending drive signals to the gate of the reset transistor RST
  • the wiring FDGL is for sending drive signals to the gate of the FD conversion gain switching transistor FDG.
  • the wiring SELL, RSTL, and FDGL are each connected to the gates of the selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG via the second wiring layer W2, first wiring layer W1, and connection parts.
  • the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 extending in the V direction (column direction) ( Figure 12).
  • the power supply line VDD is connected to the drain of the amplifier transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part.
  • the reference potential line VSS is connected to the VSS contact area 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part 218V.
  • the reference potential line VSS is also connected to the VSS contact area 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad part 121.
  • the vertical signal line 543 is connected to the source (VOUT) of the select transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1 and a connection part.
  • the contact portions 201 and 202 may be provided at a position overlapping the pixel array portion 540 in a planar view (e.g., FIG. 3), or may be provided at the outer peripheral portion 540B of the pixel array portion 540 (e.g., FIG. 6).
  • the contact portions 201 and 202 are provided on the surface of the second substrate 200 (the surface facing the wiring layer 200T).
  • the contact portions 201 and 202 are made of a metal such as CU (copper) and AL (aluminum).
  • the contact portions 201 and 202 are exposed on the surface of the wiring layer 200T (the surface facing the third substrate 300).
  • the contact portions 201 and 202 are used to electrically connect the second substrate 200 and the third substrate 300 and to bond the second substrate 200 and the third substrate 300 together.
  • FIG. 6 illustrates an example in which a peripheral circuit is provided in the peripheral portion 540B of the second substrate 200.
  • This peripheral circuit may include a part of the row driver 520 or a part of the column signal processor 550. As shown in FIG. 3, the peripheral circuit may not be provided in the peripheral portion 540B of the second substrate 200, and the connection holes H1 and H2 may be located near the pixel array portion 540.
  • the third substrate 300 has, for example, a wiring layer 300T and a semiconductor layer 300S in this order from the second substrate 200 side.
  • the surface of the semiconductor layer 300S is provided on the second substrate 200 side.
  • the semiconductor layer 300S is made of a silicon substrate.
  • a circuit is provided on the surface side of the semiconductor layer 300S. Specifically, for example, at least some of the input section 510A, row driver section 520, timing control section 530, column signal processing section 550, image signal processing section 560, and output section 510B are provided on the surface side of the semiconductor layer 300S.
  • the wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact portions 301 and 302.
  • the contact portions 301 and 302 are exposed on the surface (the surface facing the second substrate 200) of the wiring layer 300T, with the contact portion 301 being in contact with the contact portion 201 of the second substrate 200 and the contact portion 302 being in contact with the contact portion 202 of the second substrate 200, respectively.
  • the contact parts 301 and 302 are electrically connected to circuits (e.g., at least one of the input part 510A, row driver part 520, timing control part 530, column signal processing part 550, image signal processing part 560, and output part 510B) formed in the semiconductor layer 300S.
  • the contact parts 301 and 302 are made of metals such as CU (copper) and aluminum (AL).
  • CU copper
  • AL aluminum
  • an external terminal TA is connected to the input part 510A via a connection hole part H1
  • an external terminal TB is connected to the output part 510B via a connection hole part H2.
  • the main components of an image capture device are a photodiode and a pixel circuit.
  • Increasing the area of the photodiode increases the charge generated as a result of photoelectric conversion, thereby improving the signal-to-noise ratio (S/N ratio) of the pixel signal and allowing the image capture device to output better image data (image information).
  • increasing the size of the transistors (especially the size of the amplifying transistor) included in the pixel circuit reduces the noise generated in the pixel circuit, thereby improving the S/N ratio of the image signal and allowing the image capture device to output better image data (image information).
  • the size of the transistor in the pixel circuit may become smaller. Also, if the size of the transistor in the pixel circuit is increased, the area of the photodiode may become smaller.
  • the imaging device 1 of this embodiment employs a structure in which multiple pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged to be superimposed on the photodiode PD.
  • This makes it possible to maximize the area of the photodiode PD within the limited area of the semiconductor substrate, and to maximize the size of the transistor provided in the pixel circuit 210. This improves the S/N ratio of the pixel signal, enabling the imaging device 1 to output better image data (image information).
  • multiple wirings extend from the floating diffusion FD of each of the multiple pixels 541 to one pixel circuit 210.
  • a connection wiring can be formed that interconnects these multiple extending wirings and combines them into one.
  • a connection wiring can be formed that interconnects the multiple extending wirings and combines them into one.
  • connection wiring that interconnects the multiple wirings extending from the floating diffusion FD of each of the multiple pixels 541 is formed on the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable that the area for forming the transistors included in the pixel circuit 210 will be reduced.
  • connection wiring that interconnects the multiple wirings extending from the VSS contact region 118 of each of the multiple pixels 541 and combines them into one is formed on the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable that the area for forming the transistors included in the pixel circuit 210 will be reduced.
  • the imaging device 1 of this embodiment can have a structure in which a plurality of pixels 541 share a single pixel circuit 210, and the shared pixel circuit 210 is arranged superimposed on a photodiode PD, and the first substrate 100 can be provided with connection wiring that interconnects and combines the floating diffusions FD of the plurality of pixels 541, and connection wiring that interconnects and combines the VSS contact regions 118 of each of the plurality of pixels 541.
  • the first substrate 100 and the second substrate 200 can be manufactured using an appropriate process according to the configuration of each substrate, for example, and a high-quality, high-performance imaging device can be manufactured.
  • the connection wiring for the first substrate 100 and the second substrate 200 can be formed by a simple process.
  • electrodes for connecting to the floating diffusions FD and electrodes for connecting to the VSS contact regions 118 are provided on the surfaces of the first substrate 100 and the second substrate 200, which are the bonding interface between the first substrate 100 and the second substrate 200, respectively. Furthermore, it is preferable to make the electrodes formed on the surfaces of the two substrates large so that the electrodes will contact each other even if misalignment occurs between the electrodes on the surfaces of the first substrate 100 and the second substrate 200 when they are bonded together. In this case, it may be difficult to arrange the electrodes within the limited area of each pixel in the imaging device 1.
  • the imaging device 1 of this embodiment can use the first manufacturing method described above as a manufacturing method in which multiple pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged superimposed on the photodiode PD. This makes it easier to align the elements formed on the first substrate 100 and the second substrate 200, making it possible to manufacture an imaging device with high quality and high performance. Furthermore, it is possible to have a unique structure that is generated by using this manufacturing method.
  • the structure has the semiconductor layer 100S and wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and wiring layer 200T of the second substrate 200 stacked in this order, in other words, the structure has the first substrate 100 and the second substrate 200 stacked face-to-back, and also has through electrodes 120E, 121E that extend from the surface side of the semiconductor layer 200S of the second substrate 200, through the semiconductor layer 200S and the wiring layer 100T of the first substrate 100, and reach the surface of the semiconductor layer 100S of the first substrate 100.
  • connection wiring that interconnects and combines the floating diffusions FD of the plurality of pixels 541 into one
  • connection wiring that interconnects and combines the VSS contact regions 118 of the plurality of pixels 541 into one
  • the imaging device 1 of this embodiment to use a conductive material with high heat resistance for the connection wiring that interconnects and combines the floating diffusions FD of the pixels 541 into one, and for the connection wiring that interconnects and combines the VSS contact regions 118 of the pixels 541 into one.
  • the conductive material with high heat resistance can be a material with a higher melting point than at least a portion of the wiring material included in the wiring layer 200T of the second substrate 200.
  • the imaging device 1 of this embodiment has: (1) a structure in which the first substrate 100 and the second substrate 200 are stacked face-to-back (specifically, a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked in this order); (2) a structure in which through-electrodes 120E, 121E are provided from the front side of the semiconductor layer 200S of the second substrate 200, penetrating the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 to the front side of the semiconductor layer 100S of the first substrate 100; and (3) a structure in which floating electrodes 120E, 121E are provided in each of the multiple pixels 541.
  • connection wiring that interconnects and combines the floating diffusions FD of each of the multiple pixels 541 into one and the connection wiring that interconnects and combines the VSS contact regions 118 of each of the multiple pixels 541 into one is formed from a highly heat-resistant conductive material, it is possible to provide the first substrate 100 with the connection wiring that interconnects and combines the floating diffusions FD of each of the multiple pixels 541 into one and the connection wiring that interconnects and combines the VSS contact regions 118 of each of the multiple pixels 541 into one, without providing a large electrode at the interface between the first substrate 100 and the second substrate 200.
  • FIGs. 13 and 14 are diagrams in which arrows representing the paths of each signal have been added to Fig. 3.
  • Fig. 13 shows with arrows the paths of the input signal input from the outside to the imaging device 1, the power supply potential, and the reference potential.
  • Fig. 14 shows with arrows the signal paths of the pixel signals output from the imaging device 1 to the outside.
  • an input signal e.g., a pixel clock and a synchronization signal
  • a row drive signal is generated in the row driver 520.
  • This row drive signal is sent to the second substrate 200 via the contact sections 301, 201. Furthermore, this row drive signal reaches each pixel sharing unit 539 of the pixel array section 540 via a row drive signal line 542 in the wiring layer 200T.
  • the drive signals other than the transfer gate TG are input to the pixel circuit 210 to drive each transistor included in the pixel circuit 210.
  • the drive signal of the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV, and the pixels 541A, 541B, 541C, and 541D are driven (FIG. 13).
  • the power supply potential and the reference potential supplied from the outside of the imaging device 1 to the input section 510A (input terminal 511) of the third substrate 300 are sent to the second substrate 200 via the contact sections 301 and 201, and are supplied to the pixel circuits 210 of the pixel sharing units 539 via wiring in the wiring layer 200T.
  • the reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E.
  • the pixel signals photoelectrically converted in the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are sent to the pixel circuits 210 of the second substrate 200 for each pixel sharing unit 539 via the through electrode 120E.
  • a pixel signal based on this pixel signal is sent from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact units 202, 302.
  • This pixel signal is processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, and then output to the outside via the output unit 510B.
  • the pixels 541A, 541B, 541C, and 541D are provided on different substrates (the first substrate 100 and the second substrate 200).
  • the first substrate 100 and the second substrate 200 are electrically connected to each other by through electrodes 120E, 121E provided in the insulating region 212.
  • the first substrate 100 and the second substrate 200 are electrically connected to each other by through electrodes 120E, 121E provided in the insulating region 212.
  • TSV Thirough Si Via
  • the formation area of the pixels 541A, 541B, 541C, 541D and the pixel circuit 210 can be expanded. As a result, it is possible to increase the amount of pixel signal obtained by photoelectric conversion and reduce noise of the transistors provided in the pixel circuit 210. This improves the signal-to-noise ratio of the pixel signal, enabling the imaging device 1 to output better pixel data (image information).
  • the pixel circuit 210, the column signal processing section 550, and the image signal processing section 560 are provided on different substrates (the second substrate 200 and the third substrate 300). This makes it possible to increase the area of the pixel circuit 210 and the areas of the column signal processing section 550 and the image signal processing section 560 compared to a case in which the pixel circuit 210, the column signal processing section 550, and the image signal processing section 560 are formed on the same substrate. This makes it possible to reduce noise generated in the column signal processing section 550 and to install a more advanced image processing circuit in the image signal processing section 560. This improves the signal-to-noise ratio of the pixel signal, and enables the imaging device 1 to output better pixel data (image information).
  • the pixel array section 540 is provided on the first substrate 100 and the second substrate 200, and the column signal processing section 550 and the image signal processing section 560 are provided on the third substrate 300.
  • the contact sections 201, 202, 301, 302 that connect the second substrate 200 and the third substrate 300 are formed above the pixel array section 540. This allows the contact sections 201, 202, 301, 302 to be freely laid out without being interfered with by the various wirings provided in the pixel array. This allows the contact sections 201, 202, 301, 302 to be used for electrical connection between the second substrate 200 and the third substrate 300.
  • the column signal processing portion 550 and the image signal processing portion 560 have greater freedom in layout. This makes it possible to reduce noise generated in the column signal processing portion 550 and to install a more advanced image processing circuit in the image signal processing portion 560. Therefore, the signal-to-noise ratio of the pixel signals is improved, and the imaging device 1 can output better pixel data (image information).
  • the pixel separator 117 penetrates the semiconductor layer 100S. This makes it possible to suppress color mixing between pixels 541A, 541B, 541C, and 541D even if the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) becomes closer due to miniaturization of the area per pixel. This improves the signal-to-noise ratio of the pixel signal, enabling the imaging device 1 to output better pixel data (image information).
  • a pixel circuit 210 is provided for each pixel sharing unit 539.
  • the amplification transistor AMP it is possible to suppress noise. This improves the signal-to-noise ratio of the pixel signal, enabling the imaging device 1 to output better pixel data (image information).
  • a pad section 120 that electrically connects the floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) of four pixels (pixels 541A, 541B, 541C, 541D) is provided on the first substrate 100.
  • This makes it possible to reduce the insulating region 212 and ensure a sufficient size for the formation region (semiconductor layer 200S) of the transistors that constitute the pixel circuit 210.
  • Modification 1> 15 to 19 show a modified example of the planar configuration of the imaging device 1 according to the above embodiment.
  • FIG. 15 shows a schematic planar configuration of the semiconductor layer 200S of the second substrate 200 near the surface, and corresponds to FIG. 8 described in the above embodiment.
  • FIG. 16 shows a schematic configuration of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and each part of the first substrate 100, and corresponds to FIG. 9 described in the above embodiment.
  • FIG. 17 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, and corresponds to FIG. 10 described in the above embodiment.
  • FIG. 18 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, and corresponds to FIG. 11 described in the above embodiment.
  • FIG. 19 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to FIG. 12 described in the above embodiment.
  • the internal layout of one pixel sharing unit 539 (e.g., the right side of the paper) is configured to be inverted in the H direction only from the internal layout of the other pixel sharing unit 539 (e.g., the left side of the paper).
  • the deviation in the V direction between the outline of one pixel sharing unit 539 and the outline of the other pixel sharing unit 539 is larger than the deviation described in the above embodiment (FIG. 9).
  • the first variant of the imaging device 1 shown in Figures 15 to 19 can make the area of the two pixel sharing units 539 arranged in the H direction the same as that of the pixel sharing unit 539 of the second substrate 200 described in the above embodiment without inverting the planar layout of each of them in the V direction.
  • the planar layout of the pixel sharing units 539 of the first substrate 100 is the same as the planar layout ( Figures 7A and 7B) described in the above embodiment. Therefore, the imaging device 1 of this variant can obtain the same effect as the imaging device 1 described in the above embodiment.
  • the arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangement described in the above embodiment and this variant.
  • Modification 2> 20 to 25 show a modified example of the planar configuration of the imaging device 1 according to the above embodiment.
  • FIG. 20 shows a schematic planar configuration of the first substrate 100, and corresponds to FIG. 7A described in the above embodiment.
  • FIG. 21 shows a schematic planar configuration of the semiconductor layer 200S of the second substrate 200 near the surface, and corresponds to FIG. 8 described in the above embodiment.
  • FIG. 22 shows a schematic configuration of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and each part of the first substrate 100, and corresponds to FIG. 9 described in the above embodiment.
  • FIG. 23 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, and corresponds to FIG. 10 described in the above embodiment.
  • FIG. 20 shows a schematic planar configuration of the first substrate 100, and corresponds to FIG. 7A described in the above embodiment.
  • FIG. 21 shows a schematic planar configuration of the semiconductor layer 200S of the second substrate 200 near the surface, and corresponds
  • FIG. 24 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, and corresponds to FIG. 11 described in the above embodiment.
  • FIG. 25 shows an example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to FIG. 12 described in the above embodiment.
  • each pixel circuit 210 has a substantially square planar shape (see FIG. 21, etc.).
  • the planar configuration of the imaging device 1 in this modified example differs from the planar configuration of the imaging device 1 described in the above embodiment.
  • the pixel sharing unit 539 of the first substrate 100 is formed across a pixel area of 2 rows x 2 columns, as described in the above embodiment, and has a roughly square planar shape (Figure 20).
  • the horizontal portions TGB of the transfer gates TG1, TG3 of pixels 541A and 541C in one pixel column extend from the position where they overlap the vertical portion TGA in a direction toward the center of the pixel sharing unit 539 in the H direction (more specifically, in the direction toward the outer edges of pixels 541A and 541C and in the direction toward the center of the pixel sharing unit 539), and the horizontal portions TGB of the transfer gates TG2, TG4 of pixels 541B and 541D in the other pixel column extend from the position where they overlap the vertical portion TGA in a direction toward the outside of the pixel sharing unit 539 in the H direction (more specifically, in the direction toward the outer edges of pixels 541B and 541D and in the direction toward the outside of the pixel sharing unit 5
  • the pad portion 120 connected to the floating diffusion FD is provided in the center of the pixel sharing unit 539 (the center of the pixel sharing unit 539 in the H and V directions), and the pad portion 121 connected to the VSS contact region 118 is provided at the end of the pixel sharing unit 539 at least in the H direction (in the H and V directions in Figure 20).
  • the horizontal portions TGB of the transfer gates TG1, TG2, TG3, and TG4 are also possible to provide the horizontal portions TGB of the transfer gates TG1, TG2, TG3, and TG4 only in the areas facing the vertical portions TGA.
  • the semiconductor layer 200S is likely to be divided into small portions, as described in the above embodiment. This makes it difficult to form large transistors in the pixel circuit 210.
  • the horizontal portions TGB of the transfer gates TG1, TG2, TG3, and TG4 are extended in the H direction from the position where they overlap the vertical portions TGA, as in the above modified example, it is possible to increase the width of the semiconductor layer 200S, as described in the above embodiment.
  • the H-direction positions of the through electrodes TGV1 and TGV3 connected to the transfer gates TG1 and TG3 can be arranged close to the H-direction position of the through electrode 120E, and the H-direction positions of the through electrodes TGV2 and TGV4 connected to the transfer gates TG2 and TG4 can be arranged close to the H-direction position of the through electrode 121E (FIG. 22).
  • the pixel sharing unit 539 of the second substrate 200 has, for example, approximately the same size in the H direction and V direction as the pixel sharing unit 539 of the first substrate 100, and is provided, for example, over an area corresponding to a pixel area of approximately 2 rows and 2 columns.
  • a selection transistor SEL and an amplification transistor AMP are arranged side by side in the V direction in one semiconductor layer 200S extending in the V direction
  • an FD conversion gain switching transistor FDG and a reset transistor RST are arranged side by side in the V direction in one semiconductor layer 200S extending in the V direction.
  • the semiconductor layer 200S in which the selection transistor SEL and the amplification transistor AMP are provided and the semiconductor layer 200S in which the FD conversion gain switching transistor FDG and the reset transistor RST are provided are arranged side by side in the H direction via an insulating region 212.
  • This insulating region 212 extends in the V direction ( Figure 21).
  • the external shape of the pixel sharing unit 539 of the second substrate 200 will be described with reference to Figs. 21 and 22.
  • the pixel sharing unit 539 of the first substrate 100 shown in Fig. 20 is connected to the amplification transistor AMP and selection transistor SEL provided on one side of the H direction of the pad section 120 (the left side of the paper in Fig. 22), and the FD conversion gain switching transistor FDG and reset transistor RST provided on the other side of the H direction of the pad section 120 (the right side of the paper in Fig. 22).
  • the external shape of the shared unit 541 of the second substrate 200 which includes the amplification transistor AMP, selection transistor SEL, FD conversion gain switching transistor FDG, and reset transistor RST, is determined by the following four outer edges.
  • the first outer edge is the outer edge of one end in the V direction (the upper end in the paper of FIG. 22) of the semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP. This first outer edge is provided between the amplification transistor AMP included in the pixel sharing unit 539 and the selection transistor SEL included in the pixel sharing unit 539 adjacent to one side in the V direction (the upper end in FIG. 22) of this pixel sharing unit 539. More specifically, the first outer edge is provided in the center in the V direction of the element isolation region 213 between the amplification transistor AMP and the selection transistor SEL.
  • the second outer edge is the outer edge of the other end in the V direction (the lower end in FIG.
  • the second outer edge is provided between the selection transistor SEL included in the pixel sharing unit 539 and the amplification transistor AMP included in the pixel sharing unit 539 adjacent to the other side of the pixel sharing unit 539 in the V direction (the lower side of the paper in FIG. 22). More specifically, the second outer edge is provided in the center in the V direction of the element isolation region 213 between the selection transistor SEL and the amplification transistor AMP.
  • the third outer edge is the outer edge of the other end in the V direction (the lower end in the paper in FIG. 22) of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG.
  • the third outer edge is provided between the FD conversion gain switching transistor FDG included in the pixel sharing unit 539 and the reset transistor RST included in the pixel sharing unit 539 adjacent to the other side in the V direction of the pixel sharing unit 539 (the lower side of the paper in FIG. 22). More specifically, the third outer edge is provided at the center in the V direction of the element isolation region 213 between the FD conversion gain switching transistor FDG and the reset transistor RST.
  • the fourth outer edge is the outer edge of one end in the V direction (the end on the upper side of the paper in FIG. 22) of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG.
  • This fourth outer edge is provided between the reset transistor RST included in the pixel sharing unit 539 and the FD conversion gain switching transistor FDG (not shown) included in the pixel sharing unit 539 adjacent to one side in the V direction of the pixel sharing unit 539 (the upper side of the paper in FIG. 22). More specifically, the fourth outer edge is provided at the center in the V direction of the element isolation region 213 (not shown) between the reset transistor RST and the FD conversion gain switching transistor FDG.
  • the third and fourth outer edges are arranged to be shifted to one side in the V direction with respect to the first and second outer edges (in other words, offset to one side in the V direction).
  • the VSS contact region 218 is provided between the semiconductor layer 200S including the selection transistor SEL and the amplifying transistor AMP and the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG.
  • multiple pixel circuits 210 have the same arrangement.
  • An imaging device 1 having such a second substrate 200 can also achieve the same effects as those described in the above embodiment.
  • the arrangement of the pixel sharing units 539 on the second substrate 200 is not limited to the arrangements described in the above embodiment and this modified example.
  • Modification 3> 26 to 31 show a modified example of the planar configuration of the imaging device 1 according to the above embodiment.
  • FIG. 26 shows a schematic planar configuration of the first substrate 100, and corresponds to FIG. 7B described in the above embodiment.
  • FIG. 27 shows a schematic planar configuration of the semiconductor layer 200S of the second substrate 200 near the surface, and corresponds to FIG. 8 described in the above embodiment.
  • FIG. 28 shows a schematic configuration of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and each part of the first substrate 100, and corresponds to FIG. 9 described in the above embodiment.
  • FIG. 29 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, and corresponds to FIG. 10 described in the above embodiment.
  • FIG. 26 shows a schematic planar configuration of the first substrate 100, and corresponds to FIG. 7B described in the above embodiment.
  • FIG. 27 shows a schematic planar configuration of the semiconductor layer 200S of the second substrate 200 near the surface, and corresponds
  • FIG. 30 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, and corresponds to FIG. 11 described in the above embodiment.
  • FIG. 31 shows an example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to FIG. 12 described in the above embodiment.
  • the semiconductor layer 200S of the second substrate 200 extends in the H direction ( Figure 28). In other words, this roughly corresponds to the planar configuration of the imaging device 1 shown in Figure 21 above, etc., rotated 90 degrees.
  • the pixel sharing unit 539 of the first substrate 100 is formed across a pixel region of 2 rows by 2 columns, as described in the above embodiment, and has a substantially square planar shape ( FIG. 26 ).
  • the transfer gates TG1, TG2 of pixels 541A and 541B in one pixel row extend toward the center of the pixel sharing unit 539 in the V direction
  • the transfer gates TG3, TG4 of pixels 541C and 541D in the other pixel row extend toward the outside of the pixel sharing unit 539 in the V direction.
  • the pad portion 120 connected to the floating diffusion FD is provided in the center of the pixel sharing unit 539, and the pad portion 121 connected to the VSS contact region 118 is provided at the end of the pixel sharing unit 539 at least in the V direction (in the V direction and H direction in FIG. 26).
  • the V direction positions of the through electrodes TGV1 and TGV2 of the transfer gates TG1 and TG2 approach the V direction position of the through electrode 120E
  • the V direction positions of the through electrodes TGV3 and TGV4 of the transfer gates TG3 and TG4 approach the V direction position of the through electrode 121E (FIG. 28). Therefore, for the same reason as described in the above embodiment, the width (size in the V direction) of the semiconductor layer 200S extending in the H direction can be increased. This makes it possible to increase the size of the amplification transistor AMP and suppress noise.
  • each pixel circuit 210 the selection transistor SEL and the amplification transistor AMP are arranged side by side in the H direction, and the reset transistor RST is arranged adjacent to the selection transistor SEL in the V direction with the insulating region 212 between them ( Figure 27).
  • the FD conversion gain switching transistor FDG is arranged side by side with the reset transistor RST in the H direction.
  • the VSS contact region 218 is provided in an island shape in the insulating region 212.
  • the third wiring layer W3 extends in the H direction ( Figure 30)
  • the fourth wiring layer W4 extends in the V direction ( Figure 31).
  • An imaging device 1 having such a second substrate 200 can also obtain the same effects as those described in the above embodiment.
  • the arrangement of the pixel sharing units 539 of the second substrate 200 is not limited to the arrangement described in the above embodiment and this modification.
  • the semiconductor layer 200S described in the above embodiment and modification 1 may extend in the H direction.
  • Fig. 32 is a schematic diagram showing a modified cross-sectional configuration of the imaging device 1 according to the above embodiment.
  • Fig. 32 corresponds to Fig. 3 described in the above embodiment.
  • the imaging device 1 has contact portions 203, 204, 303, 304 at positions facing the center of the pixel array section 540, in addition to the contact portions 201, 202, 301, 302.
  • the imaging device 1 of this modified example differs from the imaging device 1 described in the above embodiment.
  • the contact portions 203 and 204 are provided on the second substrate 200 and are exposed at the bonding surface with the third substrate 300.
  • the contact portions 303 and 304 are provided on the third substrate 300 and are exposed at the bonding surface with the second substrate 200.
  • the contact portion 203 is in contact with the contact portion 303, and the contact portion 204 is in contact with the contact portion 304. That is, in this imaging device 1, the second substrate 200 and the third substrate 300 are connected by the contact portions 201, 202, 301, and 302 as well as the contact portions 203, 204, 303, and 304.
  • FIG. 33 the input signal input from the outside to the imaging device 1 and the paths of the power supply potential and reference potential are indicated by arrows.
  • Figure 34 the signal path of the pixel signal output from the imaging device 1 to the outside is indicated by arrows.
  • an input signal input to the imaging device 1 via the input section 510A is transmitted to the row driver section 520 of the third substrate 300, and a row drive signal is generated in the row driver section 520.
  • This row drive signal is sent to the second substrate 200 via the contact sections 303, 203.
  • this row drive signal reaches each of the pixel sharing units 539 of the pixel array section 540 via the row drive signal line 542 in the wiring layer 200T.
  • the drive signals other than the transfer gate TG are input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven.
  • the drive signal of the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through-hole electrode TGV, and pixels 541A, 541B, 541C, and 541D are driven.
  • the power supply potential and the reference potential supplied to the input section 510A (input terminal 511) of the third substrate 300 from the outside of the imaging device 1 are sent to the second substrate 200 via the contact sections 303 and 203, and are supplied to the pixel circuits 210 of each pixel sharing unit 539 via wiring in the wiring layer 200T.
  • the reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through-hole electrode 121E.
  • the pixel signals photoelectrically converted in the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are sent to the pixel circuit 210 of the second substrate 200 for each pixel sharing unit 539.
  • a pixel signal based on this pixel signal is sent from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact sections 204 and 304.
  • This pixel signal is processed in the column signal processing section 550 and image signal processing section 560 of the third substrate 300, and then output to the outside via the output section 510B.
  • the imaging device 1 having such contact parts 203, 204, 303, 304 can also achieve the same effects as those described in the above embodiment.
  • the position and number of the contact parts can be changed according to the design of the circuit of the third substrate 300, which is the destination of the wiring via the contact parts 303, 304.
  • Fig. 35 shows a modified cross-sectional configuration of the imaging device 1 according to the above embodiment.
  • Fig. 35 corresponds to Fig. 6 described in the above embodiment.
  • a transfer transistor TR having a planar structure is provided on the first substrate 100.
  • the imaging device 1 of this modified example differs from the imaging device 1 described in the above embodiment.
  • the transfer gate TG is formed only by the horizontal portion TGB. In other words, the transfer gate TG does not have a vertical portion TGA, and is disposed opposite the semiconductor layer 100S.
  • An imaging device 1 having such a planar-structure transfer transistor TR can achieve the same effects as those described in the above embodiment. Furthermore, by providing a planar-type transfer gate TG on the first substrate 100, the photodiode PD can be formed closer to the surface of the semiconductor layer 100S than when a vertical transfer gate TG is provided on the first substrate 100, and this can be considered to increase the saturation signal quantity (QS). In addition, the method of forming a planar-type transfer gate TG on the first substrate 100 requires fewer manufacturing steps than the method of forming a vertical transfer gate TG on the first substrate 100, and is therefore less likely to have adverse effects on the photodiode PD due to the manufacturing steps.
  • Fig. 36 shows a modified example of the pixel circuit of the imaging device 1 according to the above embodiment.
  • Fig. 36 corresponds to Fig. 4 described in the above embodiment.
  • a pixel circuit 210 is provided for each pixel (pixel 541A). That is, the pixel circuit 210 is not shared by multiple pixels.
  • the imaging device 1 of this modified example differs from the imaging device 1 described in the above embodiment.
  • the imaging device 1 of this modified example is the same as the imaging device 1 described in the above embodiment in that the pixel 541A and the pixel circuit 210 are provided on different substrates (first substrate 100 and second substrate 200). Therefore, the imaging device 1 of this modified example can also obtain the same effects as those described in the above embodiment.
  • Variation 7> 37 shows a modified example of the planar configuration of pixel isolation section 117 described in the above embodiment. Gaps may be provided in pixel isolation section 117 surrounding pixels 541A, 541B, 541C, and 541D. That is, pixels 541A, 541B, 541C, and 541D do not have to be entirely surrounded by pixel isolation section 117. For example, the gaps in pixel isolation section 117 are provided near pad sections 120 and 121 (see FIG. 7B).
  • the pixel separator 117 has an FTI structure that penetrates the semiconductor layer 100S, but the pixel separator 117 may have a configuration other than an FTI structure.
  • the pixel separator 117 does not have to be arranged to completely penetrate the semiconductor layer 100S, and may have a so-called DTI (Deep Trench Isolation) structure.
  • Variation 8> As shown in each of the above-described embodiments and modified examples, in the present disclosure, at least between the first substrate 100 and the second substrate 200, the potential of the floating diffusion layer (FD) in the pixel 541 and the pixel circuit 210 is shared by a connection using a metal (copper is one non-limiting example).
  • the signal generated by the photodiode PD which is the light receiving element, is transferred to the floating diffusion FD by the transfer transistor TR.
  • the ground voltage that serves as the reference for this signal is defined on each substrate.
  • FIG. 38 shows a modified example of the pixel circuit of the imaging device 1 according to the above embodiment.
  • FIG. 38 corresponds to FIG. 4 described in the above embodiment.
  • FIG. 38 shows an example in which one of the pixels 541 in FIG. 4 is provided with an amplifying transistor, i.e., an example in which each pixel has a floating diffusion FD.
  • the photodiode PD outputs a signal based on the intensity of the received light.
  • the photodiode PD formed on the first substrate 100 has, for example, an anode potential set to the first ground potential GND1.
  • the transfer transistor TR formed on the first substrate 100 has a body potential set to the first ground potential GND1.
  • the elements formed on the second substrate 200 have their ground potential set to the second ground potential GND2.
  • the body potential of the amplifying transistor AMP formed on the second substrate 200 is the second ground potential GND2.
  • This second ground potential GND2 is a different potential from the first ground potential GND1.
  • a signal based on the intensity of light received by the photodiode PD arranged on the first substrate 100 is amplified by the amplifier transistor AMP arranged on the second substrate 200 and transmitted to the vertical signal line 543.
  • the ground potentials that serve as the reference potentials for these are set to different potentials.
  • the first substrate 100 may be provided with a capacitor C1 that forms a potential relative to the floating diffusion FD with the first ground potential GND1 as a reference.
  • the second substrate 200 may be provided with a capacitor C2 that forms a potential with respect to the floating diffusion FD relative to the second ground potential GND2.
  • capacitance can be arranged on each substrate to create an appropriate floating diffusion FD potential.
  • the configuration may not include capacitors C1 and C2, as shown in Figures 4 and 36.
  • the imaging device 1 may be configured to provide an analog-to-digital conversion circuit (ADC) for each pixel. More specifically, it may be configured to provide an ADC for each photodiode PD.
  • ADC analog-to-digital conversion circuit
  • Figure 40 is a diagram showing yet another example of an equivalent circuit relating to this modified example.
  • pixel sharing units 539 are the repeating units, and these are repeatedly arranged in an array consisting of row and column directions.
  • the first ground potential GND1 which is the ground potential on the first substrate 100
  • the second ground potential GND2 which is the ground potential on the second substrate 200
  • the photodiode PD which is a light receiving element
  • the transfer transistor TR may be controlled to the first ground potential GND1.
  • the planar layout of transistors, gates, contacts, etc. on the first substrate 100 and the second substrate 200 may be, by way of non-limiting example, similar to those shown in Figures 7A, 7B, and 8, or may be another arrangement such as that shown in Figure 9 and subsequent figures.
  • the electrodes connected to the ground potential are connected to the first ground potential GND1 and the second ground potential GND2 on the first substrate 100 and the second substrate 200, respectively.
  • the cross-sectional layout of the transistors, gates, contacts, etc. on the first substrate 100 and the second substrate 200 can be the same as or similar to each of the above-mentioned forms, to the extent that the first ground potential GND1 and the second ground potential GND2 can be arranged to be different potentials.
  • Figure 41 is a potential diagram showing the potentials of the wiring etc. and the gates of the transistors on the first substrate 100 and the second substrate 200.
  • the upper part of the figure shows the structure of the wiring etc. and the gates of each transistor.
  • the floating diffusions FD of the first substrate 100 and the second substrate 200 are at the same potential as the gate of the amplifying transistor AMP via contacts.
  • the contacts connecting the floating diffusions FD may be, for example, metal.
  • the metal may be copper.
  • Figure 41 shows the range of potential at each gate, wiring, etc.
  • the potential diagram shown at the bottom is a graph that indicates increasingly negative values as you go up the page, and increasingly positive values as you go down the page.
  • the second ground potential GND2 is, for example, a more positive potential than the first ground potential GND1.
  • the first ground potential GND1 may be a negative bias potential.
  • the second ground potential GND2 may be 0 [V].
  • the reset transistor RST resets the potential of the floating diffusion FD of the second substrate 200, which is connected to the floating diffusion FD of the first substrate 100, to the potential connected to the power supply line VDD, by applying a voltage to the gate.
  • the potential of this gate can be in a range higher than the second ground potential GND2, as shown in the figure.
  • the voltage applied to the gate of the transfer transistor TR is based on the first ground potential GND1, which is a negative bias, for example.
  • the transfer transistor TR turns off when a voltage that is more negative than the first ground potential GND1 is applied to the gate, and a voltage exceeding the threshold voltage is applied when the transfer is to be performed.
  • the transfer transistor TR transfers the signal from the cathode side of the photodiode PD, which is in a higher state than the floating diffusion FD on the first substrate 100, to the reset floating diffusion FD.
  • This signal is transferred via the contact to the floating diffusion FD on the second substrate 200 and applied to the gate of the amplifying transistor AMP.
  • the amplifying transistor AMP which forms a source follower circuit, outputs a voltage based on the level of the potential applied to its gate to the drain of the selection transistor SEL.
  • the voltage applied to the gate of the selection transistor SEL can be a voltage based on the second ground potential GND2.
  • the body of the amplifying transistor AMP can also be at the second ground potential GND2.
  • a signal based on the intensity of the light received by the pixel is transmitted to the vertical signal line 543 via the selection transistor SEL at the appropriate timing.
  • the voltage range that determines the High/Low level of the signal on the first substrate 100 and the voltage range that determines the High/Low level of the signal on the second substrate 200 can be set to different potentials.
  • the range of voltages applied to the gates of the transistors in the second substrate 200 can be made significantly narrower than the range of voltages applied to the gates of the transistors in the first substrate 100, which has a photodiode PD.
  • transistors that operate at 5V can be used on the first substrate 100, while transistors that operate at 3V can be used on the second substrate 200.
  • the first ground potential GND1 For example, by lowering the first ground potential GND1, it is possible to increase the upper and lower ranges (potential difference) of the saturation signal of the photodiode PD while lowering the potential difference applied to the transistor formed on the second substrate 200.
  • the ground potential As described above, it is possible, for example, to make the withstand voltage performance of the transistors provided on the second substrate 200 lower than the withstand voltage performance of the transistors provided on the first substrate 100.
  • the thickness of the gate oxide film and the width and distance of the wiring can be reduced on the second substrate 200, so that the layout efficiency on the second substrate 200 can be improved regardless of the saturation signal level of the photodiode PD.
  • FIG. 42 is a schematic diagram showing an example of the configuration and cross section of a semiconductor substrate that forms the light receiving elements, pixel circuits, and logic circuits of the imaging device 1.
  • the imaging device 1 may include a first substrate 100, a second substrate 200, and a third substrate 300.
  • the first substrate 100 includes, for example, at least a photodiode PD, which is a light receiving element.
  • the second substrate 200 includes, for example, a pixel circuit that controls a signal output from the photodiode PD, and the pixel circuit includes various pixel transistors.
  • the floating diffusion FD of the first substrate 100 and the floating diffusion FD of the second substrate 200 may be connected via a contact region and controlled to the same potential.
  • the ground potentials of the first substrate 100 and the second substrate 200 may be different potentials as described above.
  • the third substrate 300 is provided with, for example, a logic circuit that performs various signal processing and image processing on the signals output from the pixel circuits.
  • the third substrate 300 may be controlled at the same ground potential as the second substrate 200.
  • This third substrate 300 may also be combined with the first substrate 100 and second substrate 200 described above to form a pixel unit.
  • the diagram on the right shows a non-limiting example of the circuit layout for this three-layer structure.
  • FIG. 43 is a schematic diagram showing an example of the configuration and cross section of a semiconductor substrate that forms the light receiving elements, pixel circuits, and logic circuits of the imaging device 1.
  • the imaging device 1 may include, in one non-limiting embodiment, a first substrate 100, a second substrate 200, and a third substrate 300.
  • the first substrate 100 includes, for example, at least a photodiode PD, which is a light receiving element.
  • the second substrate 200 includes, for example, a pixel circuit that controls a signal output from the photodiode PD, and the pixel circuit includes various pixel transistors.
  • the floating diffusion FD of the first substrate 100 and the floating diffusion FD of the second substrate 200 may be connected via a contact region and controlled to the same potential.
  • the ground potentials of the first substrate 100 and the second substrate 200 may be different potentials as described above.
  • the third substrate 300 is provided with, for example, a part of the pixel circuit and a logic circuit that performs various signal processing and image processing on the signal output from the pixel circuit.
  • the third substrate 300 may be controlled at the same ground potential as the second substrate 200.
  • This third substrate 300 may be combined with the first substrate 100 and the second substrate 200 described above to form a pixel unit. In this way, a part of the pixel circuit may be provided on the third substrate 300.
  • FIG. 44 is a schematic diagram showing an example of the configuration and cross section of a semiconductor substrate that forms the light receiving elements, pixel circuits, and logic circuits of the imaging device 1.
  • the diagram on the left shows an example of the configuration of a semiconductor substrate.
  • the imaging device 1 may include a first substrate 100 and a second substrate 200.
  • the first substrate 100 includes, for example, at least a photodiode PD, which is a light receiving element.
  • the second substrate 200 includes, for example, a pixel circuit that controls the signal output from the photodiode PD, and a logic circuit that performs various signal processing and image processing on the signal output from the pixel circuit.
  • the pixel circuit and logic circuit can each include a plurality of transistors.
  • the floating diffusion FD of the first substrate 100 and the floating FD of the second substrate 200 may be connected via a contact region and controlled to the same potential.
  • the ground potentials of the first substrate 100 and the second substrate 200 may be set to different potentials as described above.
  • logic circuits can be provided on the second substrate 200.
  • the ground potentials of the photodiode PD, the amplifying transistor AMP, etc. can be set to the same potential or different potentials as desired.
  • the saturation signal amount of the photodiode PD can be increased and the degree of freedom in layout can be further improved.
  • FIG. 45 shows an example of the configuration of an equivalent circuit according to one embodiment.
  • the potential of the well of the amplifier transistor AMP may be set equal to the potential of the source of the amplifier transistor AMP via the body region, rather than being set to the second ground potential GND2.
  • the source and well potentials of the amplifier transistor AMP become equal, and by setting the modulation depth of the amplifier gate forming the source follower circuit to 1, the potential conversion efficiency of the floating diffusion FD can be increased.
  • FIG. 46 shows an example of the configuration of an equivalent circuit according to one embodiment.
  • the reset transistor RST may be provided on the first substrate 100 instead of the second substrate 200.
  • the reset transistor RST may be formed on the same substrate as the transfer transistor TR, the floating diffusion FD for locating the reset transistor RST can be eliminated from the second substrate 200.
  • FIG. 47 shows an example of the configuration of an equivalent circuit according to one embodiment.
  • a reset transistor RST and an amplifying transistor AMP may be provided on the first substrate 100.
  • the distance between the floating diffusion FD and the amplifying transistor AMP can be made shorter, thereby further increasing the conversion efficiency of the signal stored in the floating diffusion FD.
  • the components of the pixel unit other than the photodiode PD, transfer diode TR, and floating diffusion FD arranged on the first substrate 100 may be arranged on either the first substrate 100 or the second substrate 200.
  • the pixel unit can include circuit elements such as transistors other than those shown in these figures.
  • FIG. 48 shows an example of the configuration of an equivalent circuit according to one embodiment.
  • the pixel circuit can be configured to have floating diffusions FD1, FD2, and FD3, with an FD conversion gain switching transistor FDG disposed between floating diffusions FD1 and FD2, and an FD conversion gain switching transistor FCG disposed between floating diffusions FD2 and FD3.
  • the floating diffusion FD1 may be connected to a first ground potential GND1 via a capacitor C1 on the first substrate 100, and to a second ground potential GND2 via a capacitor C2 on the second substrate 200.
  • the floating diffusion FD2 may be connected to a second ground potential GND2 via a capacitor C3.
  • the floating diffusion FD3 may be connected to a second ground potential GND2 via capacitor C4 and to a power supply voltage FD_VDD via capacitor C5.
  • FD conversion gain switching transistors FDG, FDC are arranged on the second substrate 200, and their ground potential is set to the second ground potential GND2.
  • the floating diffusions FD2, FD3 are formed on the second substrate 200.
  • the floating diffusion FD1 and floating diffusion FD2 are connected, and the conversion efficiency can be controlled to be lower than when the FD conversion gain switching transistor FDG is turned off.
  • the floating diffusions FD1 and FD2 are connected to the floating diffusion FD3, making the conversion efficiency lower than when only the FD conversion gain switching transistor FDG is turned on.
  • the ground voltage of the transistor that switches the FD conversion gain can be set in the same way as the ground voltage of other transistors on the substrate.
  • the transistor that switches the transfer conversion gain does not need to be a two-stage configuration, and it is also possible to have a configuration that has only a single-stage FD conversion gain switching transistor FCG, as shown in Figures 4 and 6, etc.
  • Figure 49 shows another example of an equivalent circuit with an FD conversion gain switching transistor.
  • the FD conversion gain switching transistors FDG, FCG may be provided on the first substrate 100.
  • the ground potentials of the FD conversion gain switching transistors FDG, FCG can be set to the first ground potential GND1.
  • the floating diffusions FD2, FD3 are formed on the first substrate 100.
  • Figure 50 shows another example of a bypass circuit equipped with an FD conversion gain switching transistor.
  • FD conversion gain switching transistors FDG, FCG can also be arranged in an imaging device 1 in which a first substrate 100, a second substrate 200, and a third substrate 300 are stacked.
  • the ground potential of the first board 100 is set to a first ground potential GND1
  • the ground potential of the second board 200 is set to a second ground potential GND2
  • the ground potential of the third board 300 is set to a third ground potential GND3.
  • floating diffusion FD1 is formed on first substrate 100 and second substrate 200
  • floating diffusion FD2 is formed on second substrate 200 and third substrate 300
  • floating diffusion FD3 is formed on third substrate 300.
  • the FD conversion gain switching transistor FDG is disposed on the second substrate 200, and its ground potential is set to the second ground potential GND2.
  • the FD conversion gain switching transistor FCG is disposed on the third substrate 300, and its ground potential is set to the third ground potential GND3.
  • the transfer transistor TRG is arranged on the first substrate 100 with the ground potential set to a first ground potential GND1
  • the amplifying transistor AMP is arranged on the second substrate 200 with the ground potential set to a second ground potential GND2
  • the selection transistor SEL is arranged on the third substrate 300 with the ground potential set to a third ground potential GND3.
  • the transistor allocation described above is shown as a non-limiting example, and can be formed on any substrate as long as it does not conflict with the circuit design.
  • FIG. 52 is a diagram showing a non-limiting example of application of an equivalent circuit according to one embodiment.
  • FIG. 55 is a plan view showing a portion of the layout of the first substrate 100 of the equivalent circuit of FIG. 52.
  • the pixel unit further includes an offset transistor OFG, a memory transfer transistor TRY, and a memory region TRX on the first substrate 100.
  • the pixel unit is not limited to CMOS image sensors having a typical four transistors, and can also be used on substrates compatible with a global shutter.
  • the offset transistor OFG is a transistor that connects the cathode of the photodiode PD to the offset potential OFG_VDD, which offsets the potential of the cathode of the photodiode PD.
  • the offset transistor OFG is turned on, the potential of the cathode of the photodiode PD is controlled to the offset potential OFG_VDD.
  • the memory transfer transistor TRY is a transistor that transfers the potential of the cathode of the photodiode PD to the memory area TRX at the appropriate timing.
  • the potential of the memory area TRX is transferred to the floating diffusion FD at the appropriate timing by the transfer transistor TR.
  • the signal intensity at the time of exposure can be transferred to the memory area TRX regardless of the timing of the scan, and the signal held in this memory area TRX can be transferred to the floating diffusion FD at an appropriate timing.
  • This operation makes it possible to perform imaging using the global shutter method, which aligns the timing of signal acquisition.
  • Figure 55 shows the regions of each transistor and the contact regions to which voltages are applied in the first substrate 100 of Figure 52.
  • GND1 and OFG_VDD in the figure indicate contacts to which the respective voltages are applied, and Cxxx indicate contacts that supply voltages to be applied to the gates of the respective transistors.
  • the memory MEM is formed, for example, with a memory transfer transistor TRY and a memory region TRX.
  • the cathode potential of the photodiode PD is controlled to the offset potential OFG_VDD via the offset transistor OFG at a predetermined timing.
  • a signal corresponding to the intensity of the signal acquired at each pixel unit is accumulated at the cathode of the photodiode PD.
  • the memory transfer transistor TRY turns on at any time and transfers the signal held at the cathode of the photodiode PD to the memory area TRX.
  • the transfer transistor TR can be turned on at any time to transfer the signal to the floating diffusion FD. This signal transfer is performed appropriately by the movement of electric charge.
  • the configuration disclosed herein for setting a ground potential for each substrate can be used to acquire image signals in a charge domain type global shutter system.
  • FIG. 53 shows an example of a schematic configuration of an imaging system 7 including the imaging device 1 according to the above embodiment and its modified example.
  • the imaging system 7 is, for example, an electronic device such as an imaging device, such as a digital still camera or a video camera, or a mobile terminal device, such as a smartphone or a tablet terminal.
  • the imaging system 7 includes, for example, the imaging device 1 according to the above embodiment and its modified examples, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248.
  • the imaging device 1 according to the above embodiment and its modified examples, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are connected to each other via a bus line 249.
  • the imaging device 1 outputs image data corresponding to incident light.
  • the DSP circuit 243 is a signal processing circuit that processes the signal (image data) output from the imaging device 1 according to the above embodiment and its modified examples.
  • the frame memory 244 temporarily holds the image data processed by the DSP circuit 243 on a frame-by-frame basis.
  • the display unit 245 is a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving images or still images captured by the imaging device 1 according to the above embodiment and its modified examples.
  • the memory unit 246 records image data of moving images or still images captured by the imaging device 1 according to the above embodiment and its modified examples in a recording medium such as a semiconductor memory or a hard disk.
  • the operation unit 247 issues operation commands for various functions of the imaging system 7 according to operations by a user.
  • the power supply unit 248 appropriately supplies various types of power to these devices as operating power sources for the imaging device 1, DSP circuit 243, frame memory 244, display unit 245, storage unit 246, and operation unit 247 according to the above-described embodiment and its modified examples.
  • Figure 54 shows an example of a flowchart of the imaging operation in the imaging system 7.
  • the user issues an instruction to start imaging by operating the operation unit 247 (step S101).
  • the operation unit 247 then transmits an imaging command to the imaging device 1 (step S102).
  • the imaging device 1 Upon receiving the imaging command, the imaging device 1 (specifically, the system control circuit 36) performs imaging using a predetermined imaging method (step S103).
  • the imaging device 1 outputs image data obtained by imaging to the DSP circuit 243.
  • the image data refers to data for all pixels of pixel signals generated based on the electric charges temporarily stored in the floating diffusion FD.
  • the DSP circuit 243 performs a predetermined signal processing (e.g., noise reduction processing) based on the image data input from the imaging device 1 (step S104).
  • the DSP circuit 243 stores the image data that has been subjected to the predetermined signal processing in the frame memory 244, and the frame memory 244 stores the image data in the storage unit 246 (step S105). In this manner, imaging is performed in the imaging system 7.
  • the imaging device 1 according to the above embodiment and its modified example is applied to an imaging system 7. This allows the imaging device 1 to be made smaller or have higher resolution, making it possible to provide a small or high-resolution imaging system 7.
  • the technology according to the present disclosure (the present technology) can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving object such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.
  • FIG. 55 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • the functional configuration of the integrated control unit 12050 includes a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (Interface) 12053.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle in accordance with various programs.
  • the drive system control unit 12010 functions as a control device for a drive force generating device for generating a drive force for the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
  • the body control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs.
  • the body control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps.
  • radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body control unit 12020.
  • the body control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
  • the outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the imaging unit 12031 is connected to the outside-vehicle information detection unit 12030.
  • the outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images.
  • the outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface based on the received images.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received.
  • the imaging unit 12031 can output the electrical signal as an image, or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects information inside the vehicle.
  • a driver state detection unit 12041 that detects the state of the driver is connected.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
  • the microcomputer 12051 can calculate control target values for the driving force generating device, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010.
  • the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which is to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc., based on information about the surroundings of the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040.
  • the microcomputer 12051 can also output control commands to the body control unit 12020 based on information outside the vehicle acquired by the outside-vehicle information detection unit 12030.
  • the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.
  • the audio/image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • Figure 56 shows an example of the installation position of the imaging unit 12031.
  • vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as imaging unit 12031.
  • the imaging units 12101, 12102, 12103, 12104, 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100.
  • the imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly obtain images of the front of the vehicle 12100.
  • the imaging units 12102, 12103 provided at the side mirrors mainly obtain images of the sides of the vehicle 12100.
  • the imaging unit 12104 provided at the rear bumper or back door mainly obtains images of the rear of the vehicle 12100.
  • the forward images acquired by the imaging units 12101 and 12105 are primarily used to detect preceding vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc.
  • FIG. 56 shows an example of the imaging ranges of the imaging units 12101 to 12104.
  • Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door.
  • an overhead image of the vehicle 12100 viewed from above can be obtained by overlaying the image data captured by the imaging units 12101 to 12104.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 can obtain the distance to each solid object within the imaging range 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract, as a preceding vehicle, a solid object that is the closest solid object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 KM/H or faster). Furthermore, the microcomputer 12051 can set a vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on the driver's operation.
  • automatic braking control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles.
  • the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by forcibly decelerating or steering the vehicle to avoid collision via the drive system control unit 12010.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the image captured by the imaging units 12101 to 12104.
  • the recognition of a pedestrian is performed by, for example, a procedure of extracting feature points in the image captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing a pattern matching process on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian.
  • the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. Additionally, the audio/video output unit 12052 may control the display unit 12062 to display an icon indicating a pedestrian or the like at a desired position.
  • the above describes an example of a mobile object control system to which the technology disclosed herein can be applied.
  • the technology disclosed herein can be applied to the imaging unit 12031 of the configuration described above.
  • the imaging device 1 according to the above embodiment and its modified example can be applied to the imaging unit 12031.
  • FIG. 57 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.
  • an operator (doctor) 11131 is shown using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a patient bed 11133.
  • the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.
  • the endoscope 11100 is composed of a tube 11101, the tip of which is inserted at a predetermined length into the body cavity of the patient 11132, and a camera head 11102 connected to the base end of the tube 11101.
  • the endoscope 11100 is configured as a so-called rigid scope having a rigid tube 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible tube.
  • the endoscope 11101 has at its tip an opening into which an objective lens is fitted.
  • a light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the tube 11101 by a light guide extending inside the tube 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132.
  • the endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.
  • the camera head 11102 contains an optical system and an image sensor, and the reflected light (observation light) from the object being observed is focused onto the image sensor by the optical system.
  • the image sensor converts the observation light into an electric signal corresponding to the observation light, i.e., an image signal corresponding to the observed image.
  • the image signal is sent to the camera control unit (CCU: Camera Control Unit) 11201 as RAW data.
  • CCU Camera Control Unit
  • the CCU 11201 is composed of a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit), and generally controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), in order to display an image based on the image signal.
  • a CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • the display device 11202 under the control of the CCU 11201, displays an image based on the image signal that has been subjected to image processing by the CCU 11201.
  • the light source device 11203 is composed of a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 11100 when photographing the surgical site, etc.
  • a light source such as an LED (Light Emitting Diode) and supplies illumination light to the endoscope 11100 when photographing the surgical site, etc.
  • the input device 11204 is an input interface for the endoscopic surgery system 11000.
  • a user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204.
  • a user can input instructions to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.
  • the treatment tool control device 11205 controls the drive of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc.
  • the insufflation device 11206 sends gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity, for the purpose of ensuring the field of view through the endoscope 11100 and ensuring the working space for the surgeon.
  • the recorder 11207 is a device capable of recording various types of information related to the surgery.
  • the printer 11208 is a device capable of printing various types of information related to the surgery in various formats, such as text, images, or graphs.
  • the light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site can be composed of a white light source composed of, for example, an LED, a laser light source, or a combination of these.
  • a white light source composed of, for example, an LED, a laser light source, or a combination of these.
  • the white light source is composed of a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so that the white balance of the captured image can be adjusted in the light source device 11203.
  • the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals.
  • the driving of the image sensor of the camera head 11102 may be controlled in synchronization with the timing of the change in the light intensity to acquire images in a time-division manner, and by combining these images, it is possible to generate an image with a high dynamic range that is free of so-called blackout and whiteout.
  • the light source device 11203 may also be configured to supply light of a predetermined wavelength band corresponding to special light observation.
  • special light observation for example, by utilizing the wavelength dependency of light absorption in body tissue, a narrow band of light is irradiated compared to the light irradiated during normal observation (i.e., white light), and a predetermined tissue such as blood vessels on the surface of the mucosa is photographed with high contrast, which is called narrow band imaging.
  • special light observation may be performed by fluorescence observation, in which an image is obtained by fluorescence generated by irradiating excitation light.
  • excitation light is irradiated to body tissue and the fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally injected into the body tissue and excitation light corresponding to the fluorescent wavelength of the reagent is irradiated to the body tissue to obtain a fluorescent image.
  • the light source device 11203 may be configured to supply narrow band light and/or excitation light corresponding to such special light observation.
  • FIG. 58 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in FIG. 57.
  • the camera head 11102 has a lens unit 11401, an imaging section 11402, a drive section 11403, a communication section 11404, and a camera head control section 11405.
  • the CCU 11201 has a communication section 11411, an image processing section 11412, and a control section 11413.
  • the camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.
  • Lens unit 11401 is an optical system provided at the connection with the telescope tube 11101. Observation light taken in from the tip of the telescope tube 11101 is guided to the camera head 11102 and enters the lens unit 11401. Lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.
  • the imaging unit 11402 is composed of an imaging element.
  • the imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type).
  • each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these image signals.
  • the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. By performing a 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical site.
  • multiple lens units 11401 may be provided corresponding to each imaging element.
  • the imaging unit 11402 does not necessarily have to be provided in the camera head 11102.
  • the imaging unit 11402 may be provided inside the telescope tube 11101, immediately after the objective lens.
  • the driving unit 11403 is composed of an actuator, and moves the zoom lens and focus lens of the lens unit 11401 a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.
  • the communication unit 11404 is composed of a communication device for transmitting and receiving various information to and from the CCU 11201.
  • the communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.
  • the communication unit 11404 also receives control signals from the CCU 11201 for controlling the operation of the camera head 11102, and supplies these to the camera head control unit 11405.
  • the control signals include information relating to the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during imaging, and/or information specifying the magnification and focus of the captured image.
  • the imaging conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal.
  • the endoscope 11100 will be equipped with the so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.
  • the camera head control unit 11405 controls the operation of the camera head 11102 based on a control signal from the CCU 11201 received via the communication unit 11404.
  • the communication unit 11411 is composed of a communication device for transmitting and receiving various information to and from the camera head 11102.
  • the communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.
  • the communication unit 11411 transmits a control signal to the camera head 11102 for controlling the operation of the camera head 11102.
  • the image signal and the control signal can be transmitted by electrical communication, optical communication, etc.
  • the image processing unit 11412 performs various image processing operations on the image signal, which is RAW data, sent from the camera head 11102.
  • the control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100, and the display of the captured images obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.
  • the control unit 11413 also displays the captured image showing the surgical site on the display device 11202 based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize surgical tools such as forceps, specific body parts, bleeding, mist generated when using the energy treatment tool 11112, and the like, by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various types of surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.
  • various image recognition techniques such as forceps, specific body parts, bleeding, mist generated when using the energy treatment tool 11112, and the like.
  • the transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.
  • communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.
  • the technology disclosed herein can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100.
  • the technology disclosed herein can be suitably applied to the imaging unit 11402, it is possible to reduce the size or increase the resolution of the imaging unit 11402, thereby making it possible to provide a small or high-resolution endoscope 11100.
  • the present disclosure can be configured as follows:
  • a first substrate and a second substrate Equipped with The first substrate is A light receiving element that outputs a signal based on the intensity of the received light, the ground potential is a first ground potential;
  • the second substrate is a transistor that outputs a signal based on a signal output from the light receiving element; the ground potential is a second ground potential different from the first ground potential; Solid-state imaging device.
  • the second ground potential is a more positive potential than the first ground potential.
  • the first ground potential is a negative bias potential.
  • a solid-state imaging device according to (2) or (3).
  • the second substrate is an amplifying transistor that amplifies a signal output from the light receiving element; Equipped with A solid-state imaging device according to any one of (1) to (4).
  • a thickness of a gate oxide film of a transistor provided on the second substrate is thinner than a thickness of a gate oxide film provided on the first substrate;
  • the first substrate and the second substrate are electrically connected via a metal.
  • a solid-state imaging device according to any one of (1) to (6).
  • the metal is copper.
  • the distance between the wirings on the second substrate is shorter than the distance between the wirings on the first substrate.
  • the first substrate and the second substrate are formed by stacking them.
  • a solid-state imaging device according to any one of (1) to (9).
  • Third board, Further equipped with The third substrate is The first substrate and the second substrate together form a pixel unit.
  • a solid-state imaging device according to any one of (1) to (10).
  • the signal acquired by the light receiving element is converted into an image signal by a charge domain type global shutter method.
  • a solid-state imaging device according to any one of (1) to (11).
  • the signal acquired by the light receiving element is converted into an image signal by a voltage domain type global shutter method.
  • a solid-state imaging device according to any one of (1) to (11).
  • the signal acquired by the light receiving element is converted into a digital signal by an analog-to-digital conversion circuit provided for each of the light receiving elements.
  • a solid-state imaging device according to any one of (1) to (13).
  • the amplifier transistor has a well potential and a source potential that are equal to each other and different from the second ground potential.
  • Imaging device 7: Imaging system
  • 100 first substrate
  • 100S, 200S, 300S Semiconductor layer
  • 100T, 200T, 300T wiring layer
  • 111 insulating film
  • 112 Fixed charge membrane
  • 113 first pinning region
  • 114 N-type semiconductor region
  • 115 P-well layer
  • 116 second pinning region
  • 117 pixel separation unit
  • 117A Light-shielding film
  • 117B insulating film
  • 118, 218 VSS contact area
  • 120E, 121E Through electrode
  • 124 Junctional membrane
  • 200 second substrate, 201, 202, 203, 204, 301, 302, 303, 304: contact parts
  • 212 Insulation area
  • 213 element isolation region
  • 300 third board
  • 401 Receiving lens, 541A,

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
PCT/JP2024/000469 2023-02-24 2024-01-11 固体撮像装置及び電子機器 Ceased WO2024176641A1 (ja)

Priority Applications (4)

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EP24759949.1A EP4672339A1 (en) 2023-02-24 2024-01-11 SEMICONDUCTOR IMAGING DEVICE AND ELECTRONIC DEVICE
JP2025502155A JPWO2024176641A1 (enExample) 2023-02-24 2024-01-11
CN202480012507.0A CN120693990A (zh) 2023-02-24 2024-01-11 固体摄像装置和电子设备
KR1020257030702A KR20250154420A (ko) 2023-02-24 2024-01-11 고체 촬상 장치 및 전자 기기

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Citations (7)

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Publication number Priority date Publication date Assignee Title
JP2009283552A (ja) * 2008-05-20 2009-12-03 Panasonic Corp 固体撮像素子
JP2013192015A (ja) * 2012-03-13 2013-09-26 Nippon Hoso Kyokai <Nhk> 固体撮像装置
JP2015159501A (ja) 2014-02-25 2015-09-03 ソニー株式会社 撮像素子および撮像装置
WO2016185839A1 (ja) * 2015-05-20 2016-11-24 ソニー株式会社 固体撮像装置および固体撮像装置の駆動方法
WO2020105713A1 (ja) * 2018-11-21 2020-05-28 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子
WO2021200174A1 (ja) * 2020-03-31 2021-10-07 ソニーセミコンダクタソリューションズ株式会社 撮像装置および電子機器
JP2022152974A (ja) * 2021-03-29 2022-10-12 ソニーセミコンダクタソリューションズ株式会社 撮像システム及び撮像装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009283552A (ja) * 2008-05-20 2009-12-03 Panasonic Corp 固体撮像素子
JP2013192015A (ja) * 2012-03-13 2013-09-26 Nippon Hoso Kyokai <Nhk> 固体撮像装置
JP2015159501A (ja) 2014-02-25 2015-09-03 ソニー株式会社 撮像素子および撮像装置
WO2016185839A1 (ja) * 2015-05-20 2016-11-24 ソニー株式会社 固体撮像装置および固体撮像装置の駆動方法
WO2020105713A1 (ja) * 2018-11-21 2020-05-28 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子
WO2021200174A1 (ja) * 2020-03-31 2021-10-07 ソニーセミコンダクタソリューションズ株式会社 撮像装置および電子機器
JP2022152974A (ja) * 2021-03-29 2022-10-12 ソニーセミコンダクタソリューションズ株式会社 撮像システム及び撮像装置

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