WO2024142212A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024142212A1
WO2024142212A1 PCT/JP2022/048098 JP2022048098W WO2024142212A1 WO 2024142212 A1 WO2024142212 A1 WO 2024142212A1 JP 2022048098 W JP2022048098 W JP 2022048098W WO 2024142212 A1 WO2024142212 A1 WO 2024142212A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
substrate
semiconductor device
semiconductor chip
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/048098
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
隆行 日坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2023529936A priority Critical patent/JP7327715B1/ja
Priority to US19/108,684 priority patent/US20260082989A1/en
Priority to PCT/JP2022/048098 priority patent/WO2024142212A1/ja
Priority to CN202280101341.0A priority patent/CN120457539A/zh
Priority to TW114113511A priority patent/TW202531518A/zh
Priority to TW112146287A priority patent/TWI897117B/zh
Publication of WO2024142212A1 publication Critical patent/WO2024142212A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/157—Containers comprising an insulating or insulated base having interconnections parallel to the insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips

Definitions

  • This disclosure relates to a semiconductor device.
  • Some semiconductor devices use hollow structure packages that are hollow inside.
  • a semiconductor chip is mounted inside the hollow structure package.
  • moisture and gas contained in the air in the hollow part can cause problems such as condensation inside the package.
  • Patent Document 1 discloses a semiconductor device in which part of the area where the package lid is attached is made breathable to prevent condensation and other problems inside the package.
  • Some semiconductor devices use molded packages, where the inside of the package is filled with resin.
  • the resin is filled so that it covers the semiconductor chip. Because resin is used in these types of packages, airtightness is not maintained, and moisture and gas can penetrate into the inside from the surrounding area.
  • the adhesives and resins used also contain moisture and gas. These factors can cause moisture and gas to reach the area around the semiconductor chip.
  • Patent Document 2 discloses a semiconductor device in which through holes are provided in the resin to prevent moisture from reaching the area around the semiconductor chip, and moisture and other substances are discharged to the outside.
  • JP 2002-124589 A Japanese Patent Application Laid-Open No. 9-219471
  • the increase in drain leakage current before and after the moisture resistance test is shown in FIG. 4. From this result, it can be seen that as the number of through-holes is increased, the increase in drain leakage current decreases. This is because the more through-holes there are, the more moisture and gas can be discharged from inside the package. It can also be seen that if there are 10 or more through-holes, the increase in drain leakage current is sufficiently small. Since the area of the opening portion when there are 10 through-holes is 1.96 mm2 , it is desirable to set the area of the opening portion of the through-hole 20 to 2 mm2 or more.
  • the shape of the opening of the through-hole 50 is a rectangle (including a square) with sides perpendicular to the surface of the semiconductor substrate 58. This rectangle extends from the top to the bottom of the side wall 46.
  • the length of the side parallel to the surface of the semiconductor substrate 58 of this rectangle is preferably 0.5 mm or more and 1 mm or less. By making this side length 0.5 mm or more, the effect of discharging moisture and gas can be improved. By making this side length 1 mm or less, it is possible to prevent the intrusion of foreign matter larger than this and to prevent deformation of the semiconductor element 62, etc. It is also possible to prevent electrical short circuits due to the intrusion of conductive foreign matter.
  • the total area of the opening of the through-hole 50 is preferably 2 mm2 or more. By making the area of the opening of the through-hole 50 2 mm2 or more, the effect of discharging moisture and gas can be improved.
  • the semiconductor element 62 is connected to a via hole 64, which is connected to a back electrode 66 formed on the back surface of the semiconductor substrate 58.
  • the through-hole 50 is provided in the side wall 46, a semiconductor device that can fully discharge moisture and gas can be obtained.
  • the substrate 72 is made of, for example, resin.
  • a semiconductor chip 14 is disposed on the substrate 72.
  • the semiconductor chip 14 is a chip manufactured using a semiconductor process and may be an active element or a passive element. It may also be a MEMS (Micro Electro Mechanical Systems).

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Led Device Packages (AREA)
  • Pressure Sensors (AREA)
  • Solid State Image Pick-Up Elements (AREA)
PCT/JP2022/048098 2022-12-27 2022-12-27 半導体装置 Ceased WO2024142212A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2023529936A JP7327715B1 (ja) 2022-12-27 2022-12-27 半導体装置
US19/108,684 US20260082989A1 (en) 2022-12-27 2022-12-27 Semiconductor apparatus
PCT/JP2022/048098 WO2024142212A1 (ja) 2022-12-27 2022-12-27 半導体装置
CN202280101341.0A CN120457539A (zh) 2022-12-27 2022-12-27 半导体装置
TW114113511A TW202531518A (zh) 2022-12-27 2023-11-29 半導體裝置
TW112146287A TWI897117B (zh) 2022-12-27 2023-11-29 半導體裝置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/048098 WO2024142212A1 (ja) 2022-12-27 2022-12-27 半導体装置

Publications (1)

Publication Number Publication Date
WO2024142212A1 true WO2024142212A1 (ja) 2024-07-04

Family

ID=87563009

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/048098 Ceased WO2024142212A1 (ja) 2022-12-27 2022-12-27 半導体装置

Country Status (5)

Country Link
US (1) US20260082989A1 (https=)
JP (1) JP7327715B1 (https=)
CN (1) CN120457539A (https=)
TW (2) TW202531518A (https=)
WO (1) WO2024142212A1 (https=)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04256346A (ja) * 1991-02-08 1992-09-11 Fujitsu Ltd 浸漬冷却用電子部品構造
JP2008227482A (ja) * 2007-02-16 2008-09-25 Yamaha Corp 半導体装置
WO2009011140A1 (ja) * 2007-07-19 2009-01-22 Fujikura Ltd. 半導体パッケージとその製造方法
JP2009253206A (ja) * 2008-04-10 2009-10-29 Sharp Corp 樹脂封止型半導体装置およびその実装構造

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI236116B (en) * 2004-11-04 2005-07-11 Advanced Semiconductor Eng High heat dissipation flip chip package structure
CN105378912B (zh) * 2014-06-09 2018-12-28 三菱电机株式会社 半导体封装件的制造方法以及半导体封装件
US9761540B2 (en) * 2015-06-24 2017-09-12 Micron Technology, Inc. Wafer level package and fabrication method thereof
DE102015223399B4 (de) * 2015-11-26 2018-11-08 Robert Bosch Gmbh Verfahren zum Verpacken mindestens eines Halbleiterbauteils und Halbleitervorrichtung
TWI848937B (zh) * 2018-07-24 2024-07-21 日商拓自達電線股份有限公司 屏蔽封裝體及屏蔽封裝體之製造方法
KR102711765B1 (ko) * 2019-03-06 2024-09-27 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
US11538731B2 (en) * 2019-03-28 2022-12-27 Intel Corporation Thermal solutions for package on package (PoP) architectures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04256346A (ja) * 1991-02-08 1992-09-11 Fujitsu Ltd 浸漬冷却用電子部品構造
JP2008227482A (ja) * 2007-02-16 2008-09-25 Yamaha Corp 半導体装置
WO2009011140A1 (ja) * 2007-07-19 2009-01-22 Fujikura Ltd. 半導体パッケージとその製造方法
JP2009253206A (ja) * 2008-04-10 2009-10-29 Sharp Corp 樹脂封止型半導体装置およびその実装構造

Also Published As

Publication number Publication date
TW202441721A (zh) 2024-10-16
JP7327715B1 (ja) 2023-08-16
US20260082989A1 (en) 2026-03-19
JPWO2024142212A1 (https=) 2024-07-04
TW202531518A (zh) 2025-08-01
TWI897117B (zh) 2025-09-11
CN120457539A (zh) 2025-08-08

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