WO2024135456A1 - 配線基板およびその製造方法 - Google Patents

配線基板およびその製造方法 Download PDF

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Publication number
WO2024135456A1
WO2024135456A1 PCT/JP2023/044427 JP2023044427W WO2024135456A1 WO 2024135456 A1 WO2024135456 A1 WO 2024135456A1 JP 2023044427 W JP2023044427 W JP 2023044427W WO 2024135456 A1 WO2024135456 A1 WO 2024135456A1
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WIPO (PCT)
Prior art keywords
groove
layer
conductor
insulating layer
electrolytic plating
Prior art date
Application number
PCT/JP2023/044427
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English (en)
French (fr)
Japanese (ja)
Inventor
宏和 仲井
範征 清水
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京セラ株式会社
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Priority to JP2024565833A priority Critical patent/JPWO2024135456A1/ja
Publication of WO2024135456A1 publication Critical patent/WO2024135456A1/ja

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • This disclosure relates to a wiring board and a method for manufacturing the same.
  • the semi-additive method has been used as a method for forming wiring conductors in wiring boards.
  • the semi-additive method is a method for forming wiring conductors in the following procedure. First, a thin base metal layer is formed on the exposed surface of the insulating layer by electroless plating, sputtering, or other methods. Next, a plating resist layer with openings corresponding to the pattern of the wiring conductor is formed on this base metal layer. Next, an electrolytic plating layer is formed on the base metal layer exposed in the openings of the plating resist layer. Next, the plating resist layer is peeled off and the base metal layer not covered by the electrolytic plating layer is etched away.
  • wiring conductors in wiring boards are becoming finer.
  • the width of the wiring conductor is 15 ⁇ m or less and the distance between adjacent wiring conductors is 15 ⁇ m or less.
  • the bonding area between the insulating layer and the wiring conductor via the underlying metal layer becomes small. This makes the wiring conductor more likely to peel off from the insulating layer. Furthermore, the reliability of electrical insulation between adjacent wiring conductors decreases.
  • a method has been proposed for forming a wiring conductor consisting of a metal base layer and an electrolytic plating layer that remain in the grooves, as described in Patent Document 1.
  • grooves corresponding to the pattern of the wiring conductor are formed to a predetermined depth on the surface of the insulating layer by laser processing.
  • a thin metal base layer is formed on the surface of the insulating layer, including the inner surface of the groove, by electroless plating or sputtering.
  • an electrolytic plating layer is formed on this metal base layer to a thickness that fills the grooves.
  • the metal base layer and electrolytic plating layer on the insulating layer are polished away by chemical mechanical polishing.
  • a relatively narrow (e.g., 15 ⁇ m or less) groove for a wiring conductor is filled well with an electrolytic plating layer.
  • a relatively wide (e.g., 150 ⁇ m or more) groove for a wiring conductor is difficult to fill well with an electrolytic plating layer.
  • the upper surface of the wiring conductor is greatly recessed and the flatness is poor. If the thickness of the electrolytic plating layer is further increased to eliminate this recess, the stress generated when forming this electrolytic plating layer increases. Therefore, the stress acts greatly between the inner wall of the groove for the wide wiring conductor via the base metal layer, making the wide wiring conductor more likely to peel off.
  • the wiring board according to the present disclosure includes a first insulating layer having a first upper surface, a second insulating layer located on the first upper surface and having a second upper surface, a first groove having a first inner surface recessed from the second upper surface toward the first insulating layer and a second groove having a second inner surface, a first wiring conductor located from the first groove to the first upper surface and including a wide pattern having a width of 150 ⁇ m or more, and a second wiring conductor located in the second groove and including a narrow pattern having a width of 15 ⁇ m or less.
  • the first wiring conductor includes a first base metal layer located on the first upper surface, a first electrolytic plating layer located on the first base metal layer and having a side surface that forms part of the first inner surface, a second base metal layer located on the first inner surface and connected to a side surface of the first electrolytic plating layer, and a second electrolytic plating layer located on the second base metal layer and filled in the first groove.
  • the second wiring conductor includes a third base metal layer located on the second inner surface, and a third electrolytic plating layer located on the third base metal layer and filling the second groove.
  • the method for manufacturing a wiring board according to the present disclosure includes the steps of forming a first insulating layer having a first upper surface, forming a wide pattern having a width of 150 ⁇ m or more on the first upper surface, the wide pattern including a first base metal layer and a first electrolytic plating layer located on the first base metal layer, forming a second insulating layer covering the first upper surface and the wide pattern and having a second upper surface, forming a first groove recessed from the second upper surface toward the first insulating layer and having a first inner surface in contact with a side surface of the wide pattern and a second groove having a second inner surface spaced from the wide pattern, forming a second base metal layer covering the first inner surface, a third base metal layer covering the second inner surface, and forming a second base metal layer and a third base metal layer.
  • the method includes forming a fourth undercoat metal layer covering the second upper surface, a second electrolytic plating layer located on the second undercoat metal layer and having a thickness that fills the first groove, a third electrolytic plating layer located on the third undercoat metal layer and having a thickness that fills the second groove, and a fourth electrolytic plating layer located on the fourth undercoat metal layer and continuous with the second electrolytic plating layer and the third electrolytic plating layer, and forming a first wiring conductor located from the first groove to the first surface and including a wide pattern, and a second wiring conductor located in the second groove and including a narrow pattern having a width of 15 ⁇ m or less by removing at least the fourth undercoat metal layer and the fourth electrolytic plating layer located on the second upper surface.
  • 1 is an explanatory diagram showing a cross section of a wiring board according to a first embodiment of the present disclosure
  • 5A to 5C are explanatory views for explaining a manufacturing process of the wiring board according to the first embodiment of the present disclosure.
  • 5A to 5C are explanatory views for explaining a manufacturing process of the wiring board according to the first embodiment of the present disclosure.
  • 5A to 5C are explanatory views for explaining a manufacturing process of the wiring board according to the first embodiment of the present disclosure.
  • 5A to 5C are explanatory views for explaining a manufacturing process of the wiring board according to the first embodiment of the present disclosure.
  • 5A to 5C are explanatory views for explaining a manufacturing process of the wiring board according to the first embodiment of the present disclosure.
  • FIG. 11 is an explanatory diagram showing a cross section of a wiring board according to a second embodiment of the present disclosure.
  • FIG. 11 is an explanatory diagram showing a cross section of a wiring board according to a third embodiment of the present disclosure.
  • FIG. 11 is an explanatory diagram showing a cross section of a wiring board according to a fourth embodiment of the present disclosure.
  • 10 is a perspective view showing a schematic view of only a conductor portion of the wiring board shown in FIG. 9 .
  • 13A to 13C are explanatory views for explaining a manufacturing process of a wiring board according to a fourth embodiment of the present disclosure.
  • 13A to 13C are explanatory views for explaining a manufacturing process of a wiring board according to a fourth embodiment of the present disclosure.
  • 13A to 13C are explanatory views for explaining a manufacturing process of a wiring board according to a fourth embodiment of the present disclosure.
  • 13A to 13C are explanatory views for explaining a manufacturing process of a wiring board according to a fourth embodiment of the present disclosure.
  • 13A to 13C are explanatory views for explaining a manufacturing process of a wiring board according to a fourth embodiment of the present disclosure.
  • grooves for wiring conductors with a relatively narrow width are well filled with the electrolytic plating layer.
  • grooves for wiring conductors with a relatively wide width are difficult to fill well with the electrolytic plating layer.
  • the upper surface of the wiring conductor is greatly recessed and the flatness is poor. If the thickness of the electrolytic plating layer is further increased to eliminate this recess, the stress generated when forming this electrolytic plating layer increases. Therefore, the stress acts greatly between the inner wall of the groove for the wide wiring conductor via the base metal layer, making the wide wiring conductor more likely to peel off. Therefore, there is a demand for a wiring board in which both narrow and wide wiring conductors are less likely to peel off and have high positional accuracy with respect to each other.
  • the wiring board according to the present disclosure has a configuration as described in the section on means for solving the above problems, so that both the narrow and wide wiring conductors are less likely to peel off, and the positional accuracy of each is also high.
  • FIG. 1 is a schematic diagram showing a portion of a cross section of a wiring board 100 according to a first embodiment of the present disclosure.
  • the wiring board 100 according to the first embodiment includes a core substrate 10, a build-up layer 20 located on the surface of the core substrate 10, and a solder resist layer 30 located on the surface of the build-up layer 20.
  • FIG. 1 shows only a portion of the top surface side of the wiring board 100.
  • the core substrate 10 includes a core insulating layer 11 and a core conductor 12.
  • the core insulating layer 11 is formed of a resin such as an epoxy resin, a bismaleimide-triazine resin, a polyimide resin, a polyphenylene ether resin, or a liquid crystal polymer. These resins may be used alone or in combination of two or more.
  • the core insulating layer 11 may contain a reinforcing material such as glass cloth, and may further contain dispersed insulating particles.
  • the insulating particles are not limited, and examples include inorganic insulating fillers such as silica, alumina, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide.
  • the core insulating layer 11 has a thickness of, for example, 0.1 mm or more and 2.0 mm or less.
  • the core conductor 12 includes a core conductor layer 12a and a through-hole conductor 12b.
  • the core conductor layer 12a is located on the top and bottom surfaces of the core insulating layer 11.
  • the core conductor layer 12a is formed of a conductor such as copper, for example, copper foil or copper plating.
  • the thickness of the core conductor layer 12a is not particularly limited, and is, for example, 5 ⁇ m or more and 50 ⁇ m or less.
  • the through-hole conductor 12b is located in a through-hole TH that penetrates the core insulating layer 11 from top to bottom.
  • the through-hole conductor 12b electrically connects the core conductor layers 12a located on the top and bottom surfaces of the core insulating layer 11.
  • the through-hole conductor 12b is formed of a conductor made of a metal plating such as copper plating.
  • the through-hole conductor 12b is integrally connected to the core conductor layers 12a on both sides of the core insulating layer 11.
  • the through-hole conductor 12b may be formed only on the inner wall surface of the through-hole TH, or may be filled inside the through-hole TH.
  • the build-up layer 20 includes a build-up insulating layer 21 and a build-up conductor layer 22.
  • the build-up insulating layer 21 includes a first insulating layer 21a having a first upper surface f1, and a second insulating layer 21b located on the first upper surface f1 of the first insulating layer 21a and having a second upper surface f2.
  • the first insulating layer 21a is formed of a resin such as an epoxy resin, a bismaleimide-triazine resin, a polyimide resin, a polyphenylene ether resin, or a liquid crystal polymer. These resins may be used alone or in combination of two or more.
  • the first insulating layer 21a may have insulating particles dispersed therein.
  • the insulating particles are not limited, and examples thereof include inorganic insulating fillers such as silica, alumina, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide.
  • the first insulating layer 21a has a thickness of, for example, 10 ⁇ m to 50 ⁇ m.
  • the second insulating layer 21b is located on the first upper surface f1 of the first insulating layer 21a.
  • the second insulating layer 21b may be made of the same resin as that forming the first insulating layer 21a, and may be used alone or in combination of two or more types. Furthermore, the second insulating layer 21b may also have insulating particles dispersed therein, similar to those in the first insulating layer 21a.
  • the thickness of the second insulating layer 21b is not limited, and may be thinner than the thickness of the first insulating layer 21a, for example.
  • the second insulating layer 21b has a thickness of, for example, 5 ⁇ m to 25 ⁇ m.
  • the core insulating layer 11, the first insulating layer 21a, and the second insulating layer 21b may be formed of the same resin or different resins. Furthermore, when insulating particles are dispersed in the core insulating layer 11, the first insulating layer 21a, and the second insulating layer 21b, the insulating particles may be the same or different.
  • the build-up conductor layer 22 includes a first base metal layer 22a, a first electrolytic plating layer 22b, a second base metal layer 22c, a second electrolytic plating layer 22d, a third base metal layer 22e, and a third electrolytic plating layer 22f.
  • the first base metal layer 22a is located on the first upper surface f1 of the first insulating layer 21a.
  • the first base metal layer 22a is formed of a metal such as copper.
  • the first base metal layer 22a has a thickness of, for example, 0.1 ⁇ m or more and 0.5 ⁇ m or less. As shown in FIG. 1, the first base metal layer 22a may be located on the inner surface of a via hole V1 that penetrates the first insulating layer 21a.
  • the first base metal layer 22a has the role of improving the adhesion of the first electrolytic plating layer 22b.
  • the first electrolytic plating layer 22b is located on the first base metal layer 22a.
  • the first electrolytic plating layer 22b is not limited to any particular layer formed by electrolytic plating, and may be formed of a metal such as copper.
  • the first electrolytic plating layer 22b has a thickness of, for example, 5 ⁇ m or more and 25 ⁇ m or less.
  • the second base metal layer 22c is located on the first inner surface n1 of the first groove G1, which is recessed from the second upper surface f2 of the second insulating layer 21b toward the first insulating layer 21a.
  • the first groove G1 is in contact with the side surface of the first electrolytic plating layer 22b.
  • the side surface of the first electrolytic plating layer 22b forms part of the first inner surface n1 of the first groove G1.
  • the second base metal layer 22c is formed of a metal such as copper.
  • the second base metal layer 22c has a thickness of, for example, 0.1 ⁇ m or more and 0.5 ⁇ m or less.
  • the second base metal layer 22c has the role of improving the adhesion of the second electrolytic plating layer 22d.
  • the second electrolytic plating layer 22d is filled into the first groove G1 in which the second base metal layer 22c is formed.
  • the second electrolytic plating layer 22d is not limited to any particular layer formed by electrolytic plating, and may be formed of a metal such as copper.
  • the second electrolytic plating layer 22d is located in the first groove G1 via the second base metal layer 22c on both the side and bottom surfaces. This provides excellent adhesion, reducing peeling of the second electrolytic plating layer 22d.
  • the third base metal layer 22e is located on the second inner surface n2 of the second groove G2 recessed from the second upper surface f2 of the second insulating layer 21b toward the first insulating layer 21a.
  • the third base metal layer 22e is formed of a metal such as copper.
  • the third base metal layer 22e has a thickness of, for example, 0.1 ⁇ m or more and 0.5 ⁇ m or less.
  • the third base metal layer 22e may be located on the inner surface of a via hole V2 penetrating the first insulating layer 21a, as shown in FIG. 1.
  • the third base metal layer 22e has the role of improving the adhesion of the third electrolytic plating layer 22f.
  • the third electrolytic plating layer 22f is filled into the second groove G2 in which the third base metal layer 22e is formed.
  • the third electrolytic plating layer 22f is not limited to any particular layer formed by electrolytic plating, and may be formed of a metal such as copper.
  • the third electrolytic plating layer 22f is located in the second groove G2 via the third base metal layer 22e on both the side and bottom surfaces. This provides excellent adhesion, and reduces peeling of the third electrolytic plating layer 22f.
  • the build-up conductor layer 22 includes a first wiring conductor 23 and a second wiring conductor 24 that have different widths.
  • the first wiring conductor 23 includes a wide pattern WP with a width W1 of 150 ⁇ m or more. On the other hand, the first wiring conductor 23 does not include a pattern with a width of 15 ⁇ m or less.
  • the first wiring conductor 23 is composed of a first base metal layer 22a and a first electrolytic plating layer 22b on the first insulating layer 21a, and a second base metal layer 22c and a second electrolytic plating layer 22d in the first groove G1.
  • the first wiring conductor 23 mainly functions as a ground and a power source.
  • the width W1 can be defined as the length between the opposing sides of the first wiring conductor 23, for example.
  • the first wiring conductor 23 has the second base metal layer 22c and the second electrolytic plating layer 22d of the first groove G1 positioned between the side of the first electrolytic plating layer 22b and the second insulating layer 21b. That is, the side of the first electrolytic plating layer 22b constituting the first wiring conductor 23 is not in contact with the second insulating layer 21b. Therefore, since the side of the first electrolytic plating layer 22b is not in contact with the second insulating layer 21b, stress directly transmitted to the second insulating layer 21b between the side of the first electrolytic plating layer 22b and the second insulating layer 21b can be eliminated. As a result, peeling of the first electrolytic plating layer 22b can be reduced.
  • the arithmetic mean roughness Ra of the side surface of the first electrolytic plating layer 22b is not limited and may be, for example, 150 nm or more and 300 nm or less. If the arithmetic mean roughness Ra of the side surface of the first electrolytic plating layer 22b is 150 nm or more and 300 nm or less, the side surface of the first electrolytic plating layer 22b is firmly adhered to the second base metal layer 22c of the first inner surface n1 of the first groove G1, and peeling of the first electrolytic plating layer 22b can be further reduced.
  • the second undercoat metal layer 22c and the second electrolytic plating layer 22d of the first groove G1 have the function of preventing the first electrolytic plating layer 22b from peeling off and increasing the positional accuracy between the first wiring conductor 23 and the second wiring conductor 24.
  • the width of the first groove G1 is not limited and may be, for example, 5 ⁇ m or more and 100 ⁇ m or less.
  • the depth of the first groove G1 is not limited and may be, for example, 5 ⁇ m or more and 75 ⁇ m or less.
  • the width of the first groove G1 can be defined, for example, as the length between the opening edges of the first groove G1 that face each other in the second insulating layer 21b.
  • the depth of the first groove G1 can be defined, for example, as the length from a position at the same height as the second upper surface f2 at the opening of the first groove G1 to a position of the first groove G1 closest to the core substrate 10.
  • the arithmetic mean roughness Ra of the first inner surface n1 of the first groove G1 other than the side surface of the first electrolytic plating layer 22b is not limited and may be, for example, 50 nm or more and 100 nm or less. If the arithmetic mean roughness Ra of the first inner surface n1 of the first groove G1 other than the side surface of the first electrolytic plating layer 22b is 50 nm or more and 100 nm or less, the second base metal layer 22c is firmly adhered to the first inner surface n1 in the first groove G1, and peeling of the second base metal layer 22c can be further reduced.
  • the second wiring conductor 24 is composed of the third undercoat metal layer 22e and the third electrolytic plating layer 22f of the second groove G2.
  • the second wiring conductor 24 includes a narrow pattern NP having a width W2 of 15 ⁇ m or less.
  • the second wiring conductor 24 does not include a pattern having a width of 150 ⁇ m or more.
  • the depth of the second groove G2 is not limited and may be, for example, 5 ⁇ m or more and 25 ⁇ m or less.
  • the second wiring conductor 24 mainly has a function for signal transmission. In FIG. 1, the second wiring conductor 24 appears wide. However, the second wiring conductor 24 appears wide and shows a cross section cut in the longitudinal direction.
  • the width W2 can be defined, for example, as the shortest length between the opposing sides of the second wiring conductor 24.
  • the depth of the second groove G2 can be defined, for example, as the length from a position at the same height as the second upper surface f2 at the opening of the second groove G2 to a position of the second groove G2 closest to the core substrate 10.
  • the arithmetic mean roughness Ra of the second inner surface n2 of the second groove G2 is not limited and may be, for example, 50 nm or more and 100 nm or less. If the arithmetic mean roughness Ra of the second inner surface n2 of the second groove G2 is 50 nm or more and 100 nm or less, the third base metal layer 22e is firmly attached to the second inner surface n2 of the second groove G2, and peeling of the third base metal layer 22e can be further reduced.
  • the second wiring conductor 24 has a surface roughness with an arithmetic mean roughness Ra of 50 nm or more and 100 nm or less, corresponding to the roughness of the second inner surface n2 of the second groove G2. This roughness is small, and is advantageous in that it makes it possible to reduce transmission loss when a high-frequency signal is transmitted to the second wiring conductor 24.
  • the solder resist layer 30 is located on the build-up layer 20.
  • the solder resist layer 30 is formed, for example, from an acrylic modified epoxy resin.
  • the solder resist layer 30 has a function of protecting the conductor layer and the like from solder, for example, when mounting electronic components or connecting to a motherboard.
  • the solder resist layer 30 has an opening formed therein for exposing a part of the first wiring conductor 23 or the second wiring conductor 24 located on the surface of the build-up layer 20. The part of the first wiring conductor 23 or the second wiring conductor 24 exposed from this opening functions as a pad, for example, when mounting a semiconductor element or the like.
  • the method for manufacturing the wiring board according to the present disclosure includes the following steps (a) to (f). (a) forming a first insulating layer having a first top surface; (b) forming a wide pattern on the first upper surface, the wide pattern having a width W1 of 150 ⁇ m or more and including a first base metal layer and a first electrolytic plating layer located on the first base metal layer; (c) forming a second insulating layer covering the first top surface and the wide pattern and having a second top surface; (d) forming a first groove recessed from the second upper surface toward the first insulating layer and having a first inner surface in contact with a side surface of the wide pattern, and a second groove having a second inner surface spaced apart from the wide pattern.
  • Figures 2 to 6 are explanatory diagrams for explaining the manufacturing process of the wiring board 100 according to the first embodiment.
  • the core substrate 10 includes a core insulating layer 11 and a core conductor 12.
  • the core insulating layer 11 and the core conductor 12 are as described above, and detailed description thereof will be omitted.
  • the first insulating layer 21a is formed so as to cover the core insulating layer 11 and the core conductor 12 of the core substrate 10 as shown in FIG. 2B.
  • the first insulating layer 21a is as described above, and detailed description will be omitted.
  • the first insulating layer 21a is formed, for example, by laminating a thermosetting resin sheet for the first insulating layer 21a on the core substrate 10 and applying pressure and heat from above and below to thermally harden it.
  • a via hole V1 is formed as necessary as shown in FIG. 2C.
  • the via hole V1 is formed, for example, by laser processing such as a CO2 laser, a UV-YAG laser, and an excimer laser.
  • a first base metal layer 22a such as copper is deposited by electroless plating on the upper surface of the first insulating layer 21a and the inner surface of the via hole V1. Palladium may be used as a catalyst when performing electroless plating.
  • the deposited first base metal layer 22a has a thickness of, for example, 0.1 ⁇ m or more and 0.5 ⁇ m or less.
  • first base metal layer 22a such as copper by electroless plating
  • the portions where the first electrolytic plating layer 22b is not to be formed are covered with resist R as shown in FIG. 3(A).
  • the first electrolytic plating layer 22b such as copper is deposited by electrolytic plating as shown in FIG. 3(B).
  • the first electrolytic plating layer 22b has a thickness of, for example, 5 ⁇ m to 25 ⁇ m. By setting the width of the portion where the first electrolytic plating layer 22b is to be deposited to 150 ⁇ m or more, a wide pattern can be formed.
  • the resist R is removed as shown in FIG. 3(C), and the first base metal layer 22a in the portion that was covered with resist R is removed as shown in FIG. 3(D).
  • a wide pattern WP having a width W1 of 150 ⁇ m or more is formed on the first insulating layer 21a, the wide pattern WP being composed of the first base metal layer 22a and the first electrolytic plating layer 22b located on the first base metal layer 22a.
  • the side surface of the first electrolytic plating layer 22b may be roughened to have an arithmetic mean roughness Ra of 150 nm or more and 300 nm or less.
  • the step (step (c)) of forming a second insulating layer that covers the upper surface of the first insulating layer and the wide pattern will be described.
  • the second insulating layer 21b is formed so as to cover the first upper surface f1 and the wide pattern WP of the first insulating layer 21a.
  • the second insulating layer 21b is formed, for example, by laminating a thermosetting resin sheet for the second insulating layer 21b on the first upper surface f1 and the wide pattern WP of the first insulating layer 21a and applying pressure and heat from above and below to thermally harden it.
  • step (d)) of forming a first groove recessed from the upper surface of the second insulating layer toward the first insulating layer and having a first inner surface in contact with the side surface of the wide pattern and a second groove having a second inner surface spaced from the wide pattern will be described.
  • a first groove G1 having a first inner surface n1 is formed at a position in contact with the side surface of the wide pattern WP
  • a second groove G2 having a second inner surface n2 spaced from the side surface of the wide pattern WP is formed at a position where the second wiring conductor 24 is formed.
  • the method of forming the first groove G1 and the second groove G2 is not limited, and they are formed by laser processing such as an excimer laser, a CO 2 laser, and a UV-YAG laser. It is preferable to adopt an excimer laser in that the first groove G1 and the second groove G2 are easily formed with a uniform depth.
  • the depth of the first groove G1 and the second groove G2 is not limited, and may be, for example, 5 ⁇ m or more and 25 ⁇ m or less. 4C, a via hole V2 may be formed in the first insulating layer 21a as required.
  • the via hole V2 may be formed by laser processing using an excimer laser, a CO2 laser, a UV-YAG laser, or the like.
  • the groove formation process may be performed so that the first inner surface n1 of the first groove G1 and the second inner surface n2 of the second groove G2, excluding the side surface of the wide pattern WP, have an arithmetic mean roughness Ra of 50 nm or more and 100 nm or less. In this case, too, using an excimer laser makes it easy to form the inner surface to a specified roughness.
  • the second base metal layer 22c and the third base metal layer 22e are firmly attached to the first insulating layer 21a and the second insulating layer 21b, and peeling of the second base metal layer 22c and the third base metal layer 22e can be further reduced.
  • step (e) of forming a second base metal layer covering the first inner surface, a third base metal layer covering the second inner surface, a fourth base metal layer continuous with the second and third base metal layers and covering the second upper surface, a second electrolytic plating layer located on the second base metal layer and having a thickness to fill the first groove, a third electrolytic plating layer located on the third base metal layer and having a thickness to fill the second groove, and a fourth electrolytic plating layer located on the fourth base metal layer continuous with the second and third electrolytic plating layers will be described.
  • a second base metal layer 22c covering the first inner surface n1, a third base metal layer 22e covering the second inner surface n2, and a fourth base metal layer 22g covering the second upper surface f2 are formed continuously with the second base metal layer 22c and the third base metal layer 22e.
  • the second base metal layer 22c, the third base metal layer 22e, and the fourth base metal layer 22g are formed simultaneously, for example, by precipitating a metal such as copper by electroless plating.
  • the second base metal layer 22c, the third base metal layer 22e, and the fourth base metal layer 22g are metal layers formed by the same electroless plating process. Palladium may be used as a catalyst when performing electroless plating.
  • the second base metal layer 22c, the third base metal layer 22e, and the fourth base metal layer 22g have a thickness of, for example, 0.1 ⁇ m or more and 0.5 ⁇ m or less, and are also formed on the inner surface of the via hole V2.
  • a second electrolytic plating layer 22d is formed on the second base metal layer 22c, with a thickness that fills the first groove G1
  • a third electrolytic plating layer 22f is formed on the third base metal layer 22e, with a thickness that fills the second groove G2
  • a fourth electrolytic plating layer 22h is formed on the fourth base metal layer 22g, continuous with the second electrolytic plating layer 22d and the third electrolytic plating layer 22f.
  • the second electrolytic plating layer 22d, the third electrolytic plating layer 22f, and the fourth electrolytic plating layer 22h are formed simultaneously with a metal such as copper.
  • the second electrolytic plating layer 22d, the third electrolytic plating layer 22f, and the fourth electrolytic plating layer 22h are plating layers formed by the same electrolytic plating process.
  • step (f) a process (step (f)) in which at least the fourth base metal layer and the fourth electrolytic plating layer located on the second insulating layer are removed to form a first wiring conductor located from the first groove to the first upper surface f1 and including a wide pattern, and a second wiring conductor located in the second groove and including a narrow pattern having a width of 15 ⁇ m or less.
  • At least the fourth undercoat metal layer 22g and the fourth electrolytic plating layer 22h located on the second insulating layer 21b are removed.
  • a part of the second insulating layer 21b may also be removed as necessary.
  • a part of the second insulating layer 21b may be removed until the width of the second groove G2 is 15 ⁇ m or less, including the fourth undercoat metal layer 22g and the fourth electrolytic plating layer 22h located on the second insulating layer 21b.
  • a first wiring conductor 23 including the wide pattern WP and the second undercoat metal layer 22c and the second electrolytic plating layer 22d remaining in the first groove G1 is formed, and a second wiring conductor 24 including a narrow pattern NP having a width of 15 ⁇ m or less including the third undercoat metal layer 22e and the third electrolytic plating layer 22f remaining in the second groove G2 is formed.
  • the first groove G1 that contacts the side surface of the wide pattern WP constituting the first wiring conductor 23 and the second groove G2 that is spaced apart from the wide pattern WP are formed in the same process (step (d)).
  • the second electrolytic plating layer 22d having a thickness that fills the first groove G1 and the third electrolytic plating layer 22f having a thickness that fills the second groove G2 are formed in (step (e))
  • at least the fourth base metal layer 22g and the fourth electrolytic plating layer 22h located on the second insulating layer 21b are removed in a process (step (f)).
  • the first wiring conductor 23 is formed, which is located from the first groove G1 to the first upper surface f1 and includes the wide pattern WP
  • the second wiring conductor 24 is formed, which is located in the second groove G2 and includes the narrow pattern NP having a width W2 of 15 ⁇ m or less.
  • the build-up layer 20 includes the first insulating layer 21a, the second insulating layer 21b located on the first upper surface f1 of the first insulating layer 21a, the first groove G1 and the second groove G2 recessed from the second upper surface f2 of the second insulating layer 21b toward the first insulating layer 21a, the first wiring conductor 23 located from the first groove G1 to the first upper surface f1 of the first insulating layer 21a and including a wide pattern WP having a width W1 of 150 ⁇ m or more, and the second wiring conductor 24 located in the second groove G2 and including a narrow pattern NP having a width W2 of 15 ⁇ m or less.
  • the wiring board 100 shown in FIG. 1 is obtained by forming the solder resist layer 30 so that it is located on the surface of the build-up layer 20.
  • the solder resist layer 30 is formed by covering the surface of the build-up layer with a film such as an acrylic modified epoxy resin and curing it.
  • the solder resist layer 30 is as described above, so a detailed description will be omitted.
  • FIG. 7 is an explanatory diagram showing a cross section of a wiring board 200 according to a second embodiment of the present disclosure.
  • the same components as those in the wiring board 100 according to the first embodiment are given the same reference numerals, and detailed descriptions will be omitted.
  • the bottom surface of the second wiring conductor 24 (the bottom surface of the third base metal layer 22e) is in contact with the first insulating layer 21a.
  • the bottom surface of the second wiring conductor 24 (the bottom surface of the third base metal layer 22e) is not in contact with the first insulating layer 21a. That is, the second wiring conductor 24 (the third base metal layer 22e and the third electrolytic plating layer 22f) is contained within the second insulating layer 21b.
  • the depth of the second groove G2 is smaller than the thickness of the second insulating layer 21b. In this way, the wiring board 200 according to the second embodiment differs from the wiring board 100 according to the first embodiment in the arrangement of the second wiring conductor 24.
  • the second undercoat metal layer 22c When palladium is used as a catalyst in forming the first undercoat metal layer 22a, the second undercoat metal layer 22c, the third undercoat metal layer 22e, and the fourth undercoat metal layer 22g by electroless plating, palladium may remain. If palladium remains, migration is likely to occur near the boundary between the first insulating layer 21a and the second insulating layer 21b between the adjacent second wiring conductors 24 (third undercoat metal layer 22e) or between the second wiring conductor 24 and the first wiring conductor 23. As in the wiring board 200 according to the second embodiment, if the second wiring conductor 24 is contained within the second insulating layer 21b, the third undercoat metal layer 22e will be separated from the boundary between the first insulating layer 21a and the second insulating layer 21b. As a result, migration near the boundary can be reduced, and insulation reliability is further improved.
  • the depth of the second groove G2 may be adjusted so that the bottom surface of the second groove G2 fits within the second insulating layer 21b.
  • the depth of the second groove G2 is formed to be smaller than the thickness of the second insulating layer 21b.
  • the depth of the second groove G2 is set appropriately according to the thickness of the second insulating layer 21b.
  • FIG. 8 is an explanatory diagram showing a cross section of a wiring board 300 according to a third embodiment of the present disclosure.
  • the same components as those in the wiring board 100 according to the first embodiment are given the same reference numerals, and detailed descriptions will be omitted.
  • the upper surface of the first wiring conductor 23 (the upper surface of the first electrolytic plating layer 22b) is not covered with the second insulating layer 21b.
  • the wiring board 300 according to the third embodiment at least a portion of the upper surface of the first wiring conductor 23 (the upper surface of the first electrolytic plating layer 22b) is not exposed from the second insulating layer 21b and is covered with the second insulating layer 21b. In this way, the wiring board 300 according to the third embodiment differs from the wiring board 100 according to the first embodiment in the arrangement of the first wiring conductor 23.
  • a small gap may exist near the boundary between the second insulating layer 21b and the insulating layer located above it, and migration may occur if adjacent wiring conductors are exposed at the boundary. In other words, migration is likely to occur near the boundary between the first wiring conductor 23 (first electrolytic plating layer 22b) and the second insulating layer 21b.
  • the wiring board 300 according to the third embodiment when at least a portion of the upper surface of the first wiring conductor 23 is covered with the second insulating layer 21b, the upper surface of the first electrolytic plating layer 22b is separated from the boundary between the upper surface of the second insulating layer 21b and the insulating layer located above it. As a result, migration can be reduced between the upper surface of the first electrolytic plating layer 22b and the upper surface of the second insulating layer 21b, and insulation reliability is further improved.
  • step (f) in the step of forming the second wiring conductor (step (f)) described above, at least the fourth base metal layer 22g and the fourth electrolytic plating layer 22h located on the second insulating layer 21b may be removed so that at least a portion of the upper surface of the first wiring conductor 23 is not exposed. If necessary, the vicinity of the upper surface of the second insulating layer 21b may be removed.
  • Figure 9 is an explanatory diagram showing a cross section of a wiring board 400 according to a fourth embodiment of the present disclosure.
  • Figure 10 is a perspective view showing a schematic view of only the conductor portion of the wiring board shown in Figure 9.
  • the same components as those in the wiring board 100 according to the first embodiment are given the same reference numerals, and detailed descriptions will be omitted.
  • the bottom surface of the first wiring conductor 23 (the bottom surface of the second base metal layer 22c) located in the first groove G1 is located near the first upper surface f1 of the first insulating layer 21a.
  • the bottom surface of the first wiring conductor 23 (the bottom surface of the second base metal layer 22c) located in the first groove G1 is in contact with the lower conductor (corresponding to the core conductor layer 12a in the wiring board 400 shown in FIG. 9). In this way, the wiring board 400 according to the fourth embodiment differs from the wiring board 100 according to the first embodiment in the arrangement of the first wiring conductor 23.
  • the bottom surface of the first wiring conductor 23 located in the first groove G1 is in contact with the underlying conductor, improving the shielding of the second wiring conductor 24, which functions as a signal wiring conductor.
  • the second wiring conductor 24 is shielded by the first wiring conductor 23, which is located so as to sandwich the second wiring conductor 24.
  • the above-mentioned manufacturing method may further include a step (step (g)) of forming a lower conductor layer on the surface opposite the first surface of the first insulating layer 21a.
  • the lower conductor layer corresponds to the core conductor layer 12a.
  • the first groove G1 is formed to a depth that reaches the lower conductor layer.
  • a conductor that will become the first wiring conductor 23 may be formed in this first groove G1.
  • the wiring board 400 according to the fourth embodiment may further include a third insulating layer 21c, a fourth insulating layer 21d, a third groove G3, and a third wiring conductor 25, as shown in FIG. 9.
  • the third insulating layer 21c is located on the second upper surface f2 of the second insulating layer 21b and has a third upper surface f3.
  • the fourth insulating layer 21d is located on the third upper surface f3 of the third insulating layer 21c and has a fourth upper surface f4.
  • the third groove G3 has a third inner surface recessed from the fourth upper surface f4 of the fourth insulating layer 21d toward the third insulating layer 21c.
  • the third wiring conductor 25 is located from the third groove G3 to the third upper surface and includes a second wide pattern WP2 having a width of 150 ⁇ m or more.
  • the third insulating layer 21c and the fourth insulating layer 21d may be made of the same resin as that forming the first insulating layer 21a.
  • the resin may be used alone or in combination of two or more types.
  • the third insulating layer 21c and the fourth insulating layer 21d may also have insulating particles dispersed therein similar to those of the first insulating layer 21a.
  • the thicknesses of the third insulating layer 21c and the fourth insulating layer 21d are not limited.
  • the thickness of the fourth insulating layer 21d may be thinner than the thickness of the third insulating layer 21c.
  • the third insulating layer 21c has a thickness of, for example, 10 ⁇ m or more and 50 ⁇ m or less.
  • the fourth insulating layer 21d has a thickness of, for example, 5 ⁇ m or more and 25 ⁇ m or less.
  • the third wiring conductor 25 has a base metal layer and an electrolytic plating layer, similar to the first wiring conductor 23 described above.
  • the first insulating layer 21a corresponds to the third insulating layer 21c
  • the first upper surface f1 corresponds to the third upper surface
  • the first groove G1 corresponds to the third groove G3
  • the first inner surface n1 corresponds to the third inner surface.
  • the third wiring conductor 25 located in the third groove G3 is in contact with the first wiring conductor 23.
  • a portion of the second wiring conductor 24 is surrounded by the lower layer conductor (corresponding to the core conductor layer 12a in the wiring board 400 shown in FIG. 9), the first wiring conductor 23, and the third wiring conductor 25.
  • a coaxial wiring structure is formed in the build-up layer 20.
  • the shielding properties of the second wiring conductor 24, which functions as a wiring conductor for signals, are further improved by forming such a coaxial wiring structure.
  • the manufacturing method may further include the following steps (h) to (l) in addition to the above-mentioned manufacturing method (steps (a) to (f)).
  • steps (h) A step of forming a third insulating layer 21c having a third upper surface on the second upper surface f2.
  • steps (i) to (i) A step of forming a second wide pattern WP2 having a width of 150 ⁇ m or more on the third upper surface.
  • the method for forming the third insulating layer 21c, the fourth insulating layer 21d, the second wide pattern WP2, the third groove G3 and the third wiring conductor 25 may be performed in accordance with the method (steps) for forming the first insulating layer 21a, the second insulating layer 21b, the wide pattern WP, the first groove G1 and the first wiring conductor 23 described above.
  • the wiring board 400 according to the fourth embodiment may further include a fifth insulating layer 21e having a plurality of electrodes 26 on the first upper surface f1 side.
  • the fifth insulating layer 21e may also be made of the same resin as that forming the first insulating layer 21a. The resin may be used alone or in combination of two or more types. Furthermore, the fifth insulating layer 21e may also have insulating particles dispersed therein similar to those in the first insulating layer 21a.
  • the thickness of the fifth insulating layer 21e is not limited. For example, the fifth insulating layer 21e has a thickness of 5 ⁇ m or more and 25 ⁇ m or less.
  • the lower layer conductor (corresponding to the core conductor layer 12a) may further include a cylindrical first through-hole conductor 121b and a second through-hole conductor 122b located inside the first through-hole conductor 121b in a plan view and spaced apart from the first through-hole conductor 121b.
  • the first through-hole conductor 121b and the second through-hole conductor 122b are located in the through-hole TH that penetrates the core insulating layer 11 from top to bottom, similar to the above-mentioned through-hole conductor 12b.
  • the first through-hole conductor 121b and the second through-hole conductor 122b electrically connect the core conductor layer 12a and the build-up conductor layer 22 located on the top and bottom surfaces of the core insulating layer 11.
  • the first through-hole conductor 121b and the second through-hole conductor 122b are also formed of a conductor made of a metal plating such as copper plating, similar to the above-mentioned through-hole conductor 12b.
  • the first through-hole conductor 121b has a cylindrical shape and is formed on the inner wall surface of the through-hole TH.
  • the second through-hole conductor 122b is located inside the first through-hole conductor 121b so as to be surrounded by the first through-hole conductor 121b.
  • the second through-hole conductor 122b has a columnar shape, for example, a cylindrical shape.
  • first through-hole conductor 121b and the second through-hole conductor 122b have such a structure, for example, when the first through-hole conductor 121b is a ground conductor and the second through-hole conductor 122b is a signal conductor, it becomes possible to shield the second through-hole conductor 122b by the first through-hole conductor 121b, improving the signal transmission characteristics.
  • the space between the first through-hole conductor 121b and the second through-hole conductor 122b is filled with a filling resin 11a.
  • a filling resin 11a There is no limitation to the filling resin 11a, and examples of the filling resin include epoxy resin, bismaleimide-triazine resin, polyimide resin, polyphenylene ether resin, and liquid crystal polymer.
  • the first through-hole conductor 121b is electrically connected to the first wiring conductor 23 and the third wiring conductor 25. At least one of the multiple electrodes 26 and the second through-hole conductor 122b are electrically connected via the second wiring conductor 24.
  • the electrode 26 is a part of the build-up conductor layer 22 exposed from an opening in the solder resist layer 30. At least two of the multiple electrodes 26 may be electrically connected via the second wiring conductor 24.
  • Figures 11 to 15 are explanatory diagrams for explaining the manufacturing process of a wiring board according to the fourth embodiment of the present disclosure.
  • a core substrate 10 is prepared.
  • a laminate of a core insulating layer 11 and a core conductor 12 is prepared.
  • a through hole TH is formed.
  • the through hole TH is formed by a general method using drilling, laser processing, or the like.
  • electroless copper plating is deposited on the surface of the core conductor 12 and the inner wall surface of the through hole TH, and then, as shown in FIG. 11(D), electrolytic copper plating is deposited. The electrolytic copper plating is deposited so as not to fill the through hole TH.
  • the through hole TH is filled with a filling resin 11a, and as shown in FIG. 11(F), the filling resin 11a protruding from the through hole TH is removed.
  • the filling resin 11a is removed, for example, by polishing.
  • the electroless copper plating and electrolytic copper plating formed on areas other than the inner wall surface of the through hole TH may be removed or may remain. In this way, a first through hole conductor 121b is formed on the inner wall surface of the through hole TH.
  • a second through-hole TH2 is formed in the center of the filled resin 11a so that the top and bottom surfaces in the thickness direction are penetrated.
  • electroless copper plating is deposited on the surface of the core conductor 12 and the inner wall surface of the second through-hole TH2, and then electrolytic copper plating is deposited as shown in FIG. 12(C).
  • the electrolytic copper plating is deposited so as to fill the second through-hole TH2.
  • the electroless copper plating and electrolytic copper plating located on the surface of the core conductor 12 are removed, for example, by polishing. In this way, a second through-hole conductor 122b is formed in the second through-hole TH2, and the core substrate 10 is formed.
  • a first insulating layer 21a is formed on the surface of the core substrate 10, and as shown in FIG. 12(F), a via hole V1 is formed in a desired position through the first insulating layer 21a.
  • the via hole V1 is formed by laser processing as described above.
  • electroless copper plating is deposited on the surface of the first insulating layer 21a and the inner wall surface of the via hole V1. This electroless copper plating corresponds to the first base metal layer 22a.
  • FIG. 13(B) the portions on which electrolytic copper plating (corresponding to the first electrolytic plating layer 22b) is not to be formed are covered with resist R, and as shown in FIG. 13(C), electrolytic copper plating is deposited to form the first electrolytic plating layer 22b.
  • resist R is removed.
  • the resist R is removed and the electroless copper plating (first base metal layer 22a) in the portion that was covered by the resist R is removed.
  • the first base metal layer 22a is removed by, for example, etching.
  • a second insulating layer 21b is formed so as to cover the surface of the first insulating layer 21a and the first electrolytic plating layer 22b.
  • the first groove G1 and the second groove G2 are formed.
  • the first groove G1 is formed so as to penetrate to the lower conductor (core conductor layer 12a) located on the opposite side of the first upper surface f1 of the first insulating layer 21a.
  • the second groove G2 is formed so that its bottom surface is located near the first upper surface f1 of the first insulating layer 21a. From the viewpoint of insulation reliability, it is preferable that the bottom surface of the second groove G2 is separated from the lower conductor by, for example, 10 ⁇ m or more.
  • the first groove G1 and the second groove G2 are formed by laser processing as described above.
  • the first groove G1 and the second groove G2 are formed, for example, by changing the number of laser shots.
  • electroless copper plating is deposited on the surface of the second insulating layer 21b, the inner wall surface of the first groove G1, and the inner wall surface of the second groove G2.
  • This electroless copper plating corresponds to the second base metal layer 22c and the third base metal layer 22e. That is, the electroless copper plating located on the inner wall surface of the first groove G1 corresponds to the second base metal layer 22c, and the electroless copper plating located on the inner wall surface of the second groove G2 corresponds to the third base metal layer 22e.
  • electrolytic copper plating is deposited so as to fill the first groove G1 and the second groove G2.
  • the electrolytic copper plating located in the first groove G1 corresponds to the second electrolytic plating layer 22d
  • the electrolytic copper plating located in the second groove G2 corresponds to the third electrolytic plating layer 22f.
  • excess electrolytic copper plating and electroless plating protruding from the first groove G1 and the second groove G2 are removed.
  • the electrolytic copper plating and electroless plating may be removed by, for example, polishing. In this way, the first wiring conductor 23 is formed in the first groove G1, and the second wiring conductor 24 is formed in the second groove G2.
  • a wiring board 400 according to the fourth embodiment is obtained, as shown in FIG. 15(C).
  • the build-up layer 20 is located on the upper surface side of the core substrate 10.
  • the build-up layer 20 may be located on the lower surface side of the core substrate 10.
  • the upper surfaces such as the "first upper surface f1" and the "second upper surface f2" correspond to the lower surface.
  • the upper surface side and the lower surface side of the core substrate 10 are reversed, so the upper surfaces are described as the “first upper surface f1" and the “second upper surface f2". That is, in this specification, the surface of each layer of the build-up layer 20 that is farther from the core substrate 10 is referred to as the "upper surface”.
  • the wiring board according to the present disclosure includes a first insulating layer having a first upper surface, a second insulating layer located on the first upper surface and having a second upper surface, a first groove having a first inner surface recessed from the second upper surface toward the first insulating layer, and a second groove having a second inner surface, a first wiring conductor located from the first groove to the first upper surface and including a wide pattern having a width of 150 ⁇ m or more, and a second wiring conductor located in the second groove and including a narrow pattern having a width of 15 ⁇ m or less.
  • the first wiring conductor includes a first base metal layer located on the first upper surface, a first electrolytic plating layer located on the first base metal layer and having a side surface that forms part of the first inner surface, a second base metal layer located on the first inner surface and connected to a side surface of the first electrolytic plating layer, and a second electrolytic plating layer located on the second base metal layer and filled in the first groove.
  • the second wiring conductor includes a third base metal layer located on the second inner surface, and a third electrolytic plating layer located on the third base metal layer and filling the second groove.
  • the side surface of the first electrolytic plating layer has an arithmetic mean roughness Ra of 150 nm or more and 300 nm or less.
  • the first inner surface and the second inner surface has an arithmetic mean roughness Ra of 50 nm or more and 100 nm or less.
  • the depth of the second groove is smaller than the thickness of the second insulating layer.
  • at least a portion of the surface of the first electrolytically plated layer is covered with a second insulating layer.
  • the first wiring conductor located in the first groove is in contact with the lower-layer conductor.
  • the wiring board according to (6) further includes a third insulating layer located on the second upper surface and having a third upper surface, a fourth insulating layer located on the third upper surface and having a fourth upper surface, a third groove having a third inner surface recessed from the fourth upper surface toward the third insulating layer, and a third wiring conductor located from the third groove to the third upper surface and including a second wide pattern having a width of 150 ⁇ m or more.
  • the third wiring conductor located in the third groove is in contact with the first wiring conductor.
  • a portion of the second wiring conductor is surrounded by the lower layer conductor, the first wiring conductor, and the third wiring conductor.
  • the wiring board according to (7) further includes a fifth insulating layer having a plurality of electrodes on the first upper surface side.
  • the lower layer conductor further includes a cylindrical first through-hole conductor and a second through-hole conductor located inside the first through-hole conductor and spaced apart from the first through-hole conductor in a plan view.
  • the first through-hole conductor is electrically connected to the first wiring conductor and the third wiring conductor.
  • At least one of the plurality of electrodes is electrically connected to the second through-hole conductor via the second wiring conductor.
  • at least two of the plurality of electrodes are electrically connected via the second wiring conductor.
  • a method for manufacturing a wiring board includes the steps of forming a first insulating layer having a first upper surface, forming a wide pattern on the first upper surface, the wide pattern including a first base metal layer and a first electrolytic plating layer located on the first base metal layer, the wide pattern having a width of 150 ⁇ m or more, forming a second insulating layer covering the first upper surface and the wide pattern and having a second upper surface, forming a first groove recessed from the second upper surface toward the first insulating layer and having a first inner surface in contact with a side surface of the wide pattern and a second groove having a second inner surface spaced from the wide pattern, forming a second base metal layer covering the first inner surface, a third base metal layer covering the second inner surface, and forming a second base metal layer and a third base metal layer.
  • the method includes forming a fourth undercoat metal layer covering the second upper surface, a second electrolytic plating layer located on the second undercoat metal layer and having a thickness to fill the first groove, a third electrolytic plating layer located on the third undercoat metal layer and having a thickness to fill the second groove, and a fourth electrolytic plating layer located on the fourth undercoat metal layer, continuous with the second electrolytic plating layer and the third electrolytic plating layer, and forming a first wiring conductor located from the first groove to the first surface and including a wide pattern, and a second wiring conductor located in the second groove and including a narrow pattern having a width of 15 ⁇ m or less, by removing at least the fourth undercoat metal layer and the fourth electrolytic plating layer located on the second upper surface.
  • a roughening treatment is performed on the side surface of the first electrolytic plating layer to give an arithmetic mean roughness Ra of 150 nm or more and 300 nm or less.
  • a groove formation process is performed such that the first inner surface and the second inner surface excluding the side surface of the wide pattern have an arithmetic mean roughness Ra of 50 nm or more and 100 nm or less.
  • the depth of the first groove is formed to be smaller than the thickness of the second insulating layer.
  • the step of forming the first wiring conductor and the second wiring conductor at least the fourth base metal layer and the fourth electrolytic plating layer located on the second insulating layer are removed so that at least a portion of the surface of the first wiring conductor is not exposed.
  • the first groove is formed to a depth reaching the lower conductor layer.
  • the manufacturing method described in (15) above further includes the steps of: forming a third insulating layer having a third upper surface on the second upper surface; forming a second wide pattern having a width of 150 ⁇ m or more on the third upper surface; covering the third upper surface and the second wide pattern and forming a fourth insulating layer having a fourth upper surface; forming a third groove recessed from the fourth upper surface toward the third insulating layer, contacting a side surface of the second wide pattern and reaching the first wiring conductor, on both sides sandwiching the second wiring conductor; and forming a third wiring conductor located from the third groove to the third upper surface, including the second wide pattern, and a portion of which contacts the first wiring conductor, on both sides sandwiching the second wiring conductor.

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PCT/JP2023/044427 2022-12-20 2023-12-12 配線基板およびその製造方法 WO2024135456A1 (ja)

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JP2008235624A (ja) * 2007-03-22 2008-10-02 Kyocer Slc Technologies Corp 配線基板およびその製造方法
JP2016207841A (ja) * 2015-04-22 2016-12-08 新光電気工業株式会社 配線基板及びその製造方法
JP2017084979A (ja) * 2015-10-28 2017-05-18 富士通株式会社 配線の形成方法および配線構造
JP2020113609A (ja) * 2019-01-09 2020-07-27 新光電気工業株式会社 積層基板及び積層基板製造方法

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