WO2024134788A1 - 半導体光素子 - Google Patents

半導体光素子 Download PDF

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Publication number
WO2024134788A1
WO2024134788A1 PCT/JP2022/046950 JP2022046950W WO2024134788A1 WO 2024134788 A1 WO2024134788 A1 WO 2024134788A1 JP 2022046950 W JP2022046950 W JP 2022046950W WO 2024134788 A1 WO2024134788 A1 WO 2024134788A1
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Prior art keywords
layer
contact
semiconductor optical
type electrode
optical device
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PCT/JP2022/046950
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English (en)
French (fr)
Japanese (ja)
Inventor
歩 淵田
剛 境野
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2023523656A priority Critical patent/JPWO2024134788A1/ja
Priority to PCT/JP2022/046950 priority patent/WO2024134788A1/ja
Publication of WO2024134788A1 publication Critical patent/WO2024134788A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227—Buried mesa structure ; Striped active layer

Definitions

  • the present invention relates to a semiconductor optical element.
  • Waveguide-type semiconductor optical devices generally have a structure in which current is injected from electrodes provided above and below the active layer.
  • devices may be designed to weaken the optical confinement in the vertical direction of the active layer in order to reduce optical absorption loss in the active layer or narrow the beam width in the vertical direction.
  • the upper cladding layer is made thicker, the current injection path from above the active layer becomes longer, which causes the problem of increased element resistance. Furthermore, the increased element resistance also causes the problem of increased heat generation.
  • One method of reducing element resistance is to increase the carrier concentration in the upper cladding layer, but in this case, the optical absorption loss in the upper cladding increases, which causes the problem of reduced optical output.
  • Patent Document 1 discloses a semiconductor optical element in which an electrode is provided diagonally above the active layer to improve heat dissipation. With this configuration, it is possible to reduce the distance from the electrode to the active layer without having to consider the leakage of light upward from the active layer. In other words, the current path can be shortened, and therefore the element resistance can be reduced. However, the above-mentioned configuration has the problem that it is not possible to sufficiently reduce light absorption loss.
  • the present disclosure aims to provide a semiconductor optical element that can achieve both reduced element resistance and reduced optical absorption loss, even in a structure in which the active layer has weak optical confinement in the vertical direction.
  • An embodiment of the present disclosure is a semiconductor optical element that includes a p-type electrode, a contact layer in contact with the p-type electrode, a block layer in contact with the contact layer and having light confinement properties, a first cladding layer that is a light seepage region in contact with the block layer, an active layer having a ridge stripe structure sandwiched on both sides by the block layer, a substrate in contact with the block layer, and an n-type electrode in contact with the substrate, and the p-type electrode is preferably formed in a position that does not overlap with the active layer in a planar view.
  • FIG. 1 is a cross-sectional view of a semiconductor optical device according to a first embodiment of the present disclosure.
  • 1 is a cross-sectional view of a semiconductor optical device according to a first modified example of the first embodiment of the present disclosure.
  • 1 is a cross-sectional view of a semiconductor optical device according to a second modification of the first embodiment of the present disclosure.
  • FIG. 11 is a cross-sectional view of a semiconductor optical device according to a second embodiment of the present disclosure.
  • FIG. 11 is a plan view of a semiconductor optical device according to a second embodiment of the present disclosure.
  • FIG. 11 is a cross-sectional view of a semiconductor optical device according to a third embodiment of the present disclosure.
  • First embodiment 1 is a cross-sectional view of a semiconductor optical device according to a first embodiment of the present disclosure.
  • the semiconductor optical device 100 includes an n-type electrode 9.
  • a substrate 1 is formed on the n-type electrode 9.
  • the substrate 1 is, for example, an n-type InP substrate.
  • An active layer 2 is formed on the substrate 1.
  • a cladding layer 3 is formed on the active layer 2.
  • the cladding layer 3 is, for example, a first p-type InP cladding layer.
  • the substrate 1, active layer 2, and cladding layer 3 form a ridge stripe structure 50.
  • the ridge stripe structure 50 is formed by growing the substrate 1, active layer 2, and cladding layer 3 in this order, and then etching down to below the active layer 2.
  • the sides of the ridge stripe structure 50 are filled with a high-resistance layer 41.
  • the high-resistance layer 41 is, for example, an InP layer doped with Fe, which is a semi-insulating material.
  • the high-resistance layer 41 is also part of the block layer 4.
  • the block layer 4 is a multilayer structure in which the high-resistance layer 41, the block layer 42, and the block layer 43 are stacked in this order.
  • the block layer 42 is, for example, an n-type InP block layer.
  • the block layer 43 is, for example, a p-type InP block layer.
  • the ridge stripe structure 50 and a portion of the block layer 4 are covered with a cladding layer 5.
  • the cladding layer 5 is, for example, a second p-type InP cladding layer.
  • the outermost surface of the cladding layer 5 is covered with an insulating film 7.
  • the insulating film 7 is made of, for example, SiO2 or SiN.
  • the ridge stripe structure 50 is embedded in the waveguide section 60.
  • the waveguide section 60 is an embedded waveguide structure in which the active layer 2 serves as a core layer, and the block layer 4, cladding layer 3, and cladding layer 5 serve as cladding layers.
  • the waveguide section 60 is sandwiched on both sides by the contact section 70.
  • the contact section 70 has a contact layer 6 on the block layer 4.
  • the contact layer 6 is, for example, a p-type InGaAs contact layer.
  • a p-type electrode 8 is formed on the contact layer 6.
  • the outermost surface of the contact layer 6 is covered with an insulating film 7 in the area other than the area in contact with the p-type electrode 8.
  • current 12 indicates the flow of current that flows when the semiconductor optical device 100 is in operation.
  • current is injected via the p-type electrode 8 and the n-type electrode 9. Holes injected from the p-type electrode 8 pass through the contact layer 6, the block layer 43, the lower part of the cladding layer 5, and the cladding layer 3, and are injected into the active layer 2. Meanwhile, electrons injected from the n-type electrode 9 pass through the substrate 1 and are injected into the active layer 2. In the active layer 2, the injected holes and electrons recombine, generating light.
  • the active layer 2 has a higher refractive index than the surrounding InP layers. Therefore, the generated light is confined in the active layer 2. However, some of the light seeps into the cladding layers 3 and 5. In particular, when the light confinement in the active layer 2 is weakened in order to reduce internal absorption loss in the active layer 2 or narrow the output beam width, there is a possibility that the light will penetrate the cladding layer 5.
  • the p-type InP doping concentration of the block layer 43, which is involved in the current resistance, and the cladding layer 3, which is the light seepage region can be designed to be different values. This makes it possible to achieve both a reduction in element resistance and a reduction in light absorption loss.
  • p-type InP has higher optical absorption loss than n-type InP.
  • the higher the doping concentration the higher the optical absorption loss, while lowering the doping concentration increases the resistance. Therefore, in conventional semiconductor optical devices with electrodes above the active layer, the doping concentration of the p-type InP layer represents a trade-off between device resistance and optical absorption loss.
  • the doping concentration of the cladding layer 3 is often about 1 ⁇ 10 18 cm -3 , but since the blocking layer 43 hardly overlaps with the light seeping out from the active layer 2, if the doping concentration is set to be higher than that of the cladding layer 3, for example, 2 ⁇ 10 18 cm -3 , the element resistance can be reduced without increasing the light absorption loss. Furthermore, if the blocking layer 43 is made thin, the distance from the p-type electrode 8 to the active layer 2 can be shortened without affecting the amount of light seeping out, thereby shortening the current path and reducing the element resistance.
  • the p-type electrode 8 is not provided above the active layer 2. That is, unlike conventional semiconductor optical devices, current injection is not performed from the top surface of the cladding layer 5. Therefore, the waveguide section 60 does not have an InGaAs layer with high light absorption, such as the contact layer 6. This makes it possible to further suppress light absorption loss.
  • an active layer 2 and a cladding layer 3 are grown on a substrate 1 having a (100) plane as its main surface.
  • the active layer 2 may include a quantum well structure or a quantum dot structure.
  • the active layer 2 is grown to a thickness of 200 nm using, for example, an AlGaInAs-based or InGaAsP-based material.
  • the cladding layer 3 is grown as a crystal to a thickness of 200 nm by, for example, MOCVD or MBE.
  • the cladding layer 3 is doped with, for example, Zn at a concentration of 1 ⁇ 10 18 cm -3 .
  • a stripe pattern mask is formed on the cladding layer 3 using photoresist.
  • the stripe pattern mask is made of a SiO2 film and extends in the [011] direction. Subsequently, etching is performed to below the active layer 2 to form a ridge stripe structure 50.
  • the high resistance layer 41 is, for example, an InP layer doped with Fe at a concentration of 5 ⁇ 10 18 cm -3 .
  • the block layer 42 is, for example, an n-type InP layer with a doping concentration of 5 ⁇ 10 18 cm -3 .
  • the block layer 43 is, for example, a p-type InP layer with a doping concentration of 2 ⁇ 10 18 cm -3 .
  • the contact layer 6 is, for example, a p-type InGaAs layer with a doping concentration of 1 ⁇ 10 19 cm -3 . In this way, the side surfaces of the ridge stripe structure 50 are filled with the block layer 4 and the contact layer 6 thereon.
  • the mask on the ridge stripe structure 50 is removed with hydrofluoric acid.
  • a stripe pattern mask is formed on the contact layer 6 in the contact portion 70 region.
  • the stripe pattern mask is made of a SiO2 film and extends in the [011] direction.
  • the contact layer 6 grown in the waveguide portion 60 region is removed using a chemical solution to expose the block layer 4.
  • This chemical solution is a selective etching chemical solution such as sulfuric acid.
  • a cladding layer 5 is grown so as to cover the ridge stripe structure 50 and the block layer 4.
  • a p-type electrode 8 is formed so as to contact the contact layer 6.
  • the p-type electrode 8 contains a metal such as Au, Ge, Ni, Ti, or Zn, and is formed by vapor deposition, metal sputtering, plating, or the like.
  • an n-type electrode 9 is formed on the rear surface of the substrate 1.
  • the n-type electrode 9 contains a metal such as Au, Ge, Ni, Ti, or Zn.
  • FIG. 2 is a cross-sectional view of a semiconductor optical device according to a first modified example of the first embodiment of the present disclosure.
  • the semiconductor optical device 200 differs from the semiconductor optical device 100 in the configuration of the block layer 4.
  • the semiconductor optical device 200 includes a block layer 4.
  • the block layer 4 is a multilayer structure in which a block layer 44, a block layer 42, and a block layer 45 are stacked in this order.
  • the block layer 44 is, for example, a first p-type InP block layer.
  • the block layer 42 is, for example, an n-type InP block layer.
  • the block layer 45 is, for example, a second p-type InP block layer.
  • FIG. 3 is a cross-sectional view of a semiconductor optical device according to a second modification of the first embodiment of the present disclosure.
  • the semiconductor optical device 300 differs from the semiconductor optical device 100 in that the cladding layer 5 includes a first region and a second region.
  • the semiconductor optical device 300 includes a p-type InP layer 51.
  • An undoped InP layer 52 is formed on the p-type InP layer 51.
  • the undoped InP layer 52 is unrelated to the current injection path, and is a layer that has a large element resistance and a small optical absorption loss compared to the p-type InP layer 51. Note that, for example, an n-type InP layer may be used instead of the undoped InP layer 52.
  • Holes in the semiconductor optical element 300 pass through the p-type electrode 8, contact layer 6, block layer 43, p-type InP layer 51, and cladding layer 3 in this order, and are injected into the active layer 2. Meanwhile, a portion of the light generated in the active layer 2 seeps into the cladding layer 3, p-type InP layer 51, and undoped InP layer 52. Since the optical absorption loss of the undoped InP layer 52 is smaller than that of the p-type InP layer 51, this configuration makes it possible to suppress optical absorption loss.
  • the semiconductor optical element 400 has a groove portion 80.
  • the groove portion 80 is provided at a position sandwiching the waveguide portion 60 and the contact portion 70.
  • the groove portion 80 also penetrates the block layer 4, and its surface is covered with an insulating film 7.
  • the waveguide portion 60 and the contact portion 70 sandwiched between the groove portion 80 form a mesa structure.
  • FIG. 5 is a plan view of a semiconductor optical device according to a second embodiment of the present disclosure. As can be seen from the semiconductor optical device 400a, the groove portion 80 is formed parallel to the waveguide portion 60 and the contact portion 70.
  • a method for manufacturing the semiconductor optical device 400 will be described.
  • the steps up to the formation of the cladding layer 5 are omitted since they are similar to those in the first embodiment.
  • etching is performed to penetrate the block layer 4 to form the grooves 80.
  • the etching may be dry etching using a gas such as SiCl4 , or wet etching using a chemical such as Br.
  • the width of the grooves 80 is, for example, 10 ⁇ m.
  • the width of the mesa structure sandwiched between the grooves 80 is, for example, 20 ⁇ m.
  • the insulating film 7 is made of, for example, SiO2 or SiN.
  • the subsequent manufacturing steps are the same as those in the first embodiment.
  • the configuration of this embodiment reduces parasitic capacitance, enabling high-speed operation. This makes it easier to apply this to directly modulated lasers and other devices that require high-speed operation.
  • Embodiment 3 6 is a cross-sectional view of a semiconductor optical device according to a third embodiment of the present disclosure.
  • the semiconductor optical device 500 differs from the semiconductor optical device 400 in that a groove 80a having an n-type electrode 9a is provided.
  • the semiconductor optical element 500 has a groove 80a.
  • the groove 80a has an opening in the insulating film 7 at its bottom.
  • An n-type electrode 9 is formed on top of the opening.
  • current 12a indicates the flow of current that flows when the semiconductor optical device 500 is in operation.
  • current is injected via the p-type electrode 8 and the n-type electrode 9. Holes injected from the p-type electrode 8 pass through the contact layer 6, the upper part of the block layer 4, the cladding layer 5, and the cladding layer 3, and are injected into the active layer 2. Meanwhile, electrons injected from the n-type electrode 9a pass through the substrate 1 and are injected into the active layer 2. In the active layer 2, the injected holes and electrons recombine, generating light.
  • the manufacturing method of the semiconductor optical element 500 will be described.
  • the process is the same as in embodiment 2 up to the step of forming the groove 80 by etching and covering the surfaces of the contact layer 6, cladding layer 5 and groove 80 with the insulating film 7.
  • openings are formed in the insulating film 7 at the contact 70 and groove 80.
  • a p-type electrode 8 and an n-type electrode 9 are formed at each opening.
  • the configuration of this embodiment not only reduces the regulated capacitance as in the second embodiment, but also allows the p-type electrode 8 and the n-type electrode 9 to be formed on the same surface. This allows for flexibility in the arrangement of electrical wiring. For example, when forming an array structure in which multiple semiconductor optical elements 500 are integrated on the same chip, it is possible to easily wire each optical element for independent operation.
  • the n-type electrode 9 is formed on the same surface as the p-type electrode 8, but the position of the n-type electrode 9 is not limited to this.
  • the n-type electrode 9 may be formed on any surface, including curved surfaces, as long as it is parallel to or facing the (100) surface, which is the main surface of the substrate 1.
  • the n-type electrode 9 cannot be formed only on surfaces parallel to the side surfaces of the groove portion 80 or only on surfaces parallel to the emission end surface.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Semiconductor Lasers (AREA)
PCT/JP2022/046950 2022-12-20 2022-12-20 半導体光素子 Ceased WO2024134788A1 (ja)

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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58116259U (ja) * 1982-01-29 1983-08-08 日本電気株式会社 半導体レ−ザ
JPS61196591A (ja) * 1985-02-25 1986-08-30 Nippon Telegr & Teleph Corp <Ntt> 半導体レ−ザ
JPS6254992A (ja) * 1985-09-03 1987-03-10 Nec Corp 半導体レ−ザ
JPS6490583A (en) * 1987-10-01 1989-04-07 Sumitomo Electric Industries Semiconductor laser element
JPH02130984A (ja) * 1988-11-11 1990-05-18 Nec Corp 半導体レーザ装置
JPH0927658A (ja) * 1995-07-13 1997-01-28 Nec Corp 半導体光集積回路およびその製造方法
JPH0997946A (ja) * 1995-07-21 1997-04-08 Matsushita Electric Ind Co Ltd 半導体レーザ及びその製造方法
JP2006165027A (ja) * 2004-12-02 2006-06-22 Fujitsu Ltd 半導体レーザ及びその製造方法
JP2012209489A (ja) * 2011-03-30 2012-10-25 Fujitsu Ltd 光半導体素子及びその製造方法
JP2017142348A (ja) * 2016-02-10 2017-08-17 古河電気工業株式会社 光導波路構造、光集積素子、および光導波路構造の製造方法
WO2022097258A1 (ja) * 2020-11-06 2022-05-12 三菱電機株式会社 光半導体装置およびその製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3230785B2 (ja) * 1993-11-11 2001-11-19 日本電信電話株式会社 半導体レーザおよびその製造方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58116259U (ja) * 1982-01-29 1983-08-08 日本電気株式会社 半導体レ−ザ
JPS61196591A (ja) * 1985-02-25 1986-08-30 Nippon Telegr & Teleph Corp <Ntt> 半導体レ−ザ
JPS6254992A (ja) * 1985-09-03 1987-03-10 Nec Corp 半導体レ−ザ
JPS6490583A (en) * 1987-10-01 1989-04-07 Sumitomo Electric Industries Semiconductor laser element
JPH02130984A (ja) * 1988-11-11 1990-05-18 Nec Corp 半導体レーザ装置
JPH0927658A (ja) * 1995-07-13 1997-01-28 Nec Corp 半導体光集積回路およびその製造方法
JPH0997946A (ja) * 1995-07-21 1997-04-08 Matsushita Electric Ind Co Ltd 半導体レーザ及びその製造方法
JP2006165027A (ja) * 2004-12-02 2006-06-22 Fujitsu Ltd 半導体レーザ及びその製造方法
JP2012209489A (ja) * 2011-03-30 2012-10-25 Fujitsu Ltd 光半導体素子及びその製造方法
JP2017142348A (ja) * 2016-02-10 2017-08-17 古河電気工業株式会社 光導波路構造、光集積素子、および光導波路構造の製造方法
WO2022097258A1 (ja) * 2020-11-06 2022-05-12 三菱電機株式会社 光半導体装置およびその製造方法

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