WO2022097258A1 - 光半導体装置およびその製造方法 - Google Patents
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- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
- H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
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- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/223—Buried stripe structure
- H01S5/2232—Buried stripe structure with inner confining structure between the active layer and the lower electrode
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- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/024—Arrangements for thermal management
- H01S5/02461—Structure or details of the laser chip to manipulate the heat flow, e.g. passive layers in the chip with a low heat conductivity
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- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/024—Arrangements for thermal management
- H01S5/02469—Passive cooling, e.g. where heat is removed by the housing as a whole or by a heat pipe without any active cooling element like a TEC
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- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
- H01S5/0425—Electrodes, e.g. characterised by the structure
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- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
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- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
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- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
- H01S5/3211—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures characterised by special cladding layers, e.g. details on band-discontinuities
- H01S5/3213—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures characterised by special cladding layers, e.g. details on band-discontinuities asymmetric clading layers
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- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/2205—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers
- H01S5/2222—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers having special electric properties
- H01S5/2224—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers having special electric properties semi-insulating semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
- H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/3235—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength longer than 1000 nm, e.g. InP-based 1300 nm and 1500 nm lasers
Definitions
- This disclosure relates to an optical semiconductor device and a method for manufacturing the same.
- ⁇ is the optical confinement coefficient
- W is the active layer width
- d is the active layer thickness
- q is the elementary charge
- dg / dn is the differential gain
- I op is the operating current. Represents the threshold current, respectively.
- the contact area between the p-type InGaAs contact layer and the p-side electrode is increased to reduce the contact resistance of the electrode portion.
- Another method is to reduce the crystal resistance of the bulk crystal by thinning the p-type InP clad layer. This is because the dominant factor in device resistance is the crystal resistance of bulk crystals.
- the p-type InP clad layer is thinned in order to reduce the crystal resistance, the volume of the crystal layer for dissipating the heat generated in the active layer is reduced. As a result, there is a problem that the thinning of the p-type InP clad layer deteriorates the heat dissipation property of the semiconductor laser, which in turn causes the element characteristics, particularly the temperature characteristics, to be significantly deteriorated.
- the present disclosure has been made in order to solve the above-mentioned problems, and an object of the present disclosure is to provide an optical semiconductor device having reduced element resistance and excellent heat dissipation, and a method for manufacturing the same.
- the optical semiconductor device has a striped ridge structure composed of a first conductive clad layer, an active layer and a second conductive first clad layer sequentially laminated on a first conductive semiconductor substrate, and the ridge structure.
- a striped mesa structure having both sides formed by a mesa reaching the first conductive semiconductor substrate from the second conductive contact layer as a center, and a first provided on the surface of the second conductive contact layer.
- a mesa protective film composed of a heat radiating layer having a width narrower than that of the two conductive contact layers, an insulating film covering both sides of the mesa structure and both ends of the surface of the second conductive contact layer, and the second conductive type.
- a second conductive type side electrode electrically connected to the contact layer is provided.
- the method for manufacturing an optical semiconductor device includes a first crystal growth step in which a first conductive clad layer, an active layer and a second conductive first clad layer are sequentially laminated on a first conductive semiconductor substrate, and the first crystal growth step described above.
- a ridge structure forming step of etching the one conductive clad layer, the active layer and the second conductive first clad layer into a striped ridge structure, and an embedded layer embedded so as to cover both side surfaces of the ridge structure are crystal-grown.
- a second crystal growth step of sequentially laminating a second conductive type second clad layer, a second conductive type contact layer and a heat radiating layer on the top of the ridge structure and the surface of the embedded layer.
- the second conductive type second clad layer can be thinned, the element resistance can be reduced and the heat dissipation is improved, so that the effect of excellent high temperature characteristics can be obtained. Play.
- FIG. 2 It is sectional drawing which shows the manufacturing method of the optical semiconductor device by Embodiment 2.
- FIG. 2 is sectional drawing which shows the manufacturing method of the optical semiconductor device by Embodiment 2.
- FIG. It is sectional drawing which shows the manufacturing method of the optical semiconductor device by Embodiment 2.
- FIG. It is sectional drawing which shows the manufacturing method of the optical semiconductor device by Embodiment 2.
- FIG. It is sectional drawing which shows the manufacturing method of the optical semiconductor device by Embodiment 2.
- FIG. It is sectional drawing which shows the structure of the optical semiconductor device by Embodiment 3.
- FIG. It is sectional drawing which shows the manufacturing method of the optical semiconductor device by Embodiment 3.
- FIG. It is sectional drawing which shows the manufacturing method of the optical semiconductor device by Embodiment 3.
- FIG. It is sectional drawing which shows the manufacturing method of the optical semiconductor device by Embodiment 3.
- FIG. It is sectional drawing which shows the structure of the optical semiconductor device by Embodiment 4.
- FIG. It is sectional drawing which shows the manufacturing method of the optical semiconductor device by Embodiment 4.
- FIG. It is sectional drawing which shows the manufacturing method of the optical semiconductor device by Embodiment 4.
- FIG. It is sectional drawing which shows the manufacturing method of the optical semiconductor device by Embodiment 4.
- FIG. It is sectional drawing which shows the structure of the optical semiconductor device according to Embodiment 5.
- FIG. It is sectional drawing which shows the structure of the optical semiconductor device according to Embodiment 6. It is sectional drawing which shows the structure of the optical semiconductor device according to Embodiment 7. It is sectional drawing which shows the structure of the optical semiconductor device by Embodiment 8. FIG. It is sectional drawing which shows the structure of the optical semiconductor device by a comparative example.
- FIG. 1 is a cross-sectional view showing the configuration of the optical semiconductor device 200 according to the first embodiment.
- the n-type InP clad layer 2 first conductive clad layer
- the active layer 3 and the p-type are sequentially laminated on the n-type InP substrate 1 (first conductive semiconductor substrate).
- a striped ridge structure 5 composed of an InP first clad layer 4 (second conductive type first clad layer) and an Fe-doped semi-insulating InP layer 6a (arbitrary) formed on both side surfaces of the striped ridge structure 5.
- An embedded layer 6 composed of a conductive semiconductor layer) and an n-type InP block layer 6b (first conductive block layer), and formed so as to cover the top of the striped ridge structure 5 and the surface of the n-type InP block layer 6b.
- a striped mesa whose both sides are formed by a type InP heat dissipation layer 9 (second conductive type heat dissipation layer) and a mesa reaching the n-type InP substrate 1 from the p-type InGaAs contact layer 8 centered on the striped ridge structure 5.
- a mesa protective film 10 (insulating film) composed of a structure 13 and SiO 2 formed so as to cover both side surfaces of the striped mesa structure 13 and both ends of the surface of the p-type InP heat dissipation layer 9 and the p-type InGaAs contact layer 8.
- a mesa protective film composed of), p-side electrodes 11 (second conductive-type side electrodes) provided on both sides of the p-type InP heat dissipation layer 9 on the surface of the p-type InGaAs contact layer 8, and the back surface of the n-type InP substrate 1. It is composed of an n-side electrode 12 (first conductive type side electrode) provided on the side.
- the Fe-doped semi-insulating InP layer 6a and the n-type InP block layer 6b are collectively referred to as an embedded layer 6.
- a crystal growth method such as a metalorganic chemical vapor deposition (MOCVD) method in which an n-type InP clad layer 2, an active layer 3, and a p-type InP first clad layer 4 are formed on the surface of an n-type InP substrate 1. Crystals grow sequentially (first crystal growth step).
- MOCVD metalorganic chemical vapor deposition
- a first SiO 2 film 101 is formed on the surface of the p-type InP first clad layer 4.
- Examples of the film forming method of the first SiO 2 film 101 include a CVD (Chemical Vapor Deposition) method.
- the first SiO 2 film 101 is patterned into stripes having a desired width by using a photolithography technique and an etching technique.
- the etching mask is not limited to the SiO 2 film, but may be a SiN film. Further, the etching is not limited to dry etching, and wet etching may be used.
- the embedded layer 6 composed of the Fe-doped semi-insulating InP layer 6a and the n-type InP block layer 6b is formed on both sides of the striped ridge structure 5 by MOCVD. Embed so as to cover the surface (second crystal growth step). That is, Fe-doped semi-insulating InP layers 6a and n-type InP block layers 6b as embedded layers 6 are formed on both side surfaces of the striped ridge structure 5.
- the structure of the embedded layer 6 is not limited to the two layers, and may be a structure in which three layers of a p-type InP layer, an Fe-doped semi-insulating InP layer, and an n-type InP layer are laminated in order.
- the striped first SiO 2 film 101 is removed by dry etching or the like.
- the p-type InP second clad layer 7 and the p-type InGaAs so as to cover the surface of the n-type InP block layer 6b and the top of the striped ridge structure 5, that is, the surface of the p-type InP first clad layer 4.
- the contact layer 8 and the p-type InP heat dissipation layer 9 are sequentially laminated by MOCVD (third crystal growth step).
- the heat dissipation layer 9 may be a p-type semiconductor layer (second conductive type semiconductor layer) other than InP, and in short, any material having excellent heat dissipation can be applied.
- a second SiO 2 film 102 is formed on the surface of the p-type InP heat dissipation layer 9.
- Examples of the film forming method of the second SiO 2 film 102 include a CVD method and the like. After the film formation of the second SiO 2 film 102 is performed, the second SiO 2 film 102 is patterned into stripes having a desired width by using a photolithography technique and an etching technique, as shown in FIG.
- the etching mask is not limited to the SiO 2 film, but may be a SiN film.
- a resist mask 103 is used so that the surface mesa width D1> the heat dissipation layer width D2 of the optical semiconductor device 200 is used, and the p-type InGaAs contact is centered on the striped ridge structure 5.
- a striped mesa structure 13 including the embedded layer 6 is formed (mesa structure forming step).
- the etching mask is not limited to the resist, and may be a SiO 2 film or a SiN film.
- the striped mesa structure 13 is formed in a striped shape by performing wet etching from the p-type InGaAs contact layer 8 to the middle of each of the Fe-doped semi-insulating InP layer 6a and the n-type InP clad layer 2. It may have a mesa structure.
- the mesa protective film 10 made of SiO 2 means the mesa protective film 10 made of an insulating film called SiO 2 .
- Examples of the film forming method of the mesa protective film 10 made of SiO 2 include a CVD method and the like.
- the mesa protective film 10 made of SiO 2 formed on both sides of the p-type InP heat dissipation layer 9 is provided with a mesa protective film opening by using photolithography technique and etching technique. 10a is provided.
- the mesa protective film 10 is provided with the mesa protective film opening 10a, the mesa protective film 10 has a shape that covers both ends of the surface of the p-type InGaAs contact layer 8.
- a p-side electrode 11 is formed in contact with the surface of the p-type InGaAs contact layer 8 at a portion where the mesa protective film openings 10a are provided on both sides of the p-type InP heat dissipation layer 9 (electrode forming step), and the n-type InP is formed.
- the n-side electrode 12 is formed on the back surface side of the substrate 1.
- the element resistance is reduced and the heat dissipation is improved, and as a result, the optical semiconductor device 200 having excellent high temperature characteristics can be easily manufactured. It is possible to manufacture with good reproducibility.
- FIG. 28 is a cross-sectional view showing the structure of the optical semiconductor device 500 as a comparative example.
- the optical semiconductor device 500 according to the comparative example has a striped ridge structure 5 composed of an n-type InP clad layer 2, an active layer 3, and a p-type InP first clad layer 4 sequentially laminated on the n-type InP substrate 1, and a striped shape.
- the embedded layer 6 composed of the Fe-doped semi-insulating InP layer 6a and the n-type InP block layer 6b formed on both side surfaces of the ridge structure 5, the top of the striped ridge structure 5 and the surface of the n-type InP block layer 6b.
- a mesa protective film 10 composed of a striped mesa structure 13 having a surface formed therein, and SiO 2 formed so as to cover both side surfaces of the striped mesa structure 13 and both ends of the surface of the p-type InGaAs contact layer 8.
- the p-side electrode 11 provided so as to cover almost the entire surface of the p-type InGaAs contact layer 8, and the n-side electrode 12 provided on the back surface side of the n-type InP substrate 1.
- the optical semiconductor device 200 By applying a forward bias between the p-side electrode 11 and the n-side electrode 12 of the optical semiconductor device 200, a current is injected from the p-type InGaAs contact layer 8.
- the injected current is current constricted in the region of the striped ridge structure 5 by the embedded layer 6, ie, the Fe-doped semi-insulating InP layer 6a and the n-type InP block layer 6b.
- the current injected into the active layer 3 generates laser light having a wavelength corresponding to the bandgap energy of the semiconductor layer constituting the active layer 3 in the active layer 3, and emits the laser light to the outside of the optical semiconductor device 200.
- the active layer is the main heat generation source.
- the heat generated in the active layer conducts heat to the surrounding semiconductor layer and spreads out of the active layer.
- the heat that conducts heat in the stacking direction is p from the active layer 3 through the p-type InP second clad layer 7 and the p-type InGaAs contact layer 8. It conducts heat to the side electrode 11 and dissipates heat to the outside of the optical semiconductor device 500.
- the thickening of the p-type InP second clad layer 7 brings about an increase in element resistance.
- Another issue in optical semiconductor devices is to reduce the element resistance.
- a method of reducing the element resistance as described above, a method of increasing the contact area between the p-type InGaAs contact layer and the p-side electrode to reduce the contact resistance of the electrode portion, or a method of reducing the contact resistance of the electrode portion is a dominant factor in the element resistance.
- a method of thinning the p-type InP clad layer In order to reduce the crystal resistance of a certain bulk crystal, there is a method of thinning the p-type InP clad layer. Therefore, the improvement of heat dissipation and the reduction of element resistance were in a trade-off relationship with respect to the setting of the layer thickness of the p-type InP second clad layer 7.
- a p-type InP heat dissipation layer 9 is newly provided in order to solve the above problems.
- the p-type InP heat dissipation layer 9 provided on the surface of the p-type InGaAs contact layer 8 efficiently transfers heat thermally conducted from the active layer 3 through the p-type InP second clad layer 7 and the p-type InGaAs contact layer 8. It functions to dissipate heat to the outside of the optical semiconductor device 200. That is, the p-type InP heat sink 9 plays a role of a heat sink.
- heat dissipation to the outside of the optical semiconductor device 200 is based on a comparative example in which the p-type InP heat dissipation layer 9 is not provided. This is because it can be realized more efficiently than the optical semiconductor device 500.
- the p-type InP heat dissipation layer 9 can efficiently dissipate heat, the p-type InP second clad layer 7 is made thicker than the original function of the clad layer is exhibited. Since there is no need to do so, it is possible to improve heat dissipation and reduce element resistance at the same time.
- the p-type InP heat dissipation layer 9 is provided on the surface of the p-type InGaAs contact layer 8, the p-type InP second clad layer is compared with the optical semiconductor device 500 according to the comparative example. Since 7 can be made thin, element resistance can be reduced, and since the p-type InP heat dissipation layer 9 improves heat dissipation, it also has an excellent effect on high temperature characteristics.
- FIG. 8 is a cross-sectional view showing the configuration of the optical semiconductor device 210 according to the second embodiment.
- the optical semiconductor device 210 according to the second embodiment includes a striped ridge structure 5 composed of an n-type InP clad layer 2, an active layer 3, and a p-type InP first clad layer 4 sequentially laminated on the n-type InP substrate 1.
- An embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b formed on both side surfaces of the striped ridge structure 5, and a top of the striped ridge structure 5 and an n-type InP block layer 6b.
- the p-type InP second clad layer 7 and the p-type InGaAs contact layer 8 formed so as to cover the surface of the surface, and the p-type InGaAs contact layer 8 to the n-type InP substrate 1 centered on the striped ridge structure 5.
- a striped mesa structure 13 having both sides formed by the above, and both sides of the striped mesa structure 13 and the p-type InP heat dissipation layer 9 and the p-type InGaAs contact layer 8 are formed so as to cover both ends of the surface.
- the p-type InP heat dissipation layer 9 is in contact with the p-type InP second clad layer 7 via the contact layer opening 8a provided in the p-type InGaAs contact layer 8. This is different from the configuration in which the p-type InP heat dissipation layer 9 is formed on the surface of the p-type InGaAs contact layer 8 in the optical semiconductor device 200 according to the first embodiment.
- a striped ridge structure 5 is formed on the surface of the n-type InP substrate 1, and a striped ridge structure 5 is formed by MOCVD with an embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b. It is the same as the manufacturing method of the optical semiconductor device 200 according to the first embodiment shown in FIGS. 2 to 4 until it is embedded so as to cover both side surfaces of the above.
- the first SiO 2 film 101 is removed by etching, and the p-type InP second clad layer 7 and the p-type InGaAs are formed on the surface of the n-type InP block layer 6b and the top of the striped ridge structure 5.
- the contact layers 8 are sequentially laminated by MOCVD (third crystal growth step).
- a third SiO 2 film 104 is formed on the surface of the p-type InGaAs contact layer 8.
- Examples of the film forming method of the third SiO 2 film 104 include a CVD method and the like. After forming the third SiO 2 film 104, as shown in FIG. 9, the third SiO 2 film 104 is formed into a striped third SiO 2 having a desired etching width D3 by using a photolithography technique and an etching technique. Patterning is performed so that the film opening 104a is provided.
- the p-type InGaAs contact layer 8 exposed to the third SiO 2 film opening 104a is combined with the p-type InP second clad layer 7.
- the contact layer opening 8a is provided by dry etching until it reaches the surface of the surface (contact layer etching step).
- the etching width D3 which is the opening width of the contact layer opening 8a, is set so that the surface mesa width D1> the etching width D3 of the optical semiconductor device 210.
- the etching mask is not limited to the SiO 2 film, but may be a SiN film.
- the third SiO 2 film 104 is removed by etching, and as shown in FIG. 11, the p-type InP heat dissipation layer 9 is laminated by MOCVD (fourth crystal growth step).
- the heat radiating layer 9 does not have to be a p-type InP, and a material other than InP may be used.
- the second SiO 2 film 102 is formed on the surface of the p-type InP heat-dissipating layer 9.
- the film forming method of the second SiO 2 film 102 include a CVD method and the like. After the film formation of the second SiO 2 film 102 is performed, the second SiO 2 film 102 is patterned into stripes having a desired width by using a photolithography technique and an etching technique, as shown in FIG.
- the stripes are formed by dry etching from the p-type InP heat dissipation layer 9 to the surface of the p-type InGaAs contact layer 8.
- a heat-dissipating layer portion made of a p-type InP heat-dissipating layer 9 having a shape is formed (heat-dissipating layer etching step).
- the p-type InP heat dissipation layer 9 has a striped shape whose bottom is in contact with the p-type InP second clad layer 7.
- the etching mask is not limited to the SiO 2 film, but may be a SiN film. Subsequent manufacturing methods are the same as the manufacturing method of the optical semiconductor device 200 according to the first embodiment.
- the optical semiconductor device 210 according to the second embodiment is manufactured by each of the above steps.
- the element resistance is reduced and the heat dissipation is improved, and as a result, the optical semiconductor device 210 having excellent high temperature characteristics can be easily manufactured. It is possible to manufacture with good reproducibility.
- the bottom of the p-type InP heat dissipation layer 9 is not the surface of the p-type InGaAs contact layer 8 as in the optical semiconductor device 200 according to the first embodiment, but the p-type InP second cladding. Since it is in contact with the layer 7, there is no p-type InGaAs contact layer 8 directly above the layering direction of the active layer 3, that is, on the top side of the striped mesa structure 13, so that the laser light from the p-type InGaAs contact layer 8 is emitted. Absorption is significantly reduced.
- the bandgap energy of the p-type InGaAs contact layer 8 is smaller than the bandgap energy of the active layer 3, and the p-type InGaAs contact layer 8 has an action of absorbing the laser beam emitted by the active layer 3, so that the active layer 3 is used.
- the far-field image (Far Field Pattern: FFP) of the laser light emitted from the active layer 3 may be disturbed in the stacking direction.
- the optical semiconductor device 210 according to the second embodiment exhibits the effect of the optical semiconductor device 200 according to the first embodiment, and further suppresses the disturbance of FFP in the direction perpendicular to the surface of the n-type InP substrate 1. It is possible to increase the output.
- the effect of the optical semiconductor device 200 according to the first embodiment that is, the effect of improving the heat dissipation and the effect of reducing the element resistance, is achieved, and the bottom of the p-type InP heat dissipation layer 9 is exhibited.
- FIG. 14 is a cross-sectional view showing the configuration of the optical semiconductor device 220 according to the third embodiment.
- the optical semiconductor device 220 according to the third embodiment has a striped ridge structure 5 composed of an n-type InP clad layer 2, an active layer 3 and a p-type InP first clad layer 4 sequentially laminated on the n-type InP substrate 1.
- An embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b formed on both side surfaces of the striped ridge structure 5, and a top of the striped ridge structure 5 and an n-type InP block layer 6b.
- an undoped InP high resistance layer 14 formed on the surface of the p-type InGaAs contact layer 8 a p-side electrode 11 provided so as to cover the p-type InGaAs contact layer 8 and the undoped InP high resistance layer 14, and n. It is composed of an n-side electrode 12 provided on the back surface side of the mold InP substrate 1.
- a striped ridge structure 5 is formed on the surface of the n-type InP substrate 1, and an embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b is formed on both side surfaces of the striped ridge structure 5. It is the same as the manufacturing method of the optical semiconductor device 200 according to the first embodiment shown in FIGS. 2 to 4 until it is embedded by MOCVD so as to cover the above.
- the first SiO 2 film 101 is removed, and as shown in FIG. 15, the surface of the n-type InP block layer 6b and the top of the striped ridge structure 5, that is, the p-type, are obtained by MOCVD.
- the p-type InP second clad layer 7, the p-type InGaAs contact layer 8 and the undoped InP high resistance layer 14 are sequentially laminated so as to cover the surface of the InP first clad layer 4 (third crystal growth step).
- the undoped InP which is a constituent material of the undoped InP high resistance layer 14, is an n-type InP clad layer 2, an active layer 3, a p-type InP first clad layer 4, and a p-type InP second clad layer 7 that constitute the optical semiconductor device 220. And has a higher resistance, that is, a higher resistance than the material constituting each layer of the p-type InGaAs contact layer 8.
- the semiconductor layer composed of undoped InP is referred to as a high resistance layer.
- the undoped InP high resistance layer 14 functions as a heat radiating layer that dissipates heat generated in the active layer 3 to the outside, similarly to the p-type InP heat radiating layer 9 constituting the optical semiconductor device 200 according to the first embodiment.
- the heat dissipation layer is made of a high resistance undoped InP material.
- the undoped InP high resistance layer 14 does not necessarily have to be undoped InP, and an n-type (second conductive type) or semi-insulating material may be used as long as it has high resistance. Further, as long as the resistance is high, a material other than InP may be used.
- the undoped InP high resistance layer 14 is dry-etched until it reaches the surface of the p-type InGaAs contact layer 8 to form a stripe shape.
- a high resistance layer portion composed of an undoped InP high resistance layer 14 is formed (heat dissipation layer etching step).
- the width of the undoped InP high resistance layer 14, that is, the high resistance layer width D4 is such that the surface mesa width D1> the high resistance layer width D4 of the optical semiconductor device 220, as shown in FIG. Set.
- the etching mask is not limited to the SiO 2 film, but may be a SiN film.
- p-type InGaAs is centered on the striped ridge structure 5 using a resist mask 103 so that the surface mesa width D1> the high resistance layer width D4 of the optical semiconductor device 220.
- a striped mesa structure 13 including the embedded layer 6 is formed (mesa structure forming step).
- the etching mask is not limited to the resist mask and may be a SiN film. Further, the etching is not limited to wet etching, and dry etching may be used.
- the striped mesa structure 13 is formed in a striped shape by performing wet etching from the p-type InGaAs contact layer 8 to the middle of each of the Fe-doped semi-insulating InP layer 6a and the n-type InP clad layer 2. It may have a mesa structure.
- the striped mesa structure 13 and the mesa protective film 10 made of SiO 2 are formed on the surface and both side surfaces of the p-type InP heat dissipation layer 9 (mesa protective film forming step).
- Examples of the film forming method of the mesa protective film 10 made of SiO 2 include a CVD method and the like.
- the mesa protective film 10 made of SiO 2 formed on both sides of the p-type InP heat dissipation layer 9 is provided with a mesa protective film opening by using photolithography technique and etching technique. 10a is provided.
- the mesa protective film 10 is provided with the mesa protective film opening 10a, the mesa protective film 10 has a shape that covers both ends of the surface of the p-type InGaAs contact layer 8.
- a p-side electrode 11 is provided so as to cover the surfaces of the p-type InGaAs contact layer 8 and the undoped InP high resistance layer 14 (electrode forming step), and the p-side electrode 11 is provided on the back surface side of the n-type InP substrate 1.
- the n-side electrode 12 is provided.
- the element resistance is reduced and the heat dissipation is improved, and as a result, the optical semiconductor device 220 having excellent high temperature characteristics can be easily manufactured. It is possible to manufacture with good reproducibility.
- the undoped InP high resistance layer 14 functions to efficiently dissipate heat conducted from the active layer 3 through the p-type InP second clad layer 7 and the p-type InGaAs contact layer 8 to the outside of the optical semiconductor device 220. do. That is, the undoped InP high resistance layer 14 serves as a heat sink.
- the undoped InP high resistance layer 14 is located higher than the p-type InGaAs contact layer 8 in the stacking direction, heat dissipation to the outside of the optical semiconductor device 220 is based on a comparative example in which the undoped InP high resistance layer 14 is not provided. This is because it can be realized more efficiently than the optical semiconductor device 500.
- the p-type InP second clad layer 7 is made thicker than the original function of the clad layer can be exhibited. Since there is no need for it, it is possible to improve heat dissipation and reduce element resistance at the same time.
- the p-side electrode 11 covers not only the p-type InGaAs contact layer 8 but also the undoped InP high resistance layer 14 so as to cover the entire surface including the side surface portion. It is provided in. Since the p-side electrode 11 has higher thermal conductivity than the semiconductor layer, the p-side electrode 11 provided on the surface of the undoped InP high resistance layer 14 also contributes to heat dissipation from the undoped InP high resistance layer 14. Therefore, the effect of further improving the heat dissipation of the optical semiconductor device 220 is brought about.
- the p-type InP second clad layer is compared with the optical semiconductor device 500 according to the comparative example. Since 7 can be made into a thin film, the element resistance can be reduced, and the undoped InP high resistance layer 14 improves the heat dissipation, so that the effect is excellent in high temperature characteristics. Further, since the p-side electrode 11 is provided on the entire surface of the undoped InP high resistance layer 14, the heat dissipation property can be further improved, so that the high temperature characteristic is further improved.
- FIG. 18 is a cross-sectional view showing the configuration of the optical semiconductor device 230 according to the fourth embodiment.
- the optical semiconductor device 230 according to the fourth embodiment includes a striped ridge structure 5 composed of an n-type InP clad layer 2, an active layer 3, and a p-type InP first clad layer 4 sequentially laminated on the n-type InP substrate 1.
- An embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b formed on both side surfaces of the striped ridge structure 5, and a top of the striped ridge structure 5 and an n-type InP block layer 6b.
- the undoped InP high resistance layer 14 in contact with the p-type InP second clad layer 7 via the contact layer opening 8a provided in the p-type InGaAs contact layer 8, the p-type InGaAs contact layer 8 and the undoped InP high resistance. It is composed of a p-side electrode 11 provided so as to cover the layer 14 and an n-side electrode 12 provided on the back surface side of the n-type InP substrate 1.
- a striped ridge structure 5 is formed on the surface of the n-type InP substrate 1, and an embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b is formed on both side surfaces of the striped ridge structure 5. It is the same as the manufacturing method of the optical semiconductor device 200 according to the first embodiment shown in FIGS. 2 to 4 until it is embedded by MOCVD so as to cover the above.
- the p-type InP second clad layer 7 and the p-type InGaAs contact layer 8 are sequentially laminated by MOCVD (third crystal growth step), and the striped third SiO 2 film 104 is used as an etching mask.
- the p-type InGaAs contact layer 8 is dry-etched until it reaches the surface of the p-type InP second clad layer 7 (contact layer etching step) until it is removed according to the second embodiment shown in FIGS. 9 and 10. This is the same as the manufacturing method of the optical semiconductor device 210.
- the undoped InP high resistance layer 14 is laminated by MOCVD (fourth crystal growth step) as shown in FIG.
- the high resistance layer 14 does not have to be an undoped InP, and may be an n-type or semi-insulating material, or may be a material other than InP.
- the second SiO 2 film 102 is formed on the surface of the undoped InP high resistance layer 14.
- Examples of the film forming method of the second SiO 2 film 102 include a CVD method and the like. After the film formation of the second SiO 2 film 102 is performed, the second SiO 2 film 102 is patterned into stripes having a desired width by using a photolithography technique and an etching technique, as shown in FIG.
- dry etching is performed from the undoped InP high resistance layer 14 until it reaches the surface of the p-type InGaAs contact layer 8.
- a high resistance layer portion made of an undoped InP high resistance layer 14 having a striped shape is formed (heat dissipation layer etching step).
- the etching mask is not limited to the SiO 2 film, but may be a SiN film. Subsequent manufacturing methods are the same as the manufacturing method of the optical semiconductor device 220 according to the third embodiment. By each of the above steps, the optical semiconductor device 230 according to the fourth embodiment is manufactured.
- the element resistance is reduced and the heat dissipation is improved, and as a result, the optical semiconductor device 230 having excellent high temperature characteristics can be easily manufactured. It is possible to manufacture with good reproducibility.
- the optical semiconductor device 230 according to the fourth embodiment has the same effect as the optical semiconductor device 220 according to the third embodiment, and the bottom of the undoped InP high resistance layer 14 is similar to the optical semiconductor device 220 according to the third embodiment. Since it is in contact with the p-type InP second clad layer 7 instead of the surface of the p-type InGaAs contact layer 8, the p-type InGaAs is located directly above the active layer 3 in the stacking direction, that is, on the top side of the striped mesa structure 13. Since there is no contact layer 8, the absorption of laser light by the p-type InGaAs contact layer 8 is significantly reduced.
- the optical semiconductor device 230 it is possible to suppress the disturbance of FFP in the direction perpendicular to the surface of the n-type InP substrate 1 and to increase the output.
- the effect of the optical semiconductor device 220 according to the third embodiment is achieved, and the bottom of the undoped InP high resistance layer 14 is exhibited.
- FIG. 22 is a cross-sectional view showing the configuration of the optical semiconductor device 240 according to the fifth embodiment.
- the optical semiconductor device 240 according to the fifth embodiment has a striped ridge structure 5 composed of an n-type InP clad layer 2, an active layer 3, and a p-type InP first clad layer 4 sequentially laminated on the n-type InP substrate 1.
- An embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b formed on both side surfaces of the striped ridge structure 5, and a top of the striped ridge structure 5 and an n-type InP block layer 6b.
- Both sides are formed by a p-type InP second clad layer 7 and a p-type InGaAs contact layer 8 formed so as to cover the surface of the p-type InGaAs contact layer 8 and a mesa reaching the n-type InP substrate 1 from the p-type InGaAs contact layer 8. From the SiO 2 film provided on both sides of the mesa structure 13 and the striped mesa structure, one end of which reaches the n-type InP substrate 1 exposed on both sides and the other end covers the embedded layer 6 exposed on both sides.
- Partial mesa protective film and p-type InP provided on the surface of the p-type InGaAs contact layer 8 and exposed on both sides of the striped mesa structure 13 on both sides of the p-type InGaAs contact layer 8 and similarly exposed. It is composed of a p-side electrode 11 provided so as to cover a part of both side surfaces of the second clad layer 7, and an n-side electrode 12 provided on the back surface side of the n-type InP substrate 1.
- a striped ridge structure 5 is formed on the surface of the n-type InP substrate 1, and a striped ridge structure 5 is formed by MOCVD with an embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b.
- MOCVD Metal Organic Chemical Vapor Deposition
- the process of embedding the p-type InP second clad layer 7 and the p-type InGaAs contact layer 8 sequentially by MOCVD is the same as the method for manufacturing the optical semiconductor device 210 according to the second embodiment. Is.
- both side surfaces are formed by wet etching mesas reaching the n-type InP substrate 1 from the p-type InGaAs contact layer 8 centering on the striped ridge structure 5.
- a striped mesa structure 13 including the embedded layer 6 is formed (mesa structure forming step).
- the etching mask is not limited to the resist mask 105, and may be a SiO 2 film or a SiN film.
- the striped mesa structure 13 is formed in a striped shape by wet etching from the p-type InGaAs contact layer 8 to the middle of either the Fe-doped semi-insulating InP layer 6a or the n-type InP clad layer 2. But it's okay.
- a partial mesa protective film 10b made of SiO 2 is formed on the entire surface including both side surfaces of the striped mesa structure 13, and the p-type InGaAs contact layer 8 and the p-type InP second are formed.
- the resist mask 106 is formed so that a part of the clad layer 7 is opened.
- the partial mesa protective film 10b made of SiO 2 is etched (partial mesa protective film forming step).
- the partial mesa protective film 10b made of SiO 2 needs to cover the n-type InP block layer 6b exposed on both side surfaces of the striped mesa structure 13.
- the p-side electrode 11 is formed on the front surface of the p-type InGaAs contact layer 8, and the n-side electrode 12 is formed on the back surface side of the n-type InP substrate 1.
- both ends of the p-side electrode 11 are a p-type InGaAs contact layer 8 exposed on both side surfaces and a p-type InP second clad layer.
- At least a part of 7 may be covered, or at least a part of the partial mesa protective film 10b composed of the p-type InGaAs contact layer 8 and the p-type InP second clad layer 7 exposed on both side surfaces and SiO 2 . May be covered.
- the element resistance is reduced and the heat dissipation is improved, and as a result, the optical semiconductor device 240 having excellent high temperature characteristics can be easily manufactured. It is possible to manufacture with good reproducibility.
- the portion where the p-side electrode 11 contacts the p-type InGaAs contact layer 8 is only the top of the striped mesa structure 13.
- the opening of the SiO 2 partial mesa protective film 10b is widened to the p-type InP second clad layer 7 exposed on both side surfaces of the striped mesa structure 13.
- Both ends of the p-side electrode 11 come into contact with the entire p-type InGaAs contact layer 8 including the portions exposed on both side surfaces and a part of the p-type InP second clad layer 7 exposed on both side surfaces.
- the heat dissipation of the device 240 is further improved.
- the contact area between the p-side electrode 11 and each semiconductor layer is increased as compared with the optical semiconductor device 500 according to the comparative example, so that the contact resistance between the two is reduced, and thus the optical semiconductor is reduced.
- This has the effect of reducing the element resistance of the device 240.
- the high temperature characteristic of the optical semiconductor device 240 is improved.
- FIG. 25 is a cross-sectional view showing the configuration of the optical semiconductor device 250 according to the sixth embodiment.
- the optical semiconductor device 250 according to the sixth embodiment has a striped ridge structure 5 composed of an n-type InP clad layer 2, an active layer 3, and a p-type InP first clad layer 4 sequentially laminated on the n-type InP substrate 1.
- An embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b formed on both side surfaces of the striped ridge structure 5, and a top of the striped ridge structure 5 and an n-type InP block layer 6b.
- the p-type InP second clad layer 7 and the top of the p-type InP second clad layer 7 are formed so as to cover the surface of the p-type InP, and the upper end thereof has an inverted mesa shape, that is, a shape that widens in the stacking direction.
- a p-type InGaAs contact layer 8 a striped mesa structure 13 formed by a mesa reaching from the p-type InGaAs contact layer 8 to the n-type InP substrate 1, and a striped mesa structure 13 provided on both side surfaces of the striped mesa structure 13 at one end.
- the p-side electrode 11 On both side surfaces of the p-type InGaAs contact layer 8, the p-side electrode 11 provided so as to cover a part of both side surfaces of the p-type InP second clad layer 7, and the back surface side of the n-type InP substrate 1. It is composed of the provided n-side electrode 12.
- a striped ridge structure 5 is formed on the surface of the n-type InP substrate 1, and a striped ridge structure 5 is formed by MOCVD with an embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b.
- the p-type InP second clad layer 7 and the p-type InGaAs contact layer 8 are sequentially laminated by MOCVD until the striped mesa structure 13 is formed. It is the same as the manufacturing method of the optical semiconductor device 240.
- wet etching is performed again with the resist mask 105 as it is without being removed.
- the etchant for example, a mixed solution of hydrogen bromide, nitric acid and hydrogen peroxide is used.
- the upper end of the p-type InP second clad layer 7 means the upper surface side of the upper and lower two surfaces of the p-type InP second clad layer 7 in the layer thickness direction, which is in contact with the p-type InGaAs contact layer 8.
- the p-type InP second clad layer 7 is etched in a cross section perpendicular to the stripe direction so as to have a wider width with respect to the stacking direction.
- the etchant other chemicals other than the above may be used as long as the etching in the reverse mesa direction can be performed.
- Subsequent manufacturing methods are the same as the manufacturing method of the optical semiconductor device 240 according to the fifth embodiment.
- the optical semiconductor device 250 according to the sixth embodiment is manufactured by each of the above steps.
- the element resistance is reduced and the heat dissipation is improved, and as a result, the optical semiconductor device 250 having excellent high temperature characteristics can be easily manufactured. It is possible to manufacture with good reproducibility.
- the p-type InGaAs contact layer 8 when the heat generated in the active layer 3 is thermally conducted to the p-type InGaAs contact layer 8 via the p-type InP second clad layer 7, the p-type InGaAs contact layer 8 is used. In addition to heat conduction from the surface of the p-side electrode 11 to the p-side electrode 11, heat conduction from both sides of the p-type InGaAs contact layer 8 and both sides of the p-type InP second clad layer 7 in contact with the p-side electrode 11. Occurs.
- both sides of the p-type InP second clad layer 7 and p are compared with the optical semiconductor device 240 according to the fifth embodiment. Since the contact area with the side electrode 11 can be structurally wider, the heat dissipation is further improved.
- the p-type InP second clad layer 7 having an inverted mesa shape at the upper end, that is, a shape having a wide width in the stacking direction is provided, and the p-type InP second clad layer 7 is provided.
- both side surfaces of the p-type InGaAs contact layer 8 is covered with the p-side electrode 11, in addition to heat conduction from the surface of the p-type InGaAs contact layer 8 to the p-side electrode 11, both side surfaces of the p-type InGaAs contact layer 8 and Since heat conduction is possible from the portions of the p-type InP second clad layer 7 in contact with the p-side electrode 11 on both side surfaces, the heat dissipation of the optical semiconductor device 250 is further improved, and as a result, the high temperature of the optical semiconductor device 250 is obtained. It has the effect of improving the characteristics.
- FIG. 26 is a cross-sectional view showing the configuration of the optical semiconductor device 260 according to the seventh embodiment.
- the optical semiconductor device 260 according to the seventh embodiment includes a striped ridge structure 5 composed of an n-type InP clad layer 2, an active layer 3, and a p-type InP first clad layer 4 sequentially laminated on the n-type InP substrate 1.
- An embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b formed on both side surfaces of the striped ridge structure 5, and a top of the striped ridge structure 5 and an n-type InP block layer 6b.
- the p-type InP second clad layer 7 and the top of the p-type InP second clad layer 7 are formed so as to cover the surface of the p-type InP, and the upper end thereof has a forward mesa shape, that is, a shape in which the width narrows in the stacking direction.
- a p-side electrode 11 provided so as to cover a part of the p-type InGaAs contact layer 8 and the p-type InP second clad layer 7 and having a shape in which the width narrows in the stacking direction, and the back surface side of the n-type InP substrate 1. It is composed of an n-side electrode 12 provided in the above.
- a striped ridge structure 5 is formed on the surface of the n-type InP substrate 1, and a striped ridge structure 5 is formed by MOCVD with an embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b.
- the p-type InP second clad layer 7 and the p-type InGaAs contact layer 8 are sequentially laminated by MOCVD until the striped mesa structure 13 is formed. It is the same as the manufacturing method of the optical semiconductor device 240.
- wet etching is performed again with the resist mask 105 as it is without being removed.
- etchant for example, a mixed solution of hydrochloric acid, hydrogen peroxide and acetic acid is used.
- At least a part of the upper end portion of the p-type InP second clad layer 7 is etched into a shape whose width is narrower with respect to the stacking direction in the cross section perpendicular to the stripe direction.
- the etchant other chemicals other than the above may be used as long as the etching in the forward mesa direction can be performed. Further, the etching surface is not limited to the forward mesa, and it is sufficient that etching having a gradient different from that of the striped mesa structure 13 can be realized, and a chemical solution capable of realizing such a shape may be used. Subsequent manufacturing methods are the same as the manufacturing method of the optical semiconductor device 240 according to the fifth embodiment.
- the optical semiconductor device 260 according to the seventh embodiment is manufactured by each of the above steps.
- the element resistance is reduced and the heat dissipation is improved, and as a result, the optical semiconductor device 260 having excellent high temperature characteristics can be easily manufactured. It is possible to manufacture with good reproducibility.
- the p-type InGaAs contact layer 8 is used.
- heat is also generated from the portions in contact with the p-side electrode 11 on both side surfaces of the p-type InGaAs contact layer 8 and both sides of the p-type InP second clad layer 7. Conduction occurs.
- the p-type InP second clad layer 7 and the p-type InGaAs contact layer 8 have a forward mesa shape
- the p-type InP second clad is compared with the optical semiconductor device 240 according to the fifth embodiment. Since the contact area between both side surfaces of the layer 7 and the p-side electrode 11 can be structurally wider, the heat dissipation property is further improved.
- the p-type InP second clad layer 7 and the p-type InGaAs contact layer 8 are provided with a p-type InP second clad layer 7 and a p-type InGaAs contact layer 8 having a forward mesa shape at the upper end, that is, a shape whose width is narrowed in the stacking direction. Since at least a part of both side surfaces of the type InGaAs contact layer 8 and both side surfaces of the p-type InP second clad layer 7 is covered with the p-side electrode 11, the surface of the p-type InGaAs contact layer 8 is transferred to the p-side electrode 11.
- heat conduction is also possible from the portions in contact with the p-side electrode 11 on both side surfaces of the p-type InGaAs contact layer 8 and both side surfaces of the p-type InP second clad layer 7, so that the optical semiconductor can be used.
- the high temperature characteristic of the optical semiconductor device 260 is improved.
- FIG. 27 is a cross-sectional view showing the configuration of the optical semiconductor device 270 according to the eighth embodiment.
- the optical semiconductor device 270 according to the eighth embodiment has a striped ridge structure 5 composed of an n-type InP clad layer 2, an active layer 3, and a p-type InP first clad layer 4 sequentially laminated on the n-type InP substrate 1.
- An embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b formed on both side surfaces of the striped ridge structure 5, and a top of the striped ridge structure 5 and an n-type InP block layer 6b.
- the p-type InP second clad layer 7 formed to cover the surface of the p-type InGaAs contact layer 8 and the p-type InGaAs contact layer 8 having a periodic uneven pattern 15 formed on the surface, and the p-type InGaAs contact layer 8 to the n-type InP substrate 1
- the p-side electrode 11 provided so as to cover a part of both side surfaces of the p-type InP second clad layer 7 exposed, and the n-side electrode provided on the back surface side of the n-type InP substrate 1. It is composed of 12.
- a striped ridge structure 5 is formed on the surface of the n-type InP substrate 1, and a striped ridge structure 5 is formed by MOCVD with an embedded layer 6 composed of an Fe-doped semi-insulating InP layer 6a and an n-type InP block layer 6b.
- the p-type InP second clad layer 7 and the p-type InGaAs contact layer 8 are sequentially laminated by MOCVD until the striped mesa structure 13 is formed. It is the same as the manufacturing method of the optical semiconductor device 240.
- a SiO 2 film (not shown) is used as an etching mask for the p-type InGaAs contact layer 8, and a periodic uneven pattern 15 is formed by dry etching (concave and convex pattern forming step).
- the etching mask may be a SiN film, and the periodic uneven pattern 15 may be formed by wet etching.
- Subsequent manufacturing methods are the same as the manufacturing method of the optical semiconductor device 240 according to the fifth embodiment.
- the optical semiconductor device 270 according to the eighth embodiment is manufactured by each of the above steps.
- the element resistance is reduced and the heat dissipation is improved, and as a result, the optical semiconductor device 270 having excellent high temperature characteristics can be easily manufactured. It is possible to manufacture with good reproducibility.
- the effective surface area of the p-type InGaAs contact layer 8 can be increased by forming the periodic uneven pattern 15 on the surface of the p-type InGaAs contact layer 8, so that the p-type can be increased. Heat conduction from the InGaAs contact layer 8 to the p-side electrode 11 is promoted more smoothly. As a result, the heat dissipation of the optical semiconductor device 270 is further improved. Further, since the contact area between the p-type InGaAs contact layer 8 and the p-side electrode 11 can be increased, the element resistance of the optical semiconductor device 270 can be reduced.
- the periodic uneven pattern 15 has been described as an example, but it goes without saying that the uneven pattern 15 is not periodic and the same effect can be obtained even with a randomly formed uneven pattern 15.
- the cross-sectional shape of the uneven pattern 15 may be a groove shape having an acute angle or a groove shape having an obtuse angle, in addition to the shape exhibiting a rectangle.
- the direction of the periodic uneven pattern 15 shows the uneven pattern 15 that is repeated in the width direction of the striped mesa structure 13, but the same is true for the uneven pattern 15 that is repeated in the direction along the stripe. It works.
- the periodic uneven pattern 15 formed on the p-type InGaAs contact layer 8 is shown as an example, but the shape is such that the bottom of the periodic uneven pattern 15 reaches the p-type InP second clad layer 7. Then, the contact area with the p-side electrode 11 is further increased, so that the heat dissipation is further improved.
- the heat dissipation of the optical semiconductor device 270 is remarkably improved by forming the uneven pattern 15 on the surface of the p-type InGaAs contact layer 8, so that the high temperature of the optical semiconductor device 270 is obtained. It has the effect of further improving the characteristics. Further, since the contact resistance between the p-type InGaAs contact layer 8 and the p-side electrode 11 is reduced, the effect of reducing the element resistance of the optical semiconductor device 270 is also achieved.
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Abstract
Description
図1は、実施の形態1による光半導体装置200の構成を示す断面図である。
実施の形態1による光半導体装置200は、n型InP基板1(第一導電型半導体基板)に順次積層されたn型InPクラッド層2(第一導電型クラッド層)、活性層3、p型InP第一クラッド層4(第二導電型第一クラッド層)からなるストライプ状のリッジ構造5と、ストライプ状のリッジ構造5の両側面に形成されたFeドープ半絶縁性InP層6a(任意の導電型の半導体層)およびn型InPブロック層6b(第一導電型ブロック層)からなる埋め込み層6と、ストライプ状のリッジ構造5の頂部およびn型InPブロック層6bの表面を覆うように形成されたp型InP第二クラッド層7(第二導電型第二クラッド層)およびp型InGaAsコンタクト層8(第二導電型コンタクト層)と、p型InGaAsコンタクト層8の表面に形成されたp型InP放熱層9(第二導電型放熱層)と、ストライプ状のリッジ構造5を中心としp型InGaAsコンタクト層8からn型InP基板1に達するメサによって両側面が形成されたストライプ状のメサ構造13と、ストライプ状のメサ構造13の両側面とp型InP放熱層9とp型InGaAsコンタクト層8の表面の両端部を覆うように形成されたSiO2からなるメサ保護膜10(絶縁膜からなるメサ保護膜)と、p型InGaAsコンタクト層8の表面でp型InP放熱層9の両側に設けられたp側電極11(第二導電型側電極)と、n型InP基板1の裏面側に設けられたn側電極12(第一導電型側電極)と、で構成される。
なお、Feドープ半絶縁性InP層6aとn型InPブロック層6bを総称して、埋め込み層6と称する。
n型InP基板1の表面に、n型InPクラッド層2、活性層3、p型InP第一クラッド層4を、有機金属気相成長法(Metal Organic Chemical Vapor Deposition:MOCVD)等の結晶成長方法によって順次結晶成長する(第一結晶成長工程)。
なお、埋め込み層6の構成は、かかる2層の構成に限らず、p型InP層、Feドープ半絶縁性InP層およびn型InP層の3層を順に積層した構成でも良い。
次に、n型InPブロック層6bの表面およびストライプ状のリッジ構造5の頂部、すなわち、p型InP第一クラッド層4の表面を覆うように、p型InP第二クラッド層7、p型InGaAsコンタクト層8およびp型InP放熱層9をMOCVDにより順次積層する(第三結晶成長工程)。なお、放熱層9は、InP以外のp型の半導体層(第二導電型の半導体層)でも良く、要するに、放熱性に優れた材料であれば適用可能である。
この際、p型InP放熱層9の放熱層幅D2は、図7に示すように、光半導体装置200の表面メサ幅D1>放熱層幅D2となるように設定する。なお、エッチングマスクはSiO2膜に限らずSiN膜でも良い。
以上の各工程により、実施の形態1による光半導体装置200が製造される。
比較例による光半導体装置500は、n型InP基板1に順次積層されたn型InPクラッド層2、活性層3、p型InP第一クラッド層4からなるストライプ状のリッジ構造5と、ストライプ状のリッジ構造5の両側面に形成されたFeドープ半絶縁性InP層6aおよびn型InPブロック層6bからなる埋め込み層6と、ストライプ状のリッジ構造5の頂部およびn型InPブロック層6bの表面を覆うように形成されたp型InP第二クラッド層7およびp型InGaAsコンタクト層8と、ストライプ状のリッジ構造5を中心としp型InGaAsコンタクト層8からn型InP基板1に達するメサによって両側面が形成されたストライプ状のメサ構造13と、ストライプ状のメサ構造13の両側面とp型InGaAsコンタクト層8の表面の両端部を覆うように形成されたSiO2からなるメサ保護膜10と、p型InGaAsコンタクト層8の表面のほぼ全面を覆うように設けられたp側電極11と、n型InP基板1の裏面側に設けられたn側電極12と、で構成される。
光半導体装置200のp側電極11とn側電極12の間に順方向バイアスを印加することにより、電流がp型InGaAsコンタクト層8から注入される。注入された電流は、埋め込み層6、すなわち、Feドープ半絶縁性InP層6aおよびn型InPブロック層6bによって、ストライプ状のリッジ構造5の領域に電流狭窄される。活性層3に注入された電流により、活性層3において活性層3を構成する半導体層のバンドギャップエネルギーに対応した波長のレーザ光が発生し、光半導体装置200の外部に出射される。
一般に、光半導体装置(半導体レーザ)では、活性層が主な熱発生源となる。活性層で発生した熱は、周囲の半導体層に熱伝導して活性層外へと広がっていく。
比較例による光半導体装置500では、活性層3で発生した熱のうち、積層方向に熱伝導する熱は、活性層3からp型InP第二クラッド層7、p型InGaAsコンタクト層8を経てp側電極11へと熱伝導し、光半導体装置500の外部へと放熱される。
したがって、放熱性の向上と素子抵抗の低減は、p型InP第二クラッド層7の層厚の設定に関して、トレードオフの関係にあった。
p型InGaAsコンタクト層8の表面に設けられたp型InP放熱層9は、活性層3からp型InP第二クラッド層7、p型InGaAsコンタクト層8を経て熱伝導された熱を、効率良く光半導体装置200の外部に放熱するように機能する。すなわち、p型InP放熱層9はヒートシンク的な役割を果たす。p型InP放熱層9は、積層方向において、p型InGaAsコンタクト層8よりも高く位置するため、光半導体装置200の外部への放熱が、p型InP放熱層9が設けられていない比較例による光半導体装置500に比べて、より一層効率的に実現できるからである。
図8は、実施の形態2による光半導体装置210の構成を示す断面図である。
実施の形態2による光半導体装置210は、n型InP基板1に順次積層されたn型InPクラッド層2、活性層3、p型InP第一クラッド層4からなるストライプ状のリッジ構造5と、ストライプ状のリッジ構造5の両側面に形成されたFeドープ半絶縁性InP層6aおよびn型InPブロック層6bからなる埋め込み層6と、ストライプ状のリッジ構造5の頂部およびn型InPブロック層6bの表面を覆うように形成されたp型InP第二クラッド層7およびp型InGaAsコンタクト層8と、ストライプ状のリッジ構造5を中心としp型InGaAsコンタクト層8からn型InP基板1に達するメサによって両側面が形成されたストライプ状のメサ構造13と、ストライプ状のメサ構造13の両側面とp型InP放熱層9とp型InGaAsコンタクト層8の表面の両端部を覆うように形成されたSiO2からなるメサ保護膜10と、p型InGaAsコンタクト層8に設けられたコンタクト層開口部8aを介してp型InP第二クラッド層7に接するp型InP放熱層9と、p型InGaAsコンタクト層8の表面でp型InP放熱層9の両側に設けられたp側電極11と、n型InP基板1の裏面側に設けられたn側電極12と、で構成される。
n型InP基板1の表面に、ストライプ状のリッジ構造5を形成し、MOCVDによって、Feドープ半絶縁性InP層6aとn型InPブロック層6bからなる埋め込み層6で、ストライプ状のリッジ構造5の両側面を覆うように埋め込むまでは、図2から図4に示す実施の形態1による光半導体装置200の製造方法と同様である。
第三SiO2膜104の成膜後、図9に示すように、フォトリソグラフィ技術およびエッチング技術を用いて、第三SiO2膜104を、所望のエッチング幅D3を有するストライプ状の第三SiO2膜開口部104aが設けられるようにパターニングする。
以降の製造方法は、実施の形態1による光半導体装置200の製造方法と同様である。
以上の各工程により実施の形態2による光半導体装置210が製造される。
図14は、実施の形態3による光半導体装置220の構成を示す断面図である。
実施の形態3による光半導体装置220は、n型InP基板1に順次積層されたn型InPクラッド層2、活性層3およびp型InP第一クラッド層4からなるストライプ状のリッジ構造5と、ストライプ状のリッジ構造5の両側面に形成されたFeドープ半絶縁性InP層6aおよびn型InPブロック層6bからなる埋め込み層6と、ストライプ状のリッジ構造5の頂部およびn型InPブロック層6bの表面を覆うように形成されたp型InP第二クラッド層7およびp型InGaAsコンタクト層8と、ストライプ状のリッジ構造5を中心としp型InGaAsコンタクト層8からn型InP基板1に達するメサによって両側面が形成されたストライプ状のメサ構造13と、ストライプ状のメサ構造13の両側面とp型InGaAsコンタクト層8の表面の両端部を覆うように形成されたSiO2からなるメサ保護膜10と、p型InGaAsコンタクト層8の表面に形成されたアンドープInP高抵抗層14と、p型InGaAsコンタクト層8およびアンドープInP高抵抗層14を覆うように設けられたp側電極11と、n型InP基板1の裏面側に設けられたn側電極12と、で構成される。
n型InP基板1の表面に、ストライプ状のリッジ構造5を形成し、Feドープ半絶縁性InP層6aとn型InPブロック層6bからなる埋め込み層6で、ストライプ状のリッジ構造5の両側面を覆うようにMOCVDによって埋め込むまでは、図2から図4に示す実施の形態1による光半導体装置200の製造方法と同様である。
以上の各工程により、実施の形態3による光半導体装置220が製造される。
アンドープInP高抵抗層14は、活性層3からp型InP第二クラッド層7、p型InGaAsコンタクト層8を経て熱伝導された熱を、効率良く光半導体装置220の外部に放熱するように機能する。すなわち、アンドープInP高抵抗層14はヒートシンクの役割を果たす。
アンドープInP高抵抗層14は、積層方向において、p型InGaAsコンタクト層8よりも高く位置するため、光半導体装置220の外部への放熱が、アンドープInP高抵抗層14が設けられていない比較例による光半導体装置500に比べて、より一層効率的に実現できるからである。
さらに、アンドープInP高抵抗層14の表面全体にp側電極11を設けているので、さらなる放熱性の向上が可能となるため、高温特性が一層向上するという効果を奏する。
図18は、実施の形態4による光半導体装置230の構成を示す断面図である。
実施の形態4による光半導体装置230は、n型InP基板1に順次積層されたn型InPクラッド層2、活性層3、p型InP第一クラッド層4からなるストライプ状のリッジ構造5と、ストライプ状のリッジ構造5の両側面に形成されたFeドープ半絶縁性InP層6aおよびn型InPブロック層6bからなる埋め込み層6と、ストライプ状のリッジ構造5の頂部およびn型InPブロック層6bの表面を覆うように形成されたp型InP第二クラッド層7およびp型InGaAsコンタクト層8と、ストライプ状のリッジ構造5を中心としp型InGaAsコンタクト層8からn型InP基板1に達するメサによって両側面が形成されたストライプ状のメサ構造13と、ストライプ状のメサ構造13の両側面とp型InGaAsコンタクト層8の表面の両端部を覆うように形成されたSiO2からなるメサ保護膜10と、p型InGaAsコンタクト層8に設けられたコンタクト層開口部8aを介してp型InP第二クラッド層7に接するアンドープInP高抵抗層14と、p型InGaAsコンタクト層8およびアンドープInP高抵抗層14を覆うように設けられたp側電極11と、n型InP基板1の裏面側に設けられたn側電極12と、で構成される。
n型InP基板1の表面に、ストライプ状のリッジ構造5を形成し、Feドープ半絶縁性InP層6aとn型InPブロック層6bからなる埋め込み層6で、ストライプ状のリッジ構造5の両側面を覆うようにMOCVDによって埋め込むまでは、図2から図4に示す実施の形態1による光半導体装置200の製造方法と同様である。
以降の製造方法は、実施の形態3による光半導体装置220の製造方法と同様である。
以上の各工程により、実施の形態4による光半導体装置230が製造される。
図22は、実施の形態5による光半導体装置240の構成を示す断面図である。
実施の形態5による光半導体装置240は、n型InP基板1に順次積層されたn型InPクラッド層2、活性層3、p型InP第一クラッド層4からなるストライプ状のリッジ構造5と、ストライプ状のリッジ構造5の両側面に形成されたFeドープ半絶縁性InP層6aおよびn型InPブロック層6bからなる埋め込み層6と、ストライプ状のリッジ構造5の頂部およびn型InPブロック層6bの表面を覆うように形成されたp型InP第二クラッド層7およびp型InGaAsコンタクト層8と、p型InGaAsコンタクト層8からn型InP基板1に達するメサによって両側面が形成されたストライプ状のメサ構造13と、ストライプ状のメサ構造の両側面に設けられ、一端が両側面に露出したn型InP基板1に達し、他端が両側面に露出した埋め込み層6を覆うSiO2膜からなる部分メサ保護膜と、p型InGaAsコンタクト層8の表面に設けられ、かつ、ストライプ状のメサ構造13の両側面に露出したp型InGaAsコンタクト層8の両側面および同様に露出したp型InP第二クラッド層7の両側面の一部を覆うように設けられたp側電極11と、n型InP基板1の裏面側に設けられたn側電極12と、で構成される。
n型InP基板1の表面に、ストライプ状のリッジ構造5を形成し、MOCVDによって、Feドープ半絶縁性InP層6aとn型InPブロック層6bからなる埋め込み層6で、ストライプ状のリッジ構造5の両側面を覆うように埋め込み、さらに、p型InP第二クラッド層7およびp型InGaAsコンタクト層8をMOCVDにより順次積層する工程までは、実施の形態2による光半導体装置210の製造方法と同様である。
上述のp側電極11の形成において、ストライプ状のメサ構造13の両側面では、p側電極11の両端部は、両側面に露出したp型InGaAsコンタクト層8と、p型InP第二クラッド層7の少なくとも一部を覆っていても良いし、あるいは、両側面に露出したp型InGaAsコンタクト層8およびp型InP第二クラッド層7と、SiO2からなる部分メサ保護膜10bの少なくとも一部を覆っていても良い。
以上の各工程により、実施の形態5による光半導体装置240が製造される。
一方、実施の形態5による光半導体装置240では、SiO2部分メサ保護膜10bの開口部をストライプ状のメサ構造13の両側面に露出したp型InP第二クラッド層7まで拡幅しているので、p側電極11の両端部が、両側面に露出した部位を含むp型InGaAsコンタクト層8の全体および両側面に露出したp型InP第二クラッド層7の一部と接触するため、光半導体装置240の放熱性が一層向上する。
図25は、実施の形態6による光半導体装置250の構成を示す断面図である。
実施の形態6による光半導体装置250は、n型InP基板1に順次積層されたn型InPクラッド層2、活性層3、p型InP第一クラッド層4からなるストライプ状のリッジ構造5と、ストライプ状のリッジ構造5の両側面に形成されたFeドープ半絶縁性InP層6aおよびn型InPブロック層6bからなる埋め込み層6と、ストライプ状のリッジ構造5の頂部およびn型InPブロック層6bの表面を覆うように形成され、上端部が逆メサ形状、すなわち、積層方向において幅が広がる形状を呈するp型InP第二クラッド層7と、p型InP第二クラッド層7の頂部に形成されたp型InGaAsコンタクト層8と、p型InGaAsコンタクト層8からn型InP基板1に達するメサによって形成されたストライプ状のメサ構造13と、ストライプ状のメサ構造13の両側面に設けられ、一端が両側面に露出したn型InP基板1に達し、他端が両側面に露出した埋め込み層6を覆うSiO2膜からなる部分メサ保護膜10bと、p型InGaAsコンタクト層8の表面に設けられ、かつ、p型InGaAsコンタクト層8の両側面と、p型InP第二クラッド層7の両側面の一部を覆うように設けられたp側電極11と、n型InP基板1の裏面側に設けられたn側電極12と、で構成される。
n型InP基板1の表面に、ストライプ状のリッジ構造5を形成し、MOCVDによって、Feドープ半絶縁性InP層6aとn型InPブロック層6bからなる埋め込み層6で、ストライプ状のリッジ構造5の両側面を覆うように埋め込み、さらに、p型InP第二クラッド層7、p型InGaAsコンタクト層8をMOCVDにより順次積層し、ストライプ状のメサ構造13を形成するまでは、実施の形態5による光半導体装置240の製造方法と同様である。
なお、エッチャントは、逆メサ方向のエッチングが行えるならば、上記以外の他の薬液を用いても構わない。
以降の製造方法は、実施の形態5による光半導体装置240の製造方法と同様である。
以上の各工程により実施の形態6による光半導体装置250が製造される。
図26は、実施の形態7による光半導体装置260の構成を示す断面図である。
実施の形態7による光半導体装置260は、n型InP基板1に順次積層されたn型InPクラッド層2、活性層3、p型InP第一クラッド層4からなるストライプ状のリッジ構造5と、ストライプ状のリッジ構造5の両側面に形成されたFeドープ半絶縁性InP層6aおよびn型InPブロック層6bからなる埋め込み層6と、ストライプ状のリッジ構造5の頂部およびn型InPブロック層6bの表面を覆うように形成され、上端部が順メサ形状、すなわち、積層方向において幅が狭まる形状を呈するp型InP第二クラッド層7と、p型InP第二クラッド層7の頂部に形成されp型InP第二クラッド層7と同じく順メサ形状を呈するp型InGaAsコンタクト層8と、p型InGaAsコンタクト層8からn型InP基板1に達するメサによって形成されたストライプ状のメサ構造13と、ストライプ状のメサ構造13の両側面に設けられ、一端が両側面に露出したn型InP基板1に達し、他端が両側面に露出した埋め込み層6を覆うSiO2膜からなる部分メサ保護膜10bと、p型InGaAsコンタクト層8およびp型InP第二クラッド層7の一部を覆うように設けられ積層方向において幅が狭まる形状を呈するp側電極11と、n型InP基板1の裏面側に設けられたn側電極12と、で構成される。
n型InP基板1の表面に、ストライプ状のリッジ構造5を形成し、MOCVDによって、Feドープ半絶縁性InP層6aとn型InPブロック層6bからなる埋め込み層6で、ストライプ状のリッジ構造5の両側面を覆うように埋め込み、さらに、p型InP第二クラッド層7、p型InGaAsコンタクト層8をMOCVDにより順次積層し、ストライプ状のメサ構造13を形成するまでは、実施の形態5による光半導体装置240の製造方法と同様である。
以降の製造方法は、実施の形態5による光半導体装置240の製造方法と同様である。
以上の各工程により実施の形態7による光半導体装置260が製造される。
図27は、実施の形態8による光半導体装置270の構成を示す断面図である。
実施の形態8による光半導体装置270は、n型InP基板1に順次積層されたn型InPクラッド層2、活性層3、p型InP第一クラッド層4からなるストライプ状のリッジ構造5と、ストライプ状のリッジ構造5の両側面に形成されたFeドープ半絶縁性InP層6aおよびn型InPブロック層6bからなる埋め込み層6と、ストライプ状のリッジ構造5の頂部およびn型InPブロック層6bの表面を覆うように形成されたp型InP第二クラッド層7および表面に周期的な凹凸パターン15が形成されたp型InGaAsコンタクト層8と、p型InGaAsコンタクト層8からn型InP基板1に達するメサによって形成されたストライプ状のメサ構造13と、ストライプ状のメサ構造13の両側面に設けられ、一端が両側面に露出したn型InP基板1に達し、他端が両側面に露出した埋め込み層6を覆うSiO2膜からなる部分メサ保護膜10bと、p型InGaAsコンタクト層8の表面に設けられ、かつ、ストライプ状のメサ構造13の両側面に露出したp型InGaAsコンタクト層8の両側面および同様に露出したp型InP第二クラッド層7の両側面の一部を覆うように設けられたp側電極11と、n型InP基板1の裏面側に設けられたn側電極12と、で構成される。
n型InP基板1の表面に、ストライプ状のリッジ構造5を形成し、MOCVDによって、Feドープ半絶縁性InP層6aとn型InPブロック層6bからなる埋め込み層6で、ストライプ状のリッジ構造5の両側面を覆うように埋め込み、さらに、p型InP第二クラッド層7、p型InGaAsコンタクト層8をMOCVDにより順次積層し、ストライプ状のメサ構造13を形成するまでは、実施の形態5による光半導体装置240の製造方法と同様である。
以降の製造方法は、実施の形態5による光半導体装置240の製造方法と同様である。
以上の各工程により実施の形態8による光半導体装置270が製造される。
Claims (20)
- 第一導電型半導体基板に順次積層された第一導電型クラッド層、活性層および第二導電型第一クラッド層からなるストライプ状のリッジ構造と、
前記リッジ構造の両側面を覆うように埋め込まれた埋め込み層と、
前記リッジ構造の頂部および前記埋め込み層の表面に順次積層された第二導電型第二クラッド層および第二導電型コンタクト層と、
前記リッジ構造を中心とし、前記第二導電型コンタクト層から前記第一導電型半導体基板に達するメサによって両側面が形成されたストライプ状のメサ構造と、
前記第二導電型コンタクト層の表面に設けられ、前記第二導電型コンタクト層よりも狭い幅を有する放熱層と、
前記メサ構造の両側面および前記第二導電型コンタクト層の表面の両端部を覆う絶縁膜からなるメサ保護膜と、
前記第二導電型コンタクト層と電気的に接続された第二導電型側電極と、
を備える光半導体装置。 - 第一導電型半導体基板に順次積層された第一導電型クラッド層、活性層および第二導電型第一クラッド層からなるストライプ状のリッジ構造と、
前記リッジ構造の両側面を覆うように埋め込まれた埋め込み層と、
前記リッジ構造の頂部および前記埋め込み層の表面に順次積層された第二導電型第二クラッド層および第二導電型コンタクト層と、
前記リッジ構造を中心とし、前記第二導電型コンタクト層から前記第一導電型半導体基板に達するメサによって両側面が形成されたストライプ状のメサ構造と、
前記第二導電型コンタクト層に設けられたコンタクト層開口部を介して前記第二導電型第二クラッド層の表面に形成された放熱層と、
前記メサ構造の両側面および前記第二導電型コンタクト層の表面の両端部を覆う絶縁膜からなるメサ保護膜と、
前記第二導電型コンタクト層と電気的に接続された第二導電型側電極と、
を備える光半導体装置。 - 前記放熱層は、第二導電型の半導体層で構成されていることを特徴とする請求項1または2に記載の光半導体装置
- 前記放熱層は、高抵抗層で構成されていることを特徴とする請求項1または2に記載の光半導体装置
- 第一導電型半導体基板に順次積層された第一導電型クラッド層、活性層および第二導電型第一クラッド層からなるストライプ状のリッジ構造と、
前記リッジ構造の両側面を覆うように埋め込まれた埋め込み層と、
前記リッジ構造の頂部および前記埋め込み層の表面に順次積層された第二導電型第二クラッド層および第二導電型コンタクト層と、
前記リッジ構造を中心とし、前記第二導電型コンタクト層から前記第一導電型半導体基板に達するメサによって両側面が形成されたストライプ状のメサ構造と、
前記メサ構造の両側面に設けられ、一端が前記両側面に露出した前記第一導電型半導体基板に達し、他端が少なくとも前記両側面に露出した前記埋め込み層を覆う絶縁膜からなる部分メサ保護膜と、
前記第二導電型コンタクト層の表面を覆い、かつ、両端部において前記メサ構造の両側面に露出した前記第二導電型コンタクト層の両側面および前記第二導電型第二クラッド層の両側面の少なくとも一部を覆うように形成された第二導電型側電極と、
を備える光半導体装置。 - 前記第二導電型側電極の両端部が、前記部分メサ保護膜の他端を覆うように形成されることを特徴とする請求項5に記載の光半導体装置。
- 前記第二導電型第二クラッド層の上端部の少なくとも一部が、ストライプ方向に垂直な断面において、積層方向に対して幅が広がる形状を呈することを特徴とする請求項5または6に記載の光半導体装置。
- 前記第二導電型第二クラッド層の上端部の少なくとも一部が、ストライプ方向に垂直な断面において、積層方向に対して幅が狭まる形状を呈することを特徴とする請求項5または6に記載の光半導体装置。
- 前記第二導電型コンタクト層が、ストライプ方向に垂直な断面において、積層方向に対して幅が狭まる形状を呈することを特徴とする請求項8に記載の光半導体装置。
- 前記第二導電型コンタクト層の表面に凹凸パターンが形成されていることを特徴とする請求項5または6に記載の光半導体装置。
- 前記凹凸パターンは周期的に設けられていることを特徴とする請求項10に記載の光半導体装置。
- 第一導電型半導体基板に、第一導電型クラッド層、活性層および第二導電型第一クラッド層を順次積層する第一結晶成長工程と、
前記第一導電型クラッド層、前記活性層および前記第二導電型第一クラッド層をストライプ状のリッジ構造にエッチングするリッジ構造形成工程と、
前記リッジ構造の両側面を覆うように埋め込む埋め込み層を結晶成長する第二結晶成長工程と、
前記リッジ構造の頂部および前記埋め込み層の表面に、第二導電型第二クラッド層、第二導電型コンタクト層および放熱層を順次積層する第三結晶成長工程と、
前記放熱層を、前記リッジ構造の幅よりも広い幅を有するストライプ状にエッチングする放熱層エッチング工程と、
前記リッジ構造を中心とし、前記第二導電型コンタクト層から前記第一導電型半導体基板に達するメサによってメサ構造の両側面を形成するメサ構造形成工程と、
前記メサ構造の両側面および前記第二導電型コンタクト層の表面の両端部を覆う絶縁膜からなるメサ保護膜を形成するメサ保護膜形成工程と、
前記第二導電型コンタクト層の表面に、前記第二導電型コンタクト層と電気的に接続された第二導電型側電極を形成する電極形成工程と、
を含む光半導体装置の製造方法。 - 第一導電型半導体基板に、第一導電型クラッド層、活性層および第二導電型第一クラッド層を順次積層する第一結晶成長工程と、
前記第一導電型クラッド層、前記活性層および前記第二導電型第一クラッド層をストライプ状のリッジ構造にエッチングするリッジ構造形成工程と、
前記リッジ構造の両側面を覆うように埋め込む埋め込み層を結晶成長する第二結晶成長工程と、
前記リッジ構造の頂部および前記埋め込み層の表面に、第二導電型第二クラッド層および第二導電型コンタクト層を順次積層する第三結晶成長工程と、
前記第二導電型コンタクト層に、底部に前記第二導電型第二クラッド層が露出するコンタクト層開口部をエッチングによって形成するコンタクト層エッチング工程と、
前記コンタクト層開口部および第二導電型コンタクト層の表面に放熱層を結晶成長する第四結晶成長工程と、
前記放熱層を、前記リッジ構造の幅よりも広い幅を有するストライプ状にエッチングする放熱層エッチング工程と、
前記リッジ構造を中心とし、前記第二導電型コンタクト層から前記第一導電型半導体基板に達するメサによってメサ構造の両側面を形成するメサ構造形成工程と、
前記メサ構造の両側面および前記第二導電型コンタクト層の表面の両端部を覆う絶縁膜からなるメサ保護膜を形成するメサ保護膜形成工程と、
前記第二導電型コンタクト層の表面に、前記第二導電型コンタクト層と電気的に接続された第二導電型側電極を形成する電極形成工程と、
を含む光半導体装置の製造方法。 - 第一導電型半導体基板に、第一導電型クラッド層、活性層および第二導電型第一クラッド層を順次積層する第一結晶成長工程と、
前記第一導電型クラッド層、前記活性層および前記第二導電型第一クラッド層をストライプ状のリッジ構造にエッチングするリッジ構造形成工程と、
前記リッジ構造の両側面を覆うように埋め込む埋め込み層を結晶成長する第二結晶成長工程と、
前記リッジ構造の頂部および前記埋め込み層の表面に、第二導電型第二クラッド層、第二導電型コンタクト層および放熱層を順次積層する第三結晶成長工程と、
前記リッジ構造を中心とし、前記第二導電型コンタクト層から前記第一導電型半導体基板に達するメサによってメサ構造の両側面を形成するメサ構造形成工程と、
前記メサ構造の両側面に設けられ、一端が前記両側面に露出した前記第一導電型半導体基板に達し、他端が少なくとも前記両側面に露出した前記埋め込み層を覆う絶縁膜からなる部分メサ保護膜を形成する部分メサ保護膜形成工程と、
前記第二導電型コンタクト層の表面を覆い、かつ、両端部において前記メサ構造の両側面に露出した前記第二導電型コンタクト層の両側面および前記第二導電型第二クラッド層の両側面の少なくとも一部を覆う第二導電型側電極を形成する電極形成工程と、
を含む光半導体装置の製造方法。 - 前記第二導電型側電極の両端部が、前記部分メサ保護膜の他端を覆うように形成されることを特徴とする請求項14に記載の光半導体装置の製造方法。
- 前記第二導電型第二クラッド層の上端部の少なくとも一部を、ストライプ方向に垂直な断面において、積層方向に対して幅が広がる形状にエッチング加工することを特徴とする請求項14または15に記載の光半導体装置の製造方法。
- 前記第二導電型第二クラッド層の上端部の少なくとも一部を、ストライプ方向に垂直な断面において、積層方向に対して幅が狭まる形状にエッチング加工することを特徴とする請求項14または15に記載の光半導体装置の製造方法。
- 前記第二導電型コンタクト層を、ストライプ方向に垂直な断面において、積層方向に対して幅が狭まる形状にエッチング加工することを特徴とする請求項17に記載の光半導体装置の製造方法。
- 前記第二導電型コンタクト層の表面に凹凸パターンを形成する凹凸パターン形成工程をさらに含むことを特徴とする請求項14または15に記載の光半導体装置の製造方法。
- 前記凹凸パターンは周期的に設けられていることを特徴とする請求項19に記載の光半導体装置の製造方法。
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TW110134360A TWI810653B (zh) | 2020-11-06 | 2021-09-15 | 光半導體裝置及其製造方法 |
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JP2004193232A (ja) * | 2002-12-10 | 2004-07-08 | Sanyo Electric Co Ltd | 半導体レーザ素子および半導体レーザ素子の製造方法 |
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TW202220318A (zh) | 2022-05-16 |
JP6910580B1 (ja) | 2021-07-28 |
US20230327405A1 (en) | 2023-10-12 |
JPWO2022097258A1 (ja) | 2022-05-12 |
CN116491036A (zh) | 2023-07-25 |
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