WO2024122644A1 - 半導体基板、半導体基板の製造方法および製造装置、並びに半導体デバイスの製造方法および製造装置 - Google Patents

半導体基板、半導体基板の製造方法および製造装置、並びに半導体デバイスの製造方法および製造装置 Download PDF

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WO2024122644A1
WO2024122644A1 PCT/JP2023/044088 JP2023044088W WO2024122644A1 WO 2024122644 A1 WO2024122644 A1 WO 2024122644A1 JP 2023044088 W JP2023044088 W JP 2023044088W WO 2024122644 A1 WO2024122644 A1 WO 2024122644A1
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Prior art keywords
ridge
tether
semiconductor substrate
substrate
wing
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PCT/JP2023/044088
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English (en)
French (fr)
Japanese (ja)
Inventor
雄一郎 林
祐基 谷口
克明 正木
剛 神川
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Kyocera Corp
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Kyocera Corp
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Priority to CN202380083494.1A priority Critical patent/CN120303772A/zh
Priority to JP2024563009A priority patent/JPWO2024122644A1/ja
Priority to EP23900756.0A priority patent/EP4632793A1/en
Priority to KR1020257018876A priority patent/KR20250109204A/ko
Publication of WO2024122644A1 publication Critical patent/WO2024122644A1/ja
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Definitions

  • This disclosure relates to semiconductor substrates, etc.
  • Patent Document 1 discloses a method (ELO method) in which a mask pattern including a mask portion and an opening is formed on a base substrate including a seed layer, and a nitride semiconductor layer is grown laterally on the mask portion, using the seed layer exposed in the opening as the growth starting point.
  • ELO method a method in which a mask pattern including a mask portion and an opening is formed on a base substrate including a seed layer, and a nitride semiconductor layer is grown laterally on the mask portion, using the seed layer exposed in the opening as the growth starting point.
  • the semiconductor substrate disclosed herein comprises a ridge substrate including a ridge portion extending in a first direction, and a first surface portion and a second surface portion that are positioned lower than the ridge portion and adjacent to each other via the ridge portion, and a nitride semiconductor layer located on the ridge substrate, the nitride semiconductor layer including a first tether portion located on the ridge portion, a first wing portion that is connected to the first tether portion while floating above the first surface portion, and a first recess that is located on the ridge portion and has a recessed shape relative to the first tether portion.
  • FIG. 1 is a plan view showing a configuration example of a semiconductor substrate according to an embodiment of the present invention
  • FIG. 2 is an example of a cross-sectional view including lines aa and bb in FIG. 4 is a cross-sectional view showing an example of the configuration of a first tether portion.
  • FIG. 4 is a cross-sectional view showing an example of the configuration of a first wing portion.
  • FIG. 4 is a cross-sectional view showing an example of the configuration of a first wing portion.
  • FIG. 2 is another example of a cross-sectional view taken along line aa and line bb in FIG. 1. 2 is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor substrate according to an embodiment of the present invention.
  • 1 is a block diagram showing a semiconductor substrate manufacturing apparatus according to an embodiment of the present invention; 5A to 5C are cross-sectional views showing another method for manufacturing a semiconductor substrate according to the present embodiment.
  • 13 is a plan view showing an example of separation of the tether portion and the wing portion.
  • FIG. 11 is a cross-sectional view showing an example of a tether portion and a wing portion being separated.
  • FIG. 11 is a cross-sectional view showing an example of a tether portion and a wing portion being separated.
  • FIG. 1 is a cross-sectional view showing an example of a semiconductor device configuration.
  • FIG. 2 is a top view showing an example of a semiconductor device configuration.
  • 1 is a plan view showing a configuration example of a semiconductor substrate according to an embodiment of the present invention; 1 is a cross-sectional view showing an example of the configuration of a semiconductor substrate according to an embodiment of the present invention.
  • 13 is a plan view showing an example of separation of the tether portion and the wing portion.
  • FIG. 11 is a cross-sectional view showing an example of a tether portion and a wing portion being separated.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 1 is a block diagram showing a semiconductor device manufacturing apparatus according to an embodiment of the present invention; 2 is a flowchart showing a method for manufacturing a semiconductor device according to the present embodiment.
  • 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 1 is a block diagram showing a semiconductor device manufacturing apparatus according to an embodiment of the present invention
  • 1 is a plan view showing a configuration example of a semiconductor substrate according to an embodiment of the present invention
  • 1 is a plan view showing a configuration example of a semiconductor substrate according to an embodiment of the present invention
  • 1 is a plan view showing a configuration example of a semiconductor substrate according to an embodiment of the present invention
  • 1 is a plan view showing a configuration example of a semiconductor substrate according to an embodiment of the present invention
  • 1 is a plan view showing a configuration example of a semiconductor substrate according to an embodiment of the present invention
  • 1 is a plan view showing a configuration example of a semiconductor substrate according to an embodiment of the present invention
  • 1 is a plan view showing a configuration example of a semiconductor substrate according to an embodiment of the present invention
  • 1 is a plan view showing a configuration example of a semiconductor substrate according to an embodiment of the present invention
  • 1 is a plan view showing a configuration example of a semiconductor substrate according to an embodiment of the present
  • FIG. 1 is a plan view showing an example of the configuration of a semiconductor substrate according to this embodiment.
  • FIG. 2 is an example of a cross-sectional view including lines a-a and b-b in FIG. 1.
  • the semiconductor substrate 10 includes a ridge portion RJ extending in a first direction X, a ridge substrate RS including a first surface portion F1 and a second surface portion F2 that are located lower than the ridge portion RJ and adjacent to each other via the ridge portion RJ, and a nitride semiconductor layer 8 located on the ridge substrate RS.
  • the nitride semiconductor layer 8 includes a first tether portion T1 located on the ridge portion RJ, a first wing portion W1 that is connected to the first tether portion T1 while floating above the first surface portion F1, and a first recessed portion B1 that is located on the ridge portion RJ and has a recessed shape relative to the first tether portion T1.
  • the direction from the ridge substrate RS to the nitride semiconductor layer 8 is defined as "upward", and a position above the target is defined as a higher position than the target.
  • the first wing portion W1 is raised above (separated from) the first surface portion F1, thereby reducing the internal stress in the first wing portion W1, and the first recess B1 reduces the internal stress on the ridge portion RJ of the nitride semiconductor layer 8. This reduces the warping of the semiconductor substrate 10 including the nitride semiconductor layer 8.
  • the contact area between the nitride semiconductor layer 8 and the ridge substrate RS can be reduced, and the nitride semiconductor layer 8 can be easily peeled off from the ridge substrate RS.
  • the contact area between the nitride semiconductor layer 8 and the ridge substrate RS can be further reduced, and the first wing portion W1 can be easily peeled off from the ridge substrate RS.
  • the first tether portion T1 and the first recessed portion B1 located on the ridge portion RJ the first tether portion T1 can be formed without etching the first wing portion W1, which has low internal stress. Also, compared to the case where the first wing portion W1 is etched, the ease of peeling off the first wing portion W1 can be increased while ensuring the width of the first wing portion W1, which has low internal stress.
  • the ridge substrate RS may include a main substrate 1 having a different lattice constant from the nitride semiconductor layer 8, the nitride semiconductor layer 8 may include a GaN-based semiconductor, and the main substrate 1 may be a silicon substrate or a silicon carbide substrate.
  • the nitride semiconductor layer 8 may include a second wing portion W2 connected to the first tether portion T1 in a state where it is floating from the second surface portion F2.
  • the nitride semiconductor layer 8 may include a second tether portion T2 located on the ridge portion RJ and spaced apart from the first tether portion T1, and the first wing portion W1 may be connected to the second tether portion T2. In this way, the first wing portion W1 can be held by the first and second tether portions T1 and T2, and the stability of the first wing portion W1 is increased.
  • the first tether portion T1 and the second tether portion T2 may be connected to both ends of the first wing portion W1 facing each other in the first direction X, and the first recess B1 may be located between the first tether portion T1 and the second tether portion T2.
  • the size of the first tether portion T1 in the first direction X may be 1 ⁇ 4 or less of the size of the first wing portion W1 in the first direction X. This makes it easier to separate the first tether portion T1 and the first wing portion W1.
  • the boundary BT between the first tether portion T1 and the first recess B1 may be located near the end of the first wing portion W1. This makes it easier to form a separation surface (e.g., a cleavage surface) at the end of the first wing portion W1 when a tape or support substrate is pressed against the surface of the semiconductor substrate 10 to peel off the first wing portion W1, as described below.
  • a separation surface e.g., a cleavage surface
  • the vicinity of the end of the first wing portion W1 may be, for example, a region 1 to 10 ⁇ m from the end of the first wing portion W1.
  • the upper surface of the ridge portion RJ may be a seed region S that serves as the starting point for crystal growth of the nitride semiconductor layer 8.
  • the bottom of the first recess B1 may reach the ridge portion RJ, and the seed region S may be exposed at the bottom of the first recess B1.
  • the ridge portion RJ may have a seed portion that includes a nitride semiconductor (e.g., GaN semiconductor, AlN), and the seed region S may be the upper surface of the seed portion.
  • the nitride semiconductor layer 8 contains a nitride semiconductor as a main component.
  • Specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride).
  • a GaN-based semiconductor is a semiconductor that contains gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.
  • the nitride semiconductor layer 8 may be doped (e.g., n-type including a donor) or non-doped.
  • a semiconductor substrate means a substrate including a semiconductor
  • the main substrate 1 of the ridge substrate RS may include a semiconductor (e.g., silicon, silicon carbide) or may not include a semiconductor.
  • An example of a main substrate 1 that does not include a semiconductor is a sapphire substrate.
  • the ridge substrate RS may be called a template substrate or a growth substrate. In the ridge substrate RS, a part of the main substrate 1 may be included in the ridge portion RJ.
  • the first direction X may be the m-axis direction ( ⁇ 1-100> direction) of the nitride semiconductor layer 8.
  • the second direction Y may be the a-axis direction ( ⁇ 11-20> direction) of the nitride semiconductor layer 8.
  • the thickness direction (third direction Z) of the nitride semiconductor layer 8 may be the c-axis direction ( ⁇ 0001> direction) of the nitride semiconductor layer 8, and the elevation direction in the semiconductor substrate 10 may be parallel to the c-axis. Viewing an object with a line of sight parallel to the normal direction (third direction Z) of the semiconductor substrate 10 (including perspective) is sometimes called "planar view".
  • the nitride semiconductor layer 8 can be formed by the ELO (Epitaxial Lateral Overgrowth) method, starting from the top surface (seed region S) of the ridge portion RJ.
  • ELO Epiaxial Lateral Overgrowth
  • the nitride semiconductor layer 8 can be formed by the ELO (Epitaxial Lateral Overgrowth) method, starting from the top surface (seed region S) of the ridge portion RJ.
  • the first and second tether portions T1 and T2 located above the ridge portion RJ may be dislocation inheritance portions with many threading dislocations, and the first and second wing portions W1 and W2 may be low-defect portions with a lower threading dislocation density compared to the dislocation inheritance portions.
  • the nitride semiconductor layer 8 may include a third wing portion W3 that is separated from the first wing portion W1 in the first direction X while floating above the first surface portion F1.
  • the nitride semiconductor layer 8 may include a third tether portion T3 located on the ridge portion RJ and separated from the first tether portion T1, and the third wing portion W3 may be connected to the third tether portion T3.
  • the nitride semiconductor layer 8 may include a third recess B3 that is located between the first tether portion T1 and the third tether portion T3 and has a recessed shape relative to the first tether portion T1.
  • the nitride semiconductor layer 8 may include a fourth wing portion W4 that is separated from the first wing portion W1 in the second direction Y while floating above the first surface portion F1.
  • the first wing portion W1 and the fourth wing portion W4 may be adjacent to each other via a gap GP.
  • the first surface portion F1 and the second surface portion F2 may each have a growth suppression function.
  • the first surface portion F1 is the first mask portion 5A
  • the second surface portion F2 is the second mask portion 5B
  • the first wing portion W1 may be located on the first mask portion 5A via the hollow portion JD.
  • the side surface of the ridge portion RJ may have a growth suppression function.
  • the thickness of the first tether portion T1 may be smaller than the thickness of the first wing portion W1.
  • the ratio of the area of the first tether portion T1 to the area of the first wing portion W1 may be 10 or greater.
  • the side surface of the first tether portion T1 may include a curved surface TS, and the inner wall of the first recess B1 may include a curved surface TS.
  • first to fourth wing sections W1 to W4 may be collectively referred to as wing section W, the first to third tether sections T1 to T3 as tether section T, and the first and second mask sections 5A and 5B as mask section 5.
  • FIG. 3 is a cross-sectional view showing an example of the configuration of the first tether portion.
  • the first recess B1 and the first tether portion T1 can be formed by patterning a vertical growth layer (base portion) crystal-grown on the ridge portion RJ.
  • the first tether portion T1 may have a tapered shape that narrows at the top.
  • FIGS. 4 and 5 are cross-sectional views showing examples of the configuration of the first wing portion.
  • the first wing portion W1 may include a first edge E1 connected to the first tether portion T1 and extending in a first direction X.
  • the first wing portion W1 may include a second edge E2 connected to the first tether portion T1 and extending in a second direction Y perpendicular to the first direction X.
  • the first and second edges E1 and E2 may be formed by patterning the nitride semiconductor layer 8, and the first wing portion W1 may include a tapered surface WS that tapers upward.
  • FIG. 6 is another example of a cross-sectional view taken along lines a-a and b-b in FIG. 1.
  • the bottom of the first recess B1 reaches the ridge portion RJ (the first recess B1 is an opening that penetrates the nitride semiconductor layer 8), but this is not limited to this.
  • the bottom of the first recess B1 may not reach the ridge portion RJ (the first recess B1 does not penetrate the nitride semiconductor layer 8).
  • FIG. 7 is a flowchart showing a method for manufacturing a semiconductor substrate according to this embodiment.
  • FIG. 8 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to this embodiment.
  • the method for manufacturing a semiconductor substrate according to this embodiment includes a step S10 of forming a ridge substrate RS including a ridge portion RJ extending in a first direction X and a first surface portion F1 and a second surface portion F2 that are lower than the ridge portion RJ and adjacent to each other through the ridge portion RJ, a step S20 of forming a nitride semiconductor layer 8 on the ridge substrate RS, and a step S30 of patterning the nitride semiconductor layer 8, for example, by dry etching, to form a first tether portion T1 located on the ridge portion RJ, a first wing portion W1 connected to the first tether portion T1 in a state of being floating above the first surface portion F1, and a first recess
  • step S20 the ELO method may be used, and the growth of the nitride semiconductor layer 8 may be stopped when the first wing portion W1 and the fourth wing portion W4, which grow toward each other (parallel to the second direction Y), do not meet (a gap GP is formed).
  • step S30 the first recess B1 and the first tether portion T1 may be formed by patterning the base portion UR (vertical growth layer) crystal-grown on the ridge portion RJ. For example, the part of the base portion UR that is not covered with resist and is etched may become the first recess B1, and the part that is covered with resist and is not etched may become the first tether portion T1.
  • a dry etching method may be used to etch the nitride semiconductor layer 8.
  • the second recess B2 and the third recess B3, and the gap (separation groove) between the first and third wing portions W1 and W3 may be formed in step S30.
  • FIG. 9 is a block diagram showing a semiconductor substrate manufacturing apparatus according to this embodiment.
  • the semiconductor substrate manufacturing apparatus 31 includes an apparatus M10 that performs step S10 in FIG. 7, an apparatus M20 that performs step S20 in FIG. 7, an apparatus M30 that performs step S30 in FIG. 7, and an apparatus M35 that controls the apparatuses M10, M20, and M30.
  • the apparatus M20 may be an MOCVD apparatus.
  • FIG. 10 is a cross-sectional view showing another method for manufacturing a semiconductor substrate according to this embodiment.
  • a nitride semiconductor layer 8 in contact with the mask pattern 6 is formed on a template substrate 7 having a seed portion 3 and a mask pattern 6 (including openings that expose the first and second mask portions 5A and 5B and the seed portion 3) formed on a main substrate 1, and then the nitride semiconductor layer 8 is patterned to form a first recess B1 and a first tether portion T1 in a base portion UR (vertical growth layer) grown on the openings of the mask pattern 6, and then the mask pattern 6 is removed to form a semiconductor substrate 10.
  • a base portion UR vertical growth layer
  • FIG. 11 is a plan view showing an example of the configuration of the semiconductor substrate according to this embodiment.
  • FIG. 12 is a cross-sectional view showing an example of the configuration of the semiconductor substrate according to this embodiment.
  • the semiconductor substrate 10 is located on the nitride semiconductor layer 8 and includes a functional layer 9 including an active layer, and the functional layer 9 may be located on the first wing portion W1.
  • An electrode D may be located on the functional layer 9.
  • the functional layer 9 may be located on the first tether portion T1, and the first tether portion T1 and the functional layer 9 may overlap in a planar view.
  • the functional layer 9 may include an active layer and a p-type layer.
  • the first recess B1 may not overlap the functional layer 9 in a planar view, as shown in FIGS. 11 and 12.
  • FIG. 13 is a plan view showing an example of the separation of the tether portion and the wing portion.
  • FIG. 14 is a cross-sectional view showing an example of the separation of the tether portion and the wing portion.
  • the first wing portion W1 can be separated from the first and second tether portions T1 and T2, and the laminate 15 can be divided into individual semiconductor devices 20 (semiconductor chips).
  • the adjacent portions A1 and A2 are broken at a plane CF parallel to the m-plane of the nitride semiconductor layer 8, and as shown in FIG. 14, the semiconductor device 20 can be transferred to the tape TP.
  • the cleavage plane the m-plane, the risk of debris due to cleavage is reduced and the transfer yield can be increased.
  • FIG. 15 is a cross-sectional view showing an example of the separation of the tether portion and the wing portion.
  • the support substrate ST e.g., a submount substrate
  • a metal layer e.g., a solder layer
  • the support substrate ST is pressed downward (pressed against the semiconductor substrate 10), whereby the adjacent portions A1 and A2 are split at a plane CF parallel to the m-plane of the nitride semiconductor layer 8, and the semiconductor device 20 can be transferred to the support substrate ST as shown in FIG. 15.
  • selective transfer may be performed in which only the laminate 15 including the first wing portion W1 is selectively transferred from among a plurality of laminates 15 each including a plurality of wing portions W.
  • FIG. 16 is a cross-sectional view showing an example of a semiconductor device configuration.
  • FIG. 17 is a top view showing an example of a semiconductor device configuration.
  • the semiconductor device 20 may include a first wing portion W1, a functional layer 9, and electrodes D1 and D2.
  • the functional layer 9 may include an n-type layer 9N, an active layer 9A, and a p-type layer 9P.
  • the n-type layer 9N may include an n-type GaN-based semiconductor
  • the p-type layer 9P may include a p-type GaN-based semiconductor.
  • the active layer 9A may have a quantum well structure.
  • the first wing portion W1 may be tapered to include a tapered surface WS, thereby increasing the light extraction efficiency to the back surface WB (the surface opposite to the surface on which the electrode D is located).
  • the electrode D1 may be an anode
  • the electrode D2 may be a cathode.
  • FIG. 18 is a plan view showing an example of the configuration of a semiconductor substrate according to this embodiment.
  • FIG. 19 is a cross-sectional view showing an example of the configuration of a semiconductor substrate according to this embodiment.
  • FIG. 20 is a plan view showing an example of the division of a tether portion and a wing portion.
  • FIG. 21 is a cross-sectional view showing an example of the division of a tether portion and a wing portion.
  • the first wing portion W1 can be separated from the first and second tether portions T1 and T2, and the laminate 15 can be divided into individual semiconductor devices 20 (semiconductor chips).
  • the adjacent portions A1 and A2 are cracked at a plane CF (e.g., a cleavage plane) parallel to the m-plane of the nitride semiconductor layer 8, and the semiconductor device 20 can be transferred to the tape TP as shown in Figure 21.
  • a plane CF e.g., a cleavage plane
  • Figure 22 is a flowchart showing a method for manufacturing a semiconductor device according to this embodiment.
  • Figure 23 is a cross-sectional view showing a method for manufacturing a semiconductor device according to this embodiment.
  • the method for manufacturing a semiconductor device according to this embodiment includes a ridge substrate RS including a ridge portion RJ extending in a first direction X, a first surface portion F1 and a second surface portion F2 that are lower than the ridge portion RJ and adjacent to each other through the ridge portion RJ, and a nitride semiconductor layer 8 located on the ridge substrate RS.
  • the nitride semiconductor layer 8 includes a first tether portion T1 located on the ridge portion RJ, a first wing portion W1 that is connected to the first tether portion T1 while floating above the first surface portion F1, and a first recess B1 located on the ridge portion RJ and having a recessed shape relative to the first tether portion T1.
  • the method includes a step S40 of preparing a semiconductor substrate 10, a step S50 of forming a functional layer 9 including an active layer 9A on the first wing portion W1, and a step S60 of obtaining a semiconductor device 20 by dividing the first wing portion W1 and the first tether portion T1.
  • step S50 the functional layer 9 (including, for example, an active layer 9A having a quantum well structure) can be formed on the first wing portion W that is substantially free of distortion, which has the advantage of improving the quality of the functional layer 9.
  • step S50 in addition to a support substrate ST such as a submount (see FIG. 23), a transfer tape can be used.
  • Step S60 may be performed after preparing the semiconductor substrate 10 (including the first tether portion T1, the first recess B1, and the functional layer 9) obtained by steps S40 and S50.
  • FIG. 24 is a block diagram showing a semiconductor device manufacturing apparatus according to this embodiment.
  • Semiconductor device manufacturing apparatus 61 may include apparatus M40 that performs step S40 in FIG. 22, apparatus M50 that performs step S50, apparatus M60 that performs step S60, and apparatus M65 that controls apparatus M40, M50, and M60.
  • FIG. 25 is a flowchart showing a method for manufacturing a semiconductor device according to this embodiment.
  • FIG. 26 is a cross-sectional view showing a method for manufacturing a semiconductor device according to this embodiment.
  • the method for manufacturing a semiconductor device according to this embodiment includes a step S70 of preparing a semiconductor substrate 10 including a ridge substrate RS including a ridge portion RJ extending in a first direction X, a first surface portion F1 and a second surface portion F2 that are located lower than the ridge portion RJ and adjacent to each other via the ridge portion RJ, and a nitride semiconductor layer 8 that is located on the ridge substrate RS and does not contact the first surface portion F1 and the second surface portion F2 (facing the first and second surface portions F1 and F2 via a hollow portion JS); It may include a step S80 of forming a layer 9 (including, for example, an active layer 9A), a step S85 of patterning the nitride semiconductor layer 8 after
  • the nitride semiconductor layer 8 and the functional layer 9 are patterned to form the first recess B1 and the first tether portion T1, which has the advantage that the nitride semiconductor layer 8 and the functional layer 9 (including the nitride semiconductor) can be formed continuously.
  • the gap between the first and third wing portions W1 and W3 may be formed in step S85.
  • a transfer tape may be used in addition to a support substrate ST such as a submount (see FIG. 26).
  • Step S90 may be performed after preparing the semiconductor substrate 10 (including the first tether portion T1, the first recess B1, and the functional layer 9) obtained by steps S70, S80, and S85.
  • FIG. 27 is a block diagram showing a semiconductor device manufacturing apparatus according to this embodiment.
  • the semiconductor device manufacturing apparatus 91 may include an apparatus M70 that performs step S70 in FIG. 25, an apparatus M80 that performs step S80, an apparatus M85 that performs step S85, an apparatus M90 that performs step S90, and an apparatus M95 that controls the apparatuses M70, M80, M85, and M90.
  • the size of the first and second tether parts T1 and T2 in the first direction X may be greater than 1/4 of the size of the first wing part W1 in the first direction X, and a first recess B1 having a circular opening may be located between the first and second tether parts T1 and T2.
  • the functional layer 9 and the electrode D may be located on the first wing part W1, or the functional layer 9 may be located on the first tether part T1.
  • first wing part W1 and the first and second tether parts T1 and T2 are separated by fracturing the part of the first wing part W1 adjacent to the first tether part T1 and the part of the first wing part W1 adjacent to the second tether part T2, and the laminate 15 including the first wing part W1, the functional layer 9, and the electrode D can be separated into individual semiconductor devices 20.
  • the nitride semiconductor layer 8 may include a third wing portion W3 that is separated from the first wing portion W1 in the first direction X while floating above the first surface portion F1, and the third wing portion W3 may be connected to the first tether portion T1.
  • the first wing portion W1 and the first and second tether portions T1 and T2 are separated, and the stack 15 including the first wing portion W1, the functional layer 9, and the electrode D can be singulated into semiconductor devices 20.
  • the first wing portion W1 may include a first cutout portion C1 adjacent to the first tether portion T1.
  • the first wing portion W1 may include first and second cutout portions C1 and C2 adjacent to the first tether portion T1, and in a planar view, a straight line CL connecting the tip of the first cutout portion C1 and the tip of the second cutout portion C2 may be oblique to the first direction X.
  • This straight line CL may be parallel to the m-plane of the nitride semiconductor layer 8.
  • the first wing portion W1 is separated from the first and second tether portions T1 and T2, and the laminate 15 including the first wing portion W1, the functional layer 9, and the electrode D can be singulated into individual semiconductor devices 20.
  • the width of the first recess B1 (size in the second direction Y) may be greater than the width of the ridge portion RJ. That is, the entire width of the ridge portion RJ may be exposed under the first recess B1.
  • a portion of the first tether portion T1 may be floating above the ridge substrate RS. That is, there may be a gap between a portion of the first tether portion T1 and the ridge substrate RS (first surface portion F1).
  • the inner circumference WE of the first wing portion W1 and the ridge portion RJ may be separated in the second direction Y.
  • the nitride semiconductor layer 8 is located on the ridge portion RJ and may include a second recess B2 that is recessed relative to the first tether portion T1, and the first tether portion T1 may be located between the first recess B1 and the second recess B2.
  • the first recess B1 may be adjacent to the first wing portion W1 and the second wing portion W2.
  • the first tether portion T1 may be connected to the center of the first wing portion W1 in the first direction X.
  • the size of the first tether portion T1 in the first direction X may be 1 ⁇ 4 or less of the size of the first wing portion W1 in the first direction X.
  • the first wing portion W1 and the first tether portion T1 can be separated by breaking a portion of the first wing portion W1 adjacent to the first tether portion T1, and the laminate 15 including the first wing portion W1, the functional layer 9, and the electrode D can be singulated into semiconductor devices 20.
  • the size of the first tether portion T1 in the first direction X may be greater than 1 ⁇ 4 the size of the first wing portion W1 in the first direction X.
  • the first wing portion W1 and the first tether portion T1 can be separated by breaking a portion of the first wing portion W1 adjacent to the first tether portion T1, and the laminate 15 including the first wing portion W1, the functional layer 9, and the electrode D can be singulated into semiconductor devices 20.
  • FIG. 38 is a cross-sectional view showing an example of the configuration of a ridge substrate.
  • a buffer portion 2 may be formed between the convex portion of the main substrate 1 and the seed portion 3.
  • the ridge portion RJ includes a part (convex portion) of the main substrate 1, but this is not limited to this.
  • a striped seed portion 3 may be formed on the main substrate 1 with a flat top surface to form the ridge portion RJ, or a buffer portion 2 may be formed between the main substrate 1 and the striped seed portion 3. In this case, the top surface of the seed portion 3 exposed from the mask pattern 6 becomes the seed region S.
  • a seed portion 3 with striped convex portions may be formed on the main substrate 1 with a flat top surface to form the ridge portion RJ.
  • the seed portion 3 can be made of GaN-based semiconductors, AlN, etc.
  • the buffer portion 2 can be made of Al, AlN, SiC, etc. When using a silicon substrate for the main substrate 1, it is desirable that the buffer portion 2 in contact with the silicon substrate does not contain gallium in order to prevent meltback (melting of silicon gallium).
  • the ridge substrate RS may have a main substrate 1, which is a heterogeneous substrate having a different lattice constant from that of the nitride semiconductor layer 8.
  • the surface orientation of the main substrate 1 is, for example, the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, or the 6H-SiC (0001) surface of a SiC substrate. These are merely examples, and any substrate and surface orientation may be used that allows the nitride semiconductor layer 8 to be grown by the ELO method.
  • the mask pattern 6 includes mask portions 5 (5A and 5B).
  • the mask portions 5 may function as selective growth masks (deposition suppression masks) for laterally growing the nitride semiconductor layer 8.
  • the mask portion 5 may be, for example, a single layer film including one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000 degrees or higher), or a laminated film including at least two of these.
  • a thermal oxide film obtained by subjecting a silicon substrate, a silicon nitride substrate, etc. to a thermal oxidation process may also be used as the mask portion 5.
  • the mask portion 5 may be a laminated film in which a silicon oxide film and a silicon nitride film are formed in this order.
  • the upper film in contact with the semiconductor layer 8 may be a silicon nitride film.
  • the nitride semiconductor layer 8 on the ridge substrate RS can be formed, for example, as follows.
  • the nitride semiconductor layer 8 is a GaN layer
  • the growth temperature is 1000-1200 degrees
  • the V/III ratio is 500-20000
  • the growth pressure is 50 kPa.
  • SiH 4 may be flowed for doping.
  • the deposition conditions for the nitride semiconductor layer 8 are preferably set in at least two stages. In the first stage, the deposition temperature is set to about 1030° C., the V/III is set to about 2000, and a growth nucleus (vertical growth layer) of the nitride semiconductor layer 8 is formed on the ridge portion RJ.
  • the thickness (height) of the growth nucleus is set to about 1 ⁇ m to 3 ⁇ m, and the width may be set to a size approximately equal to the width of the ridge portion RJ or slightly protruding in the a-axis direction ( ⁇ 11-20> direction).
  • the film formation temperature is increased by about 100° C.
  • the GaN layer is grown laterally (in the a-axis direction) from the growth nucleus, and the growth is stopped when the width of the gap GP between the nitride semiconductor layers 8 (GaN layers) growing in the opposite directions on the gap JS reaches a specified value (for example, 10 ⁇ m or less).
  • the semiconductor substrate 10 (with the nitride semiconductor layer 8 exposed) obtained as described above may be removed from the MOCVD apparatus and stored, or a functional layer 9 including an active layer or the like may be formed in the MOCVD apparatus.
  • the first wing portion W1 may have a ratio of its width in the first direction X to its thickness of 5.0 or more.
  • the first wing portion W1 may have a width in the first direction X of 7.0 ⁇ m or more.
  • the width of the gap GP may be greater than the thickness (height) of the void JS.
  • the ratio of the width of the first wing portion W1 to the width of the ridge portion RJ may be 3.0 or more.
  • the thickness (height) of the void JS may be 3.0 ⁇ m or less.
  • the thickness of the mask portion 5 may be 50 nm or less.
  • the seed portion 3 may be composed of a nitride semiconductor containing argon or oxygen at 2 ⁇ 10 18 /cm 3 or more.
  • FIG. 39 is a plan view showing an example of the configuration of a semiconductor substrate according to this embodiment.
  • FIG. 40 is an example of a cross-sectional view including lines a-a and b-b in FIG. 39.
  • the semiconductor substrate 10 includes a ridge portion RJ extending in the first direction X, a ridge substrate RS including a first surface portion F1 and a second surface portion F2 that are lower than the ridge portion RJ and adjacent to each other via the ridge portion RJ, and a nitride semiconductor layer 8 located on the ridge substrate RS.
  • the nitride semiconductor layer 8 includes a first tether portion T1 located on the ridge portion RJ, a first wing portion W1 that is connected to the first tether portion T1 while floating above the first surface portion F1, and a first recess B1 that is located on the ridge portion RJ and has a shape recessed with respect to the first tether portion T1.
  • the ridge portion RJ includes a crystal portion CS that is connected to the nitride semiconductor layer 8, and a growth suppression film DF that contacts the crystal portion CS.
  • the ridge substrate RS may include a main substrate 1 having a lattice constant different from that of the nitride semiconductor layer 8, the nitride semiconductor layer 8 may include a GaN-based semiconductor, and the main substrate 1 may be a silicon substrate or a silicon carbide substrate.
  • the ridge substrate RS includes an underlayer 4 located above the main substrate 1, the underlayer 4 may include a seed region S and a first surface portion F1 (growth inhibition region DA), and a crystal portion CS may be located on the seed region S.
  • a modified region and a non-modified region are formed in the underlayer 4, the non-modified region functions as the seed region S, and the modified region functions as the growth inhibition region (non-seed region) DA.
  • the modified regions (F1 and F2) can be formed by performing a plasma treatment or the like on the underlayer 4 (e.g., an AlN layer).
  • the first wing portion W1 can be grown laterally while floating above the first surface portion F1 (growth inhibition region DA).
  • the crystal portion CS e.g., GaN-based semiconductor crystal
  • the growth inhibition film DF e.g., silicon nitride film
  • the nitride semiconductor layer 8 may include a second wing portion W2 connected to the first tether portion T1 while floating above the second surface portion F2 (growth inhibition region DA).
  • the nitride semiconductor layer 8 may include a second tether portion T2 located on the ridge portion RJ and spaced apart from the first tether portion T1, and the first wing portion W1 may be connected to the second tether portion T2. In this way, the first wing portion W1 can be held by the first and second tether portions T1 and T2, and the stability of the first wing portion W1 is increased.
  • the first tether portion T1 and the second tether portion T2 may be connected to both ends of the first wing portion W1 facing each other in the first direction X, and the first recess B1 may be located between the first tether portion T1 and the second tether portion T2.

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PCT/JP2023/044088 2022-12-09 2023-12-08 半導体基板、半導体基板の製造方法および製造装置、並びに半導体デバイスの製造方法および製造装置 Ceased WO2024122644A1 (ja)

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