WO2022224902A1 - 半導体基板並びにその製造方法および製造装置、半導体デバイス並びにその製造方法および製造装置、電子機器 - Google Patents
半導体基板並びにその製造方法および製造装置、半導体デバイス並びにその製造方法および製造装置、電子機器 Download PDFInfo
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- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
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- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Definitions
- the present invention relates to semiconductor substrates and the like.
- Patent Document 1 discloses a method of forming a floating semiconductor device layer (including an active layer) above a main substrate such as a silicon substrate using an ELO (Epitaxial Lateral Overgrowth) method.
- ELO Epiaxial Lateral Overgrowth
- a semiconductor substrate includes a main substrate, a seed portion positioned above the main substrate, and first and second semiconductor portions arranged in a first direction, wherein the first and second semiconductor portions are arranged in a first direction. is in contact with the seed portion, the seed portion has the first direction as its longitudinal direction, and a hollow portion is located between the main substrate and the first and second semiconductor portions.
- FIG. 4 is a flow chart showing an example of a method for manufacturing a semiconductor substrate according to the present embodiment
- 1 is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to an embodiment
- FIG. It is a flow chart which shows an example of a manufacturing method of a semiconductor device concerning this embodiment.
- 1 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to an embodiment
- FIG. 1 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to an embodiment
- FIG. 1 is a plan view showing the configuration of a semiconductor substrate according to Example 1;
- FIG. FIG. 10 is a cross-sectional view taken along line cc of FIG. 9;
- FIG. 10 is a cross-sectional view taken along line dd in FIG. 9;
- FIG. 10 is a plan view showing a step of dividing the semiconductor device into individual pieces in Example 1;
- FIG. 4 is a cross-sectional view showing a step of dividing the semiconductor device into individual pieces in Example 1;
- 4 is a cross-sectional view showing another configuration of the semiconductor substrate according to Example 1;
- FIG. 4 is a cross-sectional view showing another configuration of the semiconductor substrate according to Example 1;
- FIG. 10 is a plan view showing the configuration of a semiconductor substrate according to Example 1;
- FIG. 10 is a cross-sectional view taken along line cc of FIG. 9;
- FIG. 10 is a cross-sectional view taken along line dd in FIG. 9;
- FIG. 10 is
- FIG. 4 is a plan view showing another configuration of the semiconductor substrate according to Example 1.
- FIG. 4 is a flow chart showing a method for manufacturing a template substrate in Example 1.
- FIG. 17 is a cross-sectional view showing the manufacturing method of FIG. 16; 5 is a flow chart showing another method for manufacturing the template substrate in Example 1.
- FIG. 19 is a cross-sectional view showing the manufacturing method of FIG. 18; 4 is a flow chart showing a method for manufacturing a semiconductor substrate in Example 1.
- FIG. 21 is a cross-sectional view showing the manufacturing method of FIG. 20;
- FIG. 4 is a plan view showing another configuration of the semiconductor substrate according to Example 1.
- FIG. 4 is a plan view showing another configuration of the semiconductor substrate according to Example 1.
- FIG. 10 is a cross-sectional view showing another method of manufacturing the semiconductor substrate in Example 1;
- FIG. 10 is a plan view showing the configuration of a semiconductor substrate according to Example 2;
- FIG. 10 is a cross-sectional view showing the configuration of a semiconductor substrate according to Example 2;
- FIG. 10 is a cross-sectional view showing the configuration of a semiconductor substrate according to Example 2;
- FIG. 11 is a schematic cross-sectional view showing the configuration of Example 4;
- FIG. 12 is a cross-sectional view showing an example of application of the fourth embodiment to an electronic device;
- FIG. 11 is a schematic cross-sectional view showing the configuration of Example 5;
- FIG. 11 is a plan view showing a semiconductor substrate of Example 6;
- 10 is a cross section showing a semiconductor substrate of Example 6.
- FIG. 10 is a plan view showing the configuration of a semiconductor substrate according to Example 2;
- FIG. 10 is a cross-sectional view showing the configuration of a semiconductor substrate according to Example 2;
- FIG. 1 is a plan view showing the configuration of first and second semiconductor portions of a semiconductor substrate according to this embodiment.
- 2A and 2B are cross-sectional views showing the configuration of the semiconductor substrate according to this embodiment.
- the semiconductor substrate 10 semiconductor wafer according to the present embodiment includes a main substrate 1, a seed portion SD positioned above the main substrate 1, and a first direction ( Y direction), the first semiconductor portion 8F and the second semiconductor portion 8S are in contact with the seed portion SD.
- the seed part SD has the Y direction as its longitudinal direction.
- a hollow portion (void portion) VD is located between the main substrate 1 and the first semiconductor portion 8F and the second semiconductor portion 8S.
- the first semiconductor portion 8F and the second semiconductor portion 8S may be the first semiconductor layer 8F and the second semiconductor layer 8S formed in layers.
- a convex portion 1Q protruding upward is provided on the upper surface 1f of the main substrate, and the seed portion SD is positioned on the convex portion 1Q.
- a mask pattern 6 having an opening K and a mask portion 5 is provided above the main substrate 1.
- a hollow portion VD is positioned between it and the mask portion 5 .
- the first semiconductor portion 8F includes a first floating portion P1 facing the main substrate 1 via the hollow portion VD, and the second semiconductor portion 8S includes a second floating portion facing the main substrate 1 via the hollow portion VD. Including P2, the first floating portion P1 and the second floating portion P2 are separated.
- the first semiconductor part 8F includes a third floating part P3 that forms a pair with the first floating part P1, and the first floating part P1 and the third floating part P3 are in a floating state (there is no supporting member on the lower side, a hollow space). are arranged in a second direction (X direction) orthogonal to the first direction (Y direction) in a state of contacting the portion).
- the second semiconductor portion 8S includes a fourth floating portion P4 paired with the second floating portion P2, and the second floating portion P2 and the fourth floating portion P4 are arranged in the X direction in a floating state.
- the first semiconductor portion 8F includes a first base portion BF located on the seed portion SD, the first base portion BF being located between the first and third floating portions P1 and P3, It is connected to the floating portions P1 and P3.
- the second semiconductor portion 8S includes a second base portion BS located on the seed portion SD, the second base portion BS being located between the second and fourth floating portions P2 and P4, and the second and fourth floating portions P2 and P4. It is connected to the floating portions P2 and P4.
- the first floating portion P1 includes a tether portion T1 connected to the first base portion BF and a body portion H1 connected to the tether portion T1, and the tether portion T1 has a smaller length in the Y direction than the body portion H1.
- the third floating portion P3 includes a tether portion T3 connected to the first base portion BF and a body portion H3 connected to the tether portion T3, and the tether portion T3 has a smaller length in the Y direction than the body portion H3.
- the configuration of the tether portion T1 is not limited to this.
- the tether portion T1 may have the same length in the Y direction as the body portion H1, and may have a smaller thickness (size in the Z direction) than the body portion H1.
- the tether portion T1 may have a configuration in which the length in the Y direction is smaller than the body portion H1 and the thickness is also smaller than the body portion H1.
- the semiconductor substrate 10 includes a third conductor portion 8T located on the seed portion SD, and the first base portion BF and the second base portion BS are connected via the third semiconductor portion 8T.
- the third conductor portion 8T is formed in a layered shape, and may be hereinafter referred to as the third conductor layer 8T.
- a semiconductor substrate means a substrate including a semiconductor portion, and the main substrate 1 may be a semiconductor or may be a non-semiconductor.
- the main substrate 1, the mask pattern 6, and the layered first seed portion S1 may be collectively referred to as a template substrate 7 in some cases.
- the first and second semiconductor portions 8F and 8S contain nitride semiconductors.
- a GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and examples thereof include GaN, AlGaN, AlGaInN, and InGaN.
- the first and second semiconductor portions 8F and 8S may be of a doped type (for example, n-type containing donors) or non-doped type.
- the first and second semiconductor portions 8F and 8S can be formed using an ELO (Epitaxial Lateral Overgrowth) method.
- ELO Epilateral Lateral Overgrowth
- a heterosubstrate having a lattice constant different from that of a GaN-based semiconductor is used as the main substrate 1
- a nitride semiconductor is used as the seed portion SD
- an inorganic compound film is used as the mask portion 5
- the second A first semiconductor portion 8F including a GaN-based semiconductor can be grown laterally (in the X direction) from one base portion BF to above (in the air) the mask portion 5 .
- the thickness direction (Z direction) of the first semiconductor part 8F is the ⁇ 0001> direction (c-axis direction) of the GaN-based crystal
- the longitudinal direction (first direction, Y direction) is the ⁇ 1-100> direction (m-axis direction) of the GaN-based crystal
- the width direction (second direction, X direction) of the seed part SD and the opening K is the ⁇ 11-20> direction of the GaN-based crystal ( a-axis direction).
- a layer formed by the ELO method (including the first and second semiconductor portions 8F, 8S, etc.) is sometimes referred to as an ELO semiconductor portion 8. As shown in FIG.
- the first semiconductor portion 8F formed by the ELO method overlaps the mask portion 5 in plan view, and has a low dislocation portion (first floating portion P1) with relatively few threading dislocations and a seed SD of the opening K in plan view. and includes a first base portion BF having relatively more threading dislocations than the low dislocation portion.
- the low dislocation portion may have a structure in which the non-threading dislocation density is higher than the threading dislocation density.
- Threading dislocations are dislocations (defects) extending from the lower surface or inside of the first semiconductor portion 8F to the surface or surface layer along the thickness direction (Z direction) of the first semiconductor portion 8F. Threading dislocations can be observed by performing CL (Cathode Luminescence) measurement on the surface layer (parallel to the c-plane) of the first semiconductor portion 8F.
- Non-threading dislocations are dislocations that are CL-measured in a cross section along a plane (eg, m-plane) parallel to the thickness direction, and are mainly basal plane (c-plane) dislocations.
- a layered functional portion 9 is provided at least on the first and second semiconductor portions 8F and 8S.
- the functional layer 9 (hereinafter also simply referred to as functional layer) may be a single layer or a laminate.
- the functional layer 9 has a function as a component of a semiconductor device, a protection function from external forces, a protection function from static electricity, a protection function to prevent foreign substances such as water and oxygen from entering, a protection function from etchants and the like, an optical function, and It may have at least one sensing function.
- the functional layer 9 may also be formed on the side surfaces (end surfaces) of the first and second semiconductor portions 8F and 8S.
- the first floating portion P1 of the first semiconductor portion 8F is in contact with the hollow portion VD (not in contact with the seed portion SD), and the second semiconductor portion 8S is Since the second floating portion P2 in contact with the hollow portion VD (not in contact with the seed portion SD) is separated from the semiconductor substrate 10, the singulation process for obtaining semiconductor devices including the body portions H1 and H3 is facilitated. is.
- the tether portion T1 may be broken.
- the body portion H1 is floating from the main substrate 1, stress from the main substrate 1 is relieved, and cracks and defects occurring in the body portion H1 are reduced.
- the body portion H1 becomes a low dislocation portion and has a low dislocation in plan view.
- An active region eg, light emitting region
- the threading dislocation density of the low dislocation portion is, for example, 5 ⁇ 10 6 pieces/cm 2 or less, and the size of the main portion H1 in the X direction can be 10 ⁇ m or more.
- the main body portion H1, the tether portion T1, and the like can be formed by a simple process such as etching after forming the ELO semiconductor portion.
- FIG. 3 is a plan view showing an example of the method for manufacturing a semiconductor substrate according to this embodiment.
- FIG. 4 is a flow chart showing an example of a method for manufacturing a semiconductor substrate according to this embodiment.
- the ELO semiconductor portion (air bridge structure) 8 which is not in contact with the mask pattern 6 is formed on the template substrate 7.
- the ELO semiconductor portion 8 is patterned (eg, etched) using a photolithographic method to form the first and second semiconductor portions 8F and 8S.
- the first floating portion P1 including the body portion H1, the tether portion T1, etc., and the second floating portion P2 separated from the first floating portion P1 can be formed.
- the step of forming the functional layer 9 can be performed.
- FIG. 5 is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to this embodiment.
- a semiconductor substrate manufacturing apparatus 70 shown in FIG. and The semiconductor portion forming portion 72 forms the ELO semiconductor portion 8 that does not come into contact with the mask pattern 6, and then patterns the ELO semiconductor portion 8 using, for example, a photolithography method to form the first and second semiconductor portions 8F and 8F. 8S is performed.
- the configuration may be such that the semiconductor substrate manufacturing apparatus 70 forms the functional layer 9 .
- the semiconductor portion forming section 72 may include an MOCVD apparatus and a patterning apparatus, and the control section 74 may include a processor and memory.
- the control section 74 may be configured to control the semiconductor section forming section 72 by executing a program stored, for example, in an internal memory, a communicable communication device, or an accessible network. A storage medium or the like in which the data is stored is also included in this embodiment.
- FIG. 6 is a flow chart showing an example of a method for manufacturing a semiconductor device according to this embodiment.
- the tether portion T1 and the like are broken to separate the body portion H1 and the like from the semiconductor substrate 10, and the step of obtaining the semiconductor device is performed.
- FIG. 7 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to this embodiment.
- a semiconductor device manufacturing apparatus 80 of FIG. 7 includes a semiconductor device generation unit 82 and a control unit 84 that controls the semiconductor device generation unit 82 .
- the semiconductor device production unit 82 separates the main body part HT from the semiconductor substrate 10 by breaking the tether part T1, and performs a step of obtaining a semiconductor device.
- the configuration may be such that the semiconductor device manufacturing apparatus 80 forms the functional layer 9 .
- the body portion H1 separated from the semiconductor substrate 10 can function as a semiconductor device.
- semiconductor devices include light emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, transistors (including power transistors and high electron mobility transistors), and the like.
- FIG. 8 is a schematic diagram showing the configuration of the electronic device according to this embodiment.
- An electronic device 30 of FIG. 8 includes a semiconductor device 20 including a main body H1, a drive board 23 on which the semiconductor device 20 is mounted, and a control circuit 25 that controls the drive board 23 .
- Examples of the electronic device 30 include a display device, a laser emitting device (including a Fabry-Perot type and a surface emitting type), a lighting device, a communication device, an information processing device, a sensing device, a power control device, and the like.
- Example 1 (overall structure) 9 is a plan view showing the configuration of the semiconductor substrate according to the first embodiment.
- FIG. 10 is a cross-sectional view taken along line cc of FIG. 9.
- FIG. 11 is a cross-sectional view taken along line dd in FIG. 9.
- the semiconductor substrate 10 according to Example 1 includes a main substrate 1, a seed portion SD located above the main substrate 1, a first semiconductor portion 8F and a first semiconductor portion 8F arranged in the Y direction.
- the first semiconductor portion 8F and the second semiconductor portion 8S are in contact with the seed portion SD, and a hollow portion is provided between the main substrate 1 and the first semiconductor portion 8F and the second semiconductor portion 8S.
- VD is located.
- the first semiconductor portion 8F includes a first floating portion P1 in contact with the hollow portion VD, and the second semiconductor portion 8S includes a second floating portion P2 in contact with the hollow portion VD. P2 are separated.
- the first semiconductor portion 8F includes a third floating portion P3 paired with the first floating portion P1, and the first floating portion P1 and the third floating portion P3 are arranged in the X direction in a floating state.
- the first semiconductor portion 8F includes a first base portion BF located on the seed portion SD, the first base portion BF being located between the first and third floating portions P1 and P3, It is connected to the floating portions P1 and P3.
- Example 1 the length of the first floating portion P1 in the X direction is greater than the thickness of the first floating portion P1.
- a convex portion 1Q protruding upward is provided on the upper surface 1F of the main substrate, the seed portion SD is positioned on the convex portion 1Q, and the length of the first floating portion P1 in the X direction is greater than the height of the convex portion 1Q.
- the first floating portion P1 includes a tether portion T1 connected to the first base portion BF and a body portion H1 connected to the tether portion T1, and the tether portion T1 has a smaller length in the Y direction than the body portion H1. .
- the semiconductor substrate 10 includes a functional layer 9 overlapping the first floating portion P1 in plan view.
- the functional layer 9 overlaps the main body portion H1 and the tether portion T1 in plan view.
- the length of the tether portion T1 in the Y direction is greater than the thickness of the tether portion T1.
- the length of the tether portion T1 in the Y direction is less than half the length of the main body portion H1 in the Y direction.
- the structure is not limited to the structure in which the functional layer 9 overlaps the main body portion H1 and the tether portion T1 in plan view.
- a configuration in which the functional layer 9 does not overlap the tether portion T1 in plan view that is, a configuration in which the functional layer 9 is laminated on the main body portion H1 and not laminated on the tether portion T1 may be employed. In this way, the tether portion T1 is easily broken during singulation.
- the semiconductor substrate 10 includes a mask pattern 6 having an opening K and a mask portion 5 (selective growth mask) above the main substrate 1, and the opening K and the seed portion SD overlap in plan view.
- a hollow portion VD is positioned between the first semiconductor portion 8F and the mask portion 5 .
- the mask portion 5 covers the end surface of the seed portion SD. That is, the upper surface of the seed portion SD is in contact with the first base portion BF, the lower surface of the seed portion SD is in contact with the upper surface (the convex portion 1Q) of the main substrate 1, and the end surface (side surface) is covered with the mask portion 5. Therefore, the semiconductor portion 8F does not contact the end surface of the seed portion SD.
- FIG. 12 is a plan view showing a semiconductor device singulation process in Example 1.
- FIG. 13A and 13B are cross-sectional views showing a step of dividing the semiconductor device into individual pieces in Example 1.
- FIG. As shown in FIGS. 12 and 13, for example, by breaking the tethers T1 and T3, the main body H1 of the first floating part P1 and the main body H3 of the third floating part P3 are separated from the semiconductor substrate 10, A semiconductor device 20 can be obtained.
- a portion Tf of the tether T1 may remain on one side surface of the semiconductor device 20, and an anchor film 9a (described later) may remain on the other side surface.
- pressure may be applied from above (downward) to the functional layer 9 (pushing), or the tethers T1 and T3 may be broken by laser.
- the semiconductor substrate 10 may be broken by temperature control.
- a Peltier element may be used to lower the temperature of the semiconductor substrate 10 with the adhesive tape attached.
- the adhesive tape which generally has a larger coefficient of thermal expansion than the semiconductor, shrinks greatly, and stress is applied to the tether portions T1 and T3.
- a supporting substrate may be bonded onto the semiconductor substrate 10, and an upward force may be mechanically applied to the tethers T1 and T3 to break them.
- a heterosubstrate having a lattice constant different from that of the GaN-based semiconductor can be used for the main substrate 1 .
- hetero-substrates include single-crystal silicon (Si) substrates, sapphire (Al 2 O 3 ) substrates, silicon carbide (SiC) substrates, and the like.
- the plane orientation of the main substrate 1 is, for example, the (111) plane of a silicon substrate, the (0001) plane of a sapphire substrate, and the 6H—SiC (0001) plane of a SiC substrate. These are just examples, and any main substrate and plane orientation on which the ELO semiconductor portion can be grown may be used.
- the seed part SD is a growth starting point of the ELO semiconductor part, and can be made of nitride semiconductor (GaN-based semiconductor, AlN, InAlN, InN, etc.), silicon carbide (SiC), or the like.
- nitride semiconductor GaN-based semiconductor, AlN, InAlN, InN, etc.
- silicon carbide SiC
- AlN aluminum nitride
- AlN aluminum nitride
- a GaN-based semiconductor locally formed on the convex portion of the main substrate 1, which is a silicon carbide substrate, can be used as the seed portion SD.
- FIG. 14A is a cross-sectional view showing another configuration of the semiconductor substrate according to Example 1.
- a seed portion SD of a GaN-based semiconductor may be locally formed on the convex portion of the main substrate 1, which is a silicon substrate, via a buffer portion 2B (for example, AlN).
- a buffer portion 2B for example, AlN
- the two the silicon substrate and the GaN-based semiconductor
- the buffer portion 2B whose lattice constant is close to that of the GaN-based semiconductor, it is expected that the crystallinity of the seed portion SD will be improved.
- the buffer portion 2B may be used as the buffer portion 2B. This improves the crystallinity of the seed part SD (for example, GaN-based semiconductor).
- the seed portion SD and the buffer portion 2B may be formed by a method other than the MOCVD method, such as a sputtering method. By doing so, it is possible to reduce consumables costs, reduce depreciation costs, and increase productivity.
- 14B is a cross-sectional view showing another configuration of the semiconductor substrate according to Example 1.
- FIG. 14B a seed portion SD may be provided on part of the upper surface of the convex portion 1Q.
- the mask pattern 6 has a mask portion 5 and an opening K through which the seed portion SD is exposed.
- a configuration in which the openings K are a plurality of slits extending in the Y direction and the mask portion 5 is positioned between the adjacent openings K may also be used.
- FIG. 15 is a plan view showing another configuration of the semiconductor substrate according to Example 1.
- the opening K and the seed portion SD may be separated in the Y direction. That is, a plurality of seed portions SD having the Y direction as the longitudinal direction are arranged in the Y direction. In this way, a plurality of ELO semiconductor parts are formed in the Y direction, and the stress generated between the main substrate 1 and mainly the first semiconductor part 8F can be relieved.
- the mask part 5 and the opening K refer to a part with and without a mask body, and it does not matter whether the mask part 5 is layered.
- the mask pattern 6 may be a mask layer. Moreover, the entire opening K may not be surrounded by the mask portion 5 .
- a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal having a high melting point (for example, 1000° C. or higher) are used.
- a single layer membrane comprising either one of the membranes, or a laminate comprising at least two of these membranes can be used.
- a small amount of the silicon oxide film decomposes and evaporates during the film formation of the ELO semiconductor portion, and may be incorporated into the ELO semiconductor portion.
- the silicon nitride film and the silicon oxynitride film are difficult to decompose and evaporate at high temperatures.
- the mask portion 5 may be a single layer film of a silicon nitride film or a silicon oxynitride film, may be a laminated film formed by forming a silicon oxide film and a silicon nitride film in this order, or may be a silicon nitride film and a silicon oxide film. may be formed in this order, or a laminated film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order.
- FIG. 16 is a flow chart showing a method of manufacturing a template substrate in Example 1.
- FIG. 17A and 17B are cross-sectional views showing the manufacturing method of FIG. 16 and 17, a step of forming a seed layer SL and a sacrificial film ZF (for example, photoresist) on the main substrate 1 in this order, and patterning the seed layer SL using the patterned sacrificial film ZF as a mask pattern.
- a seed layer SL and a sacrificial film ZF for example, photoresist
- the mask portion 5 is configured to cover the end surface (side surface) of the seed portion SD.
- FIG. 18 is a flow chart showing another method for manufacturing the template substrate in Example 1.
- FIG. 19A and 19B are cross-sectional views showing the manufacturing method of FIG. 18 and 19, a step of forming a seed layer SL and a sacrificial film ZF (a silicon oxide film or a resist film) in this order on the main substrate 1 which is a silicon substrate or a silicon carbide substrate; a step of patterning the sacrificial film ZF; a step of etching the surface of the main substrate 1 using the sacrificial film ZF as a mask pattern to form the projections 1Q; a step of etching (removing) the sacrificial film ZF; is subjected to substrate processing (thermal oxidation or nitridation), and a mask portion 5 and an opening K which are substrate processing films (silicon thermal oxide film, silicon nitride film, or silicon oxynitride film) are formed.
- the substrate processing film has excellent film quality and is suitable for a selective growth
- the thickness of the mask pattern 6 is, for example, approximately 100 nm to 4 ⁇ m (preferably approximately 150 nm to 2 ⁇ m), and the width of the opening K is approximately 0.1 ⁇ m to 20 ⁇ m.
- the number of threading dislocations propagating from each opening K to the ELO semiconductor portion 8 decreases as the width of the opening K decreases.
- the area of the main body (H1, etc.), which is a low-dislocation portion, can be increased.
- Example 1 (Film formation of ELO semiconductor part)
- the ELO semiconductor portion (including 8F/8S/8T) was a GaN layer
- the ELO film was formed on the template substrate 7 using an MOCVD (Metal Organic Chemical Vapor Deposition) apparatus.
- MOCVD Metal Organic Chemical Vapor Deposition
- substrate temperature 1120° C.
- growth pressure 50 kPa
- TMG trimethylgallium
- NH 3 15 slm
- V/III 6000 supply ratio
- the ELO semiconductor portion is selectively grown on the seed portion SD, and subsequently laterally grown above the mask portion 5 (in the air). Then, the lateral growth was stopped before the ELO semiconductor portions growing laterally from both sides above the mask portion 5 joined together.
- the method for increasing the film formation rate in the lateral direction is as follows. First, a vertical growth layer growing in the Z direction (c-axis direction) is formed on the seed portion SD, and then a lateral growth layer growing in the X direction (a-axis direction) is formed. For vertical growth, the growth temperature is lowered to 1050° C., for example. At this time, by setting the thickness of the vertical growth layer to 10 ⁇ m or less, preferably 5 ⁇ m or less, and more preferably 3 ⁇ m or less, the thickness of the horizontal growth layer can be kept low and the horizontal film formation rate can be increased.
- a temperature of 1150°C or less is preferable to a temperature exceeding 1200°C. It is possible to form the ELO semiconductor portion 8 even at a low temperature below 1000° C., which is preferable from the viewpoint of suppressing decomposition of the mask portion 5 .
- TEG triethylgallium
- the crystal growth of the ELO method includes a hydride vapor phase epitaxy (HVPE) method, a molecular beam epitaxy (MBE) method, and the like. can be used.
- HVPE hydride vapor phase epitaxy
- MBE molecular beam epitaxy
- the functional layer 9 located on the first and second semiconductor portions 8F and 8S includes a layered device portion 9d (hereinafter also simply referred to as a device layer) and an insulating film 9p (passivation film) located above the device layer 9d. ), and first and second electrodes E1 and E2 located above the insulating film 9p.
- the body portion H1 and the functional layer 9 may be configured to function as a semiconductor device such as a light emitting diode or a semiconductor laser.
- the device layer 9d, the insulating film 9p, and the first and second electrodes E1 and E2 do not overlap the tether portion T1.
- the device layer 9d is, for example, a laminate of an n-type semiconductor portion (eg, GaN-based), a non-doped semiconductor portion (eg, GaN-based), and a p-type semiconductor portion (eg, GaN-based). (a layer in which electrons and holes combine).
- the device layer 9d may be formed by any method.
- An inorganic film such as silicon oxide or silicon nitride can be used for the insulating film 9p.
- One of the first and second electrodes E1 and E2 can be an anode and the other can be a cathode.
- the area of the first electrode E1 can also be made larger than the area of the second electrode E2.
- the first and second electrodes E1 and E2 are provided on the device layer 9d, but the present invention is not limited to this.
- only the first electrode E1 may be provided on the device layer 9d.
- FIG. 20 is a flow chart showing a method for manufacturing a semiconductor substrate in Example 1.
- FIG. 21A to 21C are cross-sectional views showing the manufacturing method of FIG. As shown in FIGS. 9, 20 and 21, a step of forming an ELO semiconductor portion 8 on a template substrate 7, a step of forming a device layer 9d on the ELO semiconductor portion 8, and a step of forming, for example, a A step of forming the insulating film 9p by the PECVD method, a step of patterning the insulating film 9p, a step of forming the first and second electrodes E1 and E2, and dry etching (for example, reactive ion etching) of the ELO semiconductor portion 8.
- dry etching for example, reactive ion etching
- the ELO semiconductor portion 8 may be etched by dry ECR (electron cyclotron resonance) etching, CAIB (chemically assisted ion beam) etching, or wet PEC (photoelectrochemical) etching.
- the insulating film 9p is a passivation film (for example, a silicon oxide film or a silicon nitride film) formed above the device layer 9d, and overlaps the main body portion H1 in plan view, but does not overlap the tether portion T1. By doing so, it is possible to avoid the problem that the insulating film 9p hinders the breakage of the tether portion T1. Further, as shown in FIG. 13, a portion of the insulating film 9p (for example, a portion covering the central portion of the end surface of H1 of the main body and reaching the mask portion 5 on the main substrate) functions as an anchor film 9a. In this way, the main body portion H1 is stabilized, and when the tether portion T1 is broken, the anchor film 9a can be broken at the same time.
- a passivation film for example, a silicon oxide film or a silicon nitride film
- the ELO semiconductor portions growing laterally from both sides above the mask portion 5 are brought together, and when the ELO semiconductor portion 8 is etched, the meeting portion (high dislocation portion) is formed. ) may be removed.
- FIG. 22 is a plan view showing another configuration of the semiconductor substrate according to Example 1.
- the first floating portion P1 may include a plurality of tether portions T1 and T5, and the body portion H1 may be connected to the first base portion BF via the plurality of tether portions T1 and T5.
- the main body H1 is stabilized.
- FIG. 23 is a plan view showing another configuration of the semiconductor substrate according to Example 1.
- the tether portion T1 of the first floating portion P1 may have a notch NC.
- the side surface of the notch NC can be configured to form an angle of 60° with respect to the X direction.
- Such a notch NC can be formed, for example, by providing a semicircular notch when forming the tether, and then immersing it in TMAH (tetramethylammonium hydroxide) to expose the m-plane of the GaN-based semiconductor. .
- TMAH tetramethylammonium hydroxide
- FIG. 24 is a cross-sectional view showing another manufacturing method of the semiconductor substrate in Example 1.
- the main substrate 1 is provided with the convex portion 1Q, but the present invention is not limited to this.
- a main substrate 1 for example, a silicon substrate
- a planar buffer layer 2 for example, AlN
- a local seed portion SD for example, a GaN-based semiconductor having a longitudinal direction in the Y direction are provided.
- an ELO semiconductor portion including the first semiconductor portion 8F
- the mask portion 5 may be removed by etching (for example, wet etching).
- the first semiconductor portion 8F can be floated (a state in which the lower surface is in contact with the hollow portion VD).
- the mask portion 5 may be removed before the functional layer 9 is formed.
- FIG. 25 is a plan view showing the configuration of a semiconductor substrate according to Example 2.
- FIG. 26 and 27 are cross-sectional views showing the configuration of a semiconductor substrate according to Example 2.
- the ELO semiconductor portions growing laterally from both sides above the mask portion 5 may be combined.
- the first semiconductor portion 8F includes a first floating portion P1 facing the main substrate 1 through the hollow portion VD, and the second semiconductor portion 8S is formed through the hollow portion VD. It includes a second floating portion P2 facing the main substrate 1, and the first floating portion P1 and the second floating portion P2 are separated.
- the first semiconductor portion 8F includes a third floating portion P3 paired with the first floating portion P1, and the first floating portion P1 and the third floating portion P3 are arranged in the X direction in a floating state.
- the first semiconductor portion 8F includes a first base portion BF located on the seed portion SD, the first base portion BF being located between the first and third floating portions P1 and P3, It is connected to the floating portions P1 and P3.
- the first floating portion P1 includes a tether portion T1 connected to the first base portion BF and a body portion H1 connected to the tether portion T1, and the tether portion T1 has a smaller length in the Y direction than the body portion H1. .
- the semiconductor substrate 10 includes a mask pattern 6 having an opening K and a mask portion 5 (selective growth mask) above the main substrate 1, and the opening K and the seed portion SD overlap in plan view.
- a hollow portion VD is positioned between the first semiconductor portion 8F and the mask portion 5 .
- the mask portion 5 covers the end surface of the seed portion SD. That is, the upper surface of the seed portion SD is in contact with the first base portion BF, the lower surface of the seed portion SD is in contact with the upper surface (the convex portion 1Q) of the main substrate 1, and the end surface (side surface) is covered with the mask portion 5. Therefore, the semiconductor portion 8F does not contact the end surface of the seed portion SD.
- the functional layer 9 formed on the semiconductor portion 8 includes a device layer 9d, an insulating film 9p (passivation film) positioned above the device layer 9d, and first and second layers positioned above the insulating film 9p. and electrodes E1 and E2.
- Example 3 In Examples 1 and 2, the ELO semiconductor portion is a GaN layer, but the present invention is not limited to this.
- an InGaN layer which is a GaN-based semiconductor portion, can be formed as the first and second semiconductor portions 8F and 8S (ELO semiconductor portions). Lateral deposition of the InGaN layer is performed at low temperatures, eg, below 1000.degree. This is because, at high temperatures, the vapor pressure of indium increases and it is not effectively incorporated into the film. Lowering the film formation temperature has the effect of reducing the mutual reaction between the mask portion 5 and the InGaN layer. In addition, the InGaN layer has the effect of being less reactive with the mask portion 5 than the GaN layer.
- TAG triethylgallium
- FIG. 28 is a schematic cross-sectional view showing the configuration of Example 4.
- the semiconductor device 20 functioning as an LED (light emitting diode) is configured by the main body H1 and the device layer 9d.
- the main body H1 for example, a GaN-based semiconductor
- the device layer 9d includes an active layer 34, an electron blocking layer 35, and a GaN-based p-type semiconductor portion 36 in order from the lower layer side.
- the active layer 34 is an MQW (Multi-Quantum Well) and includes an InGaN layer and a GaN layer.
- the electron blocking layer 35 is, for example, an AlGaN layer.
- the GaN-based p-type semiconductor portion 36 is, for example, a GaN layer.
- the anode 38 (for example, first electrode E1) is arranged so as to be in contact with the GaN-based p-type semiconductor portion 36, and the cathode 39 (for example, second electrode E2) is arranged so as to be in contact with main body portion H1. .
- FIG. 29 is a cross-sectional view showing an example of application of the fourth embodiment to electronic equipment.
- a red micro-LED 20R, a green micro-LED 20G, and a blue micro-LED 20B can be obtained, and by mounting these on a drive substrate (TFT substrate) 23, a micro LED display 30D (electronic device) can be configured. can be done.
- a red micro-LED 20R, a green micro-LED 20G, and a blue micro-LED 20B are mounted on a plurality of pixel circuits 27 of the driving substrate 23 via a conductive resin 24 (for example, an anisotropic conductive resin) or the like, and then mounted on the driving substrate 23.
- a control circuit 25, a driver circuit 29, and the like are mounted.
- a portion of the driver circuit 29 may be included in the drive substrate 23 .
- Example 5 is a schematic cross-sectional view showing the configuration of Example 5.
- the semiconductor device 20 functioning as a semiconductor laser is configured by the main body portion H1 and the device layer 9d.
- the device layer 9d includes, from the lower layer side, an n-type cladding layer 41, an n-type optical guide layer 42, an active layer 43, an electron blocking layer 44, a p-type optical guide layer 45, a p-type cladding layer 46, and a GaN-based p-type layer.
- a semiconductor portion 47 is included.
- An InGaN layer can be used for each of the optical guide layers 42 and 45 .
- a GaN layer or an AlGaN layer can be used for each of the clad layers 41 and 46 .
- the anode 48 is arranged so as to be in contact with the GaN-based p-type semiconductor portion 47 , and the body portion H ⁇ b>1 is mounted on the n-pad 49 of the mounting substrate 53 .
- FIG. 31 is a plan view showing a semiconductor substrate of Example 6.
- FIG. FIG. 32 is a cross section showing a semiconductor substrate of Example 6.
- the semiconductor substrate 10 of Example 6 includes a template substrate 7 including first and second seed regions J1 and J2 and a growth suppression region (deposition suppression region) SP on the upper surface, and a template substrate 7 having a structure extending from the first seed region J1 to the growth suppression region SP.
- the first and second semiconductor portions 8F and 8S are adjacent to each other in the first direction (Y direction) with a gap G1 therebetween.
- the Y direction may be the m-axis direction of the first and second semiconductor portions 8F and 8S containing nitride semiconductors.
- the first and second seed regions J1 and J2 may be positioned above the growth suppression region SP.
- the first and second seed regions J1 and J2 may have a shape whose longitudinal direction is the Y direction. Both ends of the first and second semiconductor portions 8F and 8S may be tapered in the Y-axis direction. A fourth semiconductor portion 8U may be arranged adjacent to the first semiconductor portion 8F in the X direction with a gap G2 therebetween.
- the X direction may be the a-axis direction of the first and second semiconductor portions 8F and 8U containing nitride semiconductors.
- the semiconductor substrate 10 has the advantage of being resistant to warping.
- the first and second seed regions J1 and J2 may be regions of the upper surface of the seed portion that overlap with the openings of the mask pattern, and the growth suppression region SP may be the upper surface of the mask portion.
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Abstract
Description
図1は、本実施形態に係る半導体基板の第1および第2半導体部の構成を示す平面図である。図2Aおよび図2Bは、本実施形態に係る半導体基板の構成を示す断面図である。本実施形態に係る半導体基板10(半導体ウエハー)は、図1、図2Aおよび図2Bに示すように、主基板1と、主基板1よりも上方に位置するシード部SDと、第1方向(Y方向)に並ぶ、第1半導体部8Fおよび第2半導体部8Sとを備え、第1半導体部8Fおよび第2半導体部8Sはシード部SDと接する。シード部SDは、Y方向を長手方向とする。主基板1と、第1半導体部8Fおよび第2半導体部8Sとの間に中空部(ボイド部)VDが位置する。なお、本開示において、第1半導体部8Fおよび第2半導体部8Sは、層状に形成された、第1半導体層8Fおよび第2半導体層8Sであってもよい。
図3は、本実施形態にかかる半導体基板の製造方法の一例を示す平面図である。図4は、本実施形態にかかる半導体基板の製造方法の一例を示すフローチャートである。図3および図4に示す半導体基板の製造方法では、テンプレート基板7を準備する工程の後に、テンプレート基板7上に、マスクパターン6に接しないELO半導体部(エアブリッジ構造)8を形成し、その後、ELO半導体部8をフォトリソグラフィ法を用いてパターニング(例えば、エッチング)することで、第1および第2半導体部8F・8Sとする工程を行う。この工程により、本体部H1およびテザー部T1等を含む第1フローティング部P1と、第1フローティング部P1から分離された第2フローティング部P2とを形成することができる。なお、ELO半導体部8をパターニングする工程の前あるいは後に機能層9を形成する工程を行うことができる。
図6は、本実施形態にかかる半導体デバイスの製造方法の一例を示すフローチャートである。図6の半導体デバイスの製造方法では、半導体基板10を準備する工程の後に、テザー部T1等を破断させて半導体基板10から本体部H1等を離隔し、半導体デバイスを得る工程を行う。
半導体基板10から離隔された本体部H1は、半導体デバイスとして機能させることができる。半導体デバイスの具体例として、発光ダイオード(LED)、半導体レーザ、ショットキーダイオード、フォトダイオード、トランジスタ(パワートランジスタ、高電子移動度トランジスタを含む)等を挙げることができる。
図8は、本実施形態に係る電子機器の構成を示す模式図である。図8の電子機器30は、本体部H1を含む半導体デバイス20と、半導体デバイス20が実装される駆動基板23と、駆動基板23を制御する制御回路25とを含む。
(全体構成)
図9は、実施例1に係る半導体基板の構成を示す平面図である。図10は、図9のc-c矢視断面図である。図11は、図9のd-d矢視断面図である。実施例1に係る半導体基板10は、図9~図11に示すように、主基板1と、主基板1よりも上方に位置するシード部SDと、Y方向に並ぶ、第1半導体部8Fおよび第2半導体部8Sとを備え、第1半導体部8Fおよび第2半導体部8Sは、シード部SDと接し、主基板1と、第1半導体部8Fおよび第2半導体部8Sとの間に中空部(ボイド部)VDが位置する。
主基板1には、GaN系半導体と異なる格子定数を有する異種基板を用いることができる。異種基板としては、単結晶のシリコン(Si)基板、サファイア(Al2O3)基板、シリコンカーバイド(SiC)基板等を挙げることができる。主基板1の面方位は、例えば、シリコン基板の(111)面、サファイア基板の(0001)面、SiC基板の6H-SiC(0001)面である。これらは例示であって、ELO半導体部を成長させることができる主基板および面方位であれば何でもよい。
シード部SDは、ELO半導体部の成長起点であり、窒化物半導体(GaN系半導体、AlN、InAlN、InN等)、シリコンカーバイド(SiC)等を用いることができる。例えばシリコン基板またはシリコンカーバイド基板である主基板1の凸部上に局所形成された窒化アルミニウム(AlN)をシード部SDとすることができる。また、シリコンカーバイド基板である主基板1の凸部上に局所形成されたGaN系半導体をシード部SDとすることができる。
マスクパターン6はマスク部5および開口部Kを有し、開口部Kにおいてシード部SDが露出する。開口部KがY方向に伸びる複数のスリットであり、隣り合う開口部Kの間にマスク部5が位置する構成でもよい。図15は、実施例1に係る半導体基板の別構成を示す平面図である。図15に示すように、開口部Kおよびシード部SDをY方向に区切ってもよい。すなわち、Y方向を長手方向とする複数のシード部SDがY方向に並ぶ構成とする。こうすれば、Y方向に並ぶ複数のELO半導体部が形成され、主基板1と主に第1半導体部8Fとの間で発生する応力を緩和することができる。これにより、第1半導体部8Fにおける欠陥、クラックの発生が低減する。また、主基板1の反りが低減し、主基板1の大口径化が容易になる。マスク部5と開口部Kは、マスク体がある部分とない部分という意味であり、マスク部5が層状であるかは問わない。マスクパターン6がマスク層であってもよい。また、開口部Kの全体がマスク部5に囲まれていなくてもよい。
図16は実施例1におけるテンプレート基板の製造方法を示すフローチャートである。図17は、図16の製造方法を示す断面図である。図16および図17では、主基板1上に、シード層SL、および犠牲膜ZF(例えば、フォトレジスト)をこの順に成膜する工程と、パターニングした犠牲膜ZFをマスクパターンとしてシード層SLをパターニングする工程と、犠牲膜ZFをマスクパターンとして主基板1表面をエッチングし、凸部1Qを形成する工程と、主基板1および犠牲膜ZFを覆うマスクパターン6を形成する工程(例えばスパッタリング法やPECVD法を用いる)と、リムーバーによってフォトレジストを除去しシード部SDを露出させる開口部Kおよびマスク部5を形成する工程とを行う。この場合、マスク部5が、シード部SDの端面(側面)を覆う構成となる。
実施例1では、ELO半導体部(8F・8S・8T含む)をGaN層とし、MOCVD(Metal Organic Chemical Vapor Deposition)装置を用いて前述のテンプレート基板7上にELO成膜を行った。ELO成膜条件の一例として、基板温度:1120℃、成長圧力:50kPa、TMG(トリメチルガリウム):22sccm、NH3:15slm、V/III=6000(III族原料の供給量に対する、V族原料の供給量の比)を採用することができる。
第1および第2半導体部8F・8S上に位置する機能層9は、層状のデバイス部9d(以下、単にデバイス層ともいう)と、デバイス層9dよりも上層に位置する絶縁膜9p(パッシベーション膜)と、絶縁膜9pよりも上層に位置する第1および第2電極E1・E2とを含む。本体部H1および機能層9が、発光ダイオード、半導体レーザ等の半導体デバイスとして機能する構成でもよい。
図25は、実施例2に係る半導体基板の構成を示す平面図である。図26および図27は、実施例2に係る半導体基板の構成を示す断面図である。実施例1では、マスク部5の上方においてその両側から横方向成長するELO半導体部が会合する前に横成長を停止させ、第1および第2半導体部8F・8Sが、平面視でマスク部5と重なる端面(エッジ)を有する構成としているが、これに限定されない。図25~図27に示すように、マスク部5の上方においてその両側から横方向成長するELO半導体部が会合させる構成でもよい。
実施例1・2では、ELO半導体部をGaN層としているがこれに限定されない。実施例3では、第1および第2半導体部8F・8S(ELO半導体部)として、GaN系半導体部であるInGaN層を形成することもできる。InGaN層の横方向成膜は、例えば1000℃を下回るような低温で行う。高温ではインジウムの蒸気圧が高くなり、膜中に有効に取り込まれないためである。成膜温度が低温になることで、マスク部5とInGaN層の相互反応が低減される効果がある。また、InGaN層は、GaN層よりもマスク部5との反応性が低いという効果もある。InGaN層にインジウムがIn組成レベル1%以上で取り込まれるようになると、マスク部5との反応性がさらに低下するため、望ましい。ガリウム原料ガスとしては、トリエチルガリウム(TEG)を用いることが好ましい。
図28は、実施例4の構成を示す模式的断面図である。実施例4では、本体部H1およびデバイス層9dによってLED(発光ダイオード)として機能する半導体デバイス20を構成する。本体部H1(例えば、GaN系半導体)は、例えばシリコン等がドープされたn型である。デバイス層9dは、下層側から順に、活性層34、電子ブロッキング層35、GaN系p型半導体部36を含む。活性層34は、MQW(Multi-Quantum Well)であり、InGaN層およびGaN層を含む。電子ブロッキング層35は、例えばAlGaN層である。GaN系p型半導体部36は、例えばGaN層である。アノード38(例えば、第1電極E1)は、GaN系p型半導体部36と接触するように配され、カソード39(例えば、第2電極E2)は、本体部H1と接触するように配される。
図30は、実施例5の構成を示す模式的断面図である。実施例5では、本体部H1およびデバイス層9dによって半導体レーザとして機能する半導体デバイス20を構成する。デバイス層9dは、下層側から順に、n型クラッド層41、n型光ガイド層42、活性層43、電子ブロッキング層44、p型光ガイド層45、p型クラッド層46、およびGaN系p型半導体部47を含む。各光ガイド層42・45には、InGaN層を用いることができる。各クラッド層41・46には、GaN層もしくはAlGaN層を用いることができる。アノード48はGaN系p型半導体部47と接触するように配され、本体部H1は、実装基板53のnパッド49上に実装される。
図31は実施例6の半導体基板を示す平面図である。図32は実施例6の半導体基板を示す断面である。実施例6の半導体基板10は、第1および第2シード領域J1・J2並びに成長抑制領域(堆積抑制領域)SPを上面に含むテンプレート基板7と、第1シード領域J1から成長抑制領域SPの上方に至り、成長抑制領域SPとの間に中空部VDが形成される第1半導体部8Fと、第2シード領域J2から成長抑制領域SPの上方に至り、成長抑制領域SPとの間に中空部VDが形成される第2半導体部8Sとを有し、第1および第2半導体部8F・8Sが、ギャップG1をおいて第1方向(Y方向)に隣り合っている。Y方向は、窒化物半導体を含む第1および第2半導体部8F・8Sのm軸方向であってよい。第1および第2シード領域J1・J2が、成長抑制領域SPよりも上側に位置していてもよい。
SD シード部
5 マスク部
6 マスクパターン
7 テンプレート基板
8F 第1半導体部
8S 第2半導体部
9 機能層
9d デバイス層
10 半導体基板
20 半導体デバイス
30 電子機器
70 半導体基板の製造装置
K 開口部
VD 中空部
P1 第1フローティング部
P2 第2フローティング部
P3 第3フローティング部
H1 本体部
T1 テザー部
Claims (36)
- 主基板と、前記主基板よりも上方に位置するシード部と、第1方向に並ぶ、第1半導体部および第2半導体部とを備え、
前記第1半導体部および第2半導体部は、前記シード部と接し、
前記シード部は、前記第1方向を長手方向とし、
前記主基板と、前記第1半導体部および前記第2半導体部との間に中空部が位置している、半導体基板。 - 前記第1半導体部は、前記中空部を介して前記主基板に対向した第1フローティング部を含み、
前記第2半導体部は、前記中空部を介して前記主基板に対向した第2フローティング部を含み、
前記第1フローティング部と第2フローティング部とが分離されている、請求項1に記載の半導体基板。 - 前記第1半導体部は、前記第1フローティング部と対となる第3フローティング部を含み、
前記第1フローティング部および第3フローティング部が、浮いた状態で前記第1方向と直交する第2方向に並ぶ、請求項2に記載の半導体基板。 - 前記第1半導体部は、前記シード部上に位置する第1ベース部を含み、
前記第1ベース部は、前記第1および第3フローティング部の間に位置し、前記第1および第3フローティング部に接続している、請求項3に記載の半導体基板。 - 前記第1フローティング部の前記第2方向の長さが、前記第1フローティング部の厚みよりも大きい、請求項3に記載の半導体基板。
- 前記主基板上面に、上方に突出する凸部が設けられ、
前記シード部は、前記凸部上に位置し、
前記第1フローティング部の前記第2方向の長さが、前記凸部の高さよりも大きい、請求項3に記載の半導体基板。 - 前記第1フローティング部は、前記第1ベース部に接続する、少なくとも1つのテザー部と、前記テザー部に接続する本体部とを含み、
前記テザー部は、前記本体部よりも前記第1方向の長さが小さい、請求項4に記載の半導体基板。 - 平面視で前記第1フローティング部と重なる機能部を備える請求項7に記載の半導体基板。
- 前記機能部は、デバイス部と前記デバイス部よりも上方の絶縁膜とを含む、請求項8に記載の半導体基板。
- 前記テザー部の前記第1方向の長さは、前記テザー部の厚みよりも大きい、請求項7に記載の半導体基板。
- 前記テザー部の前記第1方向の長さは、前記本体部の第1方向の長さの半分以下である、請求項7に記載の半導体基板。
- 前記テザー部に切り欠きが設けられている、請求項7に記載の半導体基板。
- 前記第1フローティング部は、前記第1ベース部に接続する複数のテザー部を含む、請求項7に記載の半導体基板。
- 前記シード部は窒化物半導体を含む、請求項1に記載の半導体基板。
- 前記シード部上に位置する第3半導体部を含み、
前記第2半導体部は、前記シード部上に位置する第2ベース部を含み、
前記第1ベース部および第2ベース部が、前記第3半導体部を介して接続されている、請求項4に記載の半導体基板。 - 前記主基板の上方に、開口部およびマスク部を有するマスクパターンを備え、
平面視において、前記開口部と前記シード部とが重なる、請求項1に記載の半導体基板。 - 前記第1半導体部および第2半導体部と、前記マスク部との間に前記中空部が位置する、請求項16に記載の半導体基板。
- 前記マスク部が、前記シード部の端面を覆う、請求項16に記載の半導体基板。
- 前記第1半導体部がGaN系半導体を含み、前記主基板が、前記GaN系半導体と格子定数が異なる異種基板である、請求項1に記載の半導体基板。
- 前記異種基板がシリコン基板または炭化ケイ素基板であり、
前記第1方向が前記GaN系半導体の<1-100>方向である、請求項19に記載の半導体基板。 - 前記第1および第2フローティング部はそれぞれ、貫通転位密度が5×106〔個/cm2〕以下の低欠陥領域を含み、
前記低欠陥領域の前記第2方向のサイズが10μm以上である、請求項3に記載の半導体基板。 - 前記機能部は、電極および活性部を含む、請求項8に記載の半導体基板。
- 前記主基板がシリコン基板であり、
前記マスク部は、前記シリコン基板に熱酸化処理あるいは窒化処理を施して得られる基板加工膜である、請求項16に記載の半導体基板。 - 前記絶縁膜は、平面視において前記本体部と重なり、かつ前記テザー部とは重ならない、請求項9に記載の半導体基板。
- 前記絶縁膜の一部は、前記本体部の側面と接触し、前記本体部を前記主基板に対して固定するアンカー膜として機能する、請求項24に記載の半導体基板。
- 請求項1に記載の半導体基板の製造方法であって、
ELO法で形成した半導体部から前記第1半導体部および第2半導体部を形成する、半導体基板の製造方法。 - 前記第1半導体部は、前記中空部を介して前記主基板に対向した第1フローティング部を含み、
前記第2半導体部は、前記中空部を介して前記主基板に対向した第2フローティング部を含み、
ELO法で形成した半導体部にエッチングを行うことで前記第1フローティング部および前記第2フローティング部を形成する、請求項26に記載の半導体基板の製造方法。 - 前記第1半導体部は、前記シード部上に位置する第1ベース部を含み、
前記エッチングにおいて、前記第1フローティング部に、前記第1ベース部に接続するテザー部と、前記テザー部に接続する本体部とを形成する、請求項27に記載の半導体基板の製造方法。 - 前記エッチングの前に、ELO法で形成した半導体部を、アンカーとして機能する絶縁膜によって支持する、請求項27に記載の半導体基板の製造方法。
- 前記主基板上面に形成された凸部に前記シード部を設けることで、前記中空部を形成する、請求項26に記載の半導体基板の製造方法。
- マスク部および開口部を含むマスクパターン上にELO法で前記半導体部を形成し、その後に前記マスク部を除去することで前記中空部を形成する、請求項26に記載の半導体基板の製造方法。
- 請求項26に記載の半導体基板の製造方法を行う、半導体基板の製造装置。
- 請求項8に記載の半導体基板を準備する工程と、
前記テザー部を破断させる工程とを含む、半導体デバイスの製造方法。 - 請求項33に記載の各工程を行う、半導体デバイスの製造装置。
- 請求項33に記載の半導体デバイスの製造方法によって得られ、前記テザー部の一部を含む半導体デバイス。
- 請求項35に記載の半導体デバイスを含む電子機器。
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CN202280028160.XA CN117121161A (zh) | 2021-04-20 | 2022-04-14 | 半导体基板和其制造方法以及制造装置、半导体器件和其制造方法以及制造装置、电子设备 |
EP22791676.4A EP4328956A1 (en) | 2021-04-20 | 2022-04-14 | Semiconductor substrate and production method and production device for same, semiconductor device and production method and production device for same, electronic apparatus |
US18/555,986 US20240203732A1 (en) | 2021-04-20 | 2022-04-14 | Semiconductor substrate, manufacturing method and manufacturing apparatus for semiconductor substrate, semiconductor device, manufacturing method and manufacturing apparatus for semiconductor device, and electronic device |
JP2023515443A JPWO2022224902A1 (ja) | 2021-04-20 | 2022-04-14 | |
KR1020237035454A KR20230157470A (ko) | 2021-04-20 | 2022-04-14 | 반도체 기판 및 그 제조 방법과 제조 장치, 반도체 디바이스 및 그 제조 방법과 제조 장치, 전자 기기 |
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JP (1) | JPWO2022224902A1 (ja) |
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WO2024122644A1 (ja) * | 2022-12-09 | 2024-06-13 | 京セラ株式会社 | 半導体基板、半導体基板の製造方法および製造装置、並びに半導体デバイスの製造方法および製造装置 |
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US20080054292A1 (en) * | 2006-08-31 | 2008-03-06 | Industrial Technology Research Institute | Nitride semiconductor substrate, method for forming a nitride semiconductor layer and method for separating the nitride semiconductor layer from the substrate |
JP2009239270A (ja) * | 2008-03-01 | 2009-10-15 | Sumitomo Chemical Co Ltd | 半導体基板、半導体基板の製造方法および電子デバイス |
JP2014150211A (ja) * | 2013-02-04 | 2014-08-21 | Pawdec:Kk | 半導体素子の製造方法、絶縁ゲート型電界効果トランジスタ、絶縁ゲート型電界効果トランジスタの製造方法、半導体発光素子の製造方法および太陽電池の製造方法 |
JP2017535051A (ja) * | 2014-09-25 | 2017-11-24 | インテル・コーポレーション | 自立シリコンメサ上のiii−nエピタキシャル素子構造 |
JP2018032863A (ja) | 2017-09-21 | 2018-03-01 | 株式会社パウデック | 絶縁ゲート型電界効果トランジスタ |
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- 2022-04-14 JP JP2023515443A patent/JPWO2022224902A1/ja active Pending
- 2022-04-14 CN CN202280028160.XA patent/CN117121161A/zh active Pending
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- 2022-04-14 KR KR1020237035454A patent/KR20230157470A/ko unknown
- 2022-04-19 TW TW111114759A patent/TWI830203B/zh active
Patent Citations (5)
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US20080054292A1 (en) * | 2006-08-31 | 2008-03-06 | Industrial Technology Research Institute | Nitride semiconductor substrate, method for forming a nitride semiconductor layer and method for separating the nitride semiconductor layer from the substrate |
JP2009239270A (ja) * | 2008-03-01 | 2009-10-15 | Sumitomo Chemical Co Ltd | 半導体基板、半導体基板の製造方法および電子デバイス |
JP2014150211A (ja) * | 2013-02-04 | 2014-08-21 | Pawdec:Kk | 半導体素子の製造方法、絶縁ゲート型電界効果トランジスタ、絶縁ゲート型電界効果トランジスタの製造方法、半導体発光素子の製造方法および太陽電池の製造方法 |
JP2017535051A (ja) * | 2014-09-25 | 2017-11-24 | インテル・コーポレーション | 自立シリコンメサ上のiii−nエピタキシャル素子構造 |
JP2018032863A (ja) | 2017-09-21 | 2018-03-01 | 株式会社パウデック | 絶縁ゲート型電界効果トランジスタ |
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WO2024122644A1 (ja) * | 2022-12-09 | 2024-06-13 | 京セラ株式会社 | 半導体基板、半導体基板の製造方法および製造装置、並びに半導体デバイスの製造方法および製造装置 |
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TWI830203B (zh) | 2024-01-21 |
TW202247264A (zh) | 2022-12-01 |
EP4328956A1 (en) | 2024-02-28 |
US20240203732A1 (en) | 2024-06-20 |
CN117121161A (zh) | 2023-11-24 |
JPWO2022224902A1 (ja) | 2022-10-27 |
KR20230157470A (ko) | 2023-11-16 |
TW202414535A (zh) | 2024-04-01 |
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