WO2022181584A1 - テンプレート基板並びにその製造方法および製造装置、半導体基板並びにその製造方法および製造装置 - Google Patents
テンプレート基板並びにその製造方法および製造装置、半導体基板並びにその製造方法および製造装置 Download PDFInfo
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
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- H01S5/021—Silicon based substrates
Definitions
- the present invention relates to template substrates and the like.
- Patent Document 1 discloses a method of forming a plurality of semiconductor portions corresponding to openings of a plurality of masks using an ELO (Epitaxial Lateral Overgrowth) method.
- JP 2011-66390 Japanese Patent Publication
- a template substrate includes a main substrate having an edge, a peripheral portion including the edge, and a non-peripheral portion positioned inside the peripheral portion, and a mask pattern positioned above the main substrate.
- the mask pattern includes a mask portion, a plurality of first openings having a first direction as a width direction and a second direction as a longitudinal direction, overlapping with the non-peripheral portion in plan view, and a plurality of first openings along the edge in plan view. and one or more second openings arranged in the .
- FIG. 2 is a plan view showing the structure of a template substrate according to the embodiment;
- FIG. 2 is a cross-sectional view (non-peripheral portion) taken along the line aa in FIG. 1;
- FIG. 2 is a cross-sectional view (periphery) taken along the line bb in FIG. 1; It is a top view which shows the structure of the semiconductor substrate which concerns on this embodiment.
- FIG. 5 is a cross-sectional view taken along the line AA of FIG. 4; 5 is a cross-sectional view taken along line cc of FIG. 4;
- FIG. FIG. 4 is a cross-sectional view showing another configuration of the semiconductor substrate according to the embodiment;
- FIG. 4 is a cross-sectional view showing another configuration of the semiconductor substrate according to the embodiment; 4 is a flow chart showing an example of a method for manufacturing a template substrate according to the present embodiment; It is a block diagram showing an example of the manufacturing apparatus of the template substrate according to the present embodiment. It is a flow chart which shows an example of a manufacturing method of a semiconductor substrate concerning this embodiment.
- 1 is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to an embodiment;
- FIG. It is a flow chart which shows an example of a manufacturing method of a semiconductor device concerning this embodiment.
- FIG. 4 is a cross-sectional view showing an example of separation and spacing of element units; It is a schematic diagram which shows the structure of the electronic device which concerns on this embodiment. It is a schematic diagram which shows another structure of the electronic device which concerns on this embodiment.
- 1 is a plan view showing the configuration of a template substrate according to Example 1.
- FIG. FIG. 18 is a cross-sectional view taken along line dd in FIG. 17; 1 is a plan view showing the configuration of a semiconductor substrate according to Example 1;
- FIG. FIG. 4 is a cross-sectional view showing an example of lateral growth of an ELO semiconductor portion; 4 is a plan view showing another configuration of the template substrate according to Example 1.
- FIG. 22 is a plan view showing a configuration of a semiconductor substrate including the template substrate of FIG.
- FIG. 4 is a plan view showing another configuration of the template substrate according to Example 1.
- FIG. 4 is a plan view showing another configuration of the template substrate according to Example 1.
- FIG. 10 is a plan view showing the configuration of a template substrate according to Example 2;
- FIG. 10 is a plan view showing the configuration of a semiconductor substrate according to Example 2;
- FIG. 11 is a plan view showing another configuration of the template substrate according to Example 2;
- FIG. 11 is a plan view showing another configuration of the template substrate according to Example 2;
- FIG. 11 is a schematic cross-sectional view showing the configuration of Example 4;
- FIG. 12 is a cross-sectional view showing an example of application of the fourth embodiment to an electronic device;
- FIG. 11 is a schematic cross-sectional view showing the configuration of Example 5;
- FIG. 12 is a cross-sectional view showing the configuration of Example 6;
- FIG. 1 is a plan view showing the structure of the template substrate according to this embodiment.
- FIG. 2 is a cross-sectional view (non-peripheral portion) taken along line aa of FIG.
- FIG. 3 is a cross-sectional view (periphery) taken along line bb in FIG.
- the template substrate 7 has an edge E (end face, side surface), a peripheral edge portion 1S including the edge E, and a non-peripheral edge portion 1P located inside the peripheral edge portion 1S.
- a substrate 1 and a mask pattern 6 (mask layer) positioned above the main substrate 1 are provided.
- Y direction) is the longitudinal direction, and has a plurality of first openings KF overlapping the non-peripheral edge portion 1P in plan view, and a plurality of second openings KB arranged along the edge E in plan view.
- the template substrate 7 can be used for forming a semiconductor portion (semiconductor layer), for example, for forming a GaN-based semiconductor portion (GaN-based semiconductor crystal) by the ELO (Epitaxial Lateral Overgrowth) method.
- the edge E (side surface, end face) of the main substrate 1 includes the curved surface Er and the flat surface Ef, but the edge E may be composed only of curved surfaces or flat surfaces.
- Each first opening KF may overlap with the non-peripheral edge portion 1P in a plan view, and may be entirely located at the non-peripheral edge portion 1P, or partially located at the peripheral edge portion 1S, The remaining portion may be located in the non-peripheral portion 1P.
- the plurality of second openings KB should be along the edge E in plan view.
- Each second opening KB may be entirely located at the non-peripheral edge portion 1P, may be entirely located at the peripheral edge portion 1S, or may be partially located at the non-peripheral edge portion 1P. , and the remaining portion may be located at the peripheral portion 1S.
- the mask pattern 6 includes a plurality of second openings KB in FIG. 1, it is not limited to this and may be one.
- the shape of the second opening KB it may be rectangular with the Y direction or X direction as its longitudinal direction, square or circular, or annular or curved longitudinal shape.
- One of the plurality of second openings KB may have a different shape from the other one.
- the mask pattern 6 may include a plurality of second openings KB having different lengths in at least one of the X direction and the Y direction. may be included.
- the template substrate 7 has a base layer 4 including a seed layer 3 above the main substrate 1, and can be configured such that the seed portion 3S of the seed layer 3 is exposed at least in the first and second openings KF and KB. can.
- the first and second openings KF and KB may have a tapered shape (a shape in which the width narrows toward the underlayer 4 side).
- a plurality of layers are laminated on the main substrate 1, and the lamination direction can be the "upward direction”.
- viewing a substrate-shaped object such as the template substrate 7 with a line of sight parallel to the substrate normal can be referred to as “plan view”.
- FIG. 4 is a plan view showing the configuration of the semiconductor substrate according to this embodiment.
- 5A is a cross-sectional view taken along the line AA in FIG. 4.
- FIG. 5B is a cross-sectional view taken along line cc in FIG. 4.
- the semiconductor substrate 10 includes a template substrate 7 and first and second semiconductor portions 8F and 8B positioned above the mask pattern 6.
- a semiconductor substrate means a substrate including a semiconductor portion, and the main substrate 1 may be a semiconductor or may be a non-semiconductor. At least one of the first and second semiconductor portions 8F and 8B may be a layered semiconductor layer.
- the first and second semiconductor parts 8F and 8B contain nitride semiconductors, for example.
- a GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.
- the first and second semiconductor parts 8F and 8B may be of doped type (for example, n-type containing donors) or non-doped type.
- the first and second semiconductor portions 8F and 8B containing nitride semiconductors can be formed by the ELO method.
- ELO method for example, a heterogeneous substrate having a lattice constant different from that of a GaN-based semiconductor is used as the main substrate 1, a GaN-based semiconductor is used as the seed portion 3S, an inorganic compound film is used as the mask pattern 6, and a GaN-based semiconductor is used as the mask portion 5. can be laterally grown.
- the thickness direction (Z direction) of the first semiconductor portion 8F is the ⁇ 0001> direction (c-axis direction) of the GaN-based crystal
- the width direction (first direction, X direction) is the ⁇ 11-20> direction (a-axis direction) of the GaN-based crystal
- the longitudinal direction (Y-direction) of the first and second openings KF and KB is the ⁇ 1-100> direction of the GaN-based crystal. (m-axis direction).
- the first semiconductor portion 8F or the first and second semiconductor portions 8F and 8B formed by the ELO method may be collectively referred to as an ELO semiconductor portion (ELO semiconductor layer) 8 in some cases.
- the first semiconductor part 8F formed by the ELO method includes a plurality of ridges 8U corresponding to the plurality of first openings KF, and each ridge 8U has the Y direction as its longitudinal direction.
- the ridge portion 8U includes a low-defect portion (dislocation non-propagating portion) EK having relatively few threading dislocations and a dislocation propagating portion NS having a relatively large amount of threading dislocations overlapping the first opening KF in plan view.
- an active layer for example, a layer in which electrons and holes combine
- the active layer can be provided so as to overlap the low defect portion EK in plan view.
- the non-threading dislocation density in a cross section parallel to the ⁇ 0001> direction may be higher than the threading dislocation density.
- Threading dislocations are dislocations (defects) extending from the lower surface or inside of the first semiconductor portion 8F to the surface or surface layer along the thickness direction (Z direction) of the first semiconductor portion 8F. Threading dislocations can be observed by performing CL (Cathode Luminescence) measurement on the surface (parallel to the c-plane) of the first semiconductor portion 8F.
- Non-threading dislocations are dislocations measured by CL in a cross section parallel to the thickness direction, and are mainly basal plane (c-plane) dislocations.
- the cross section parallel to the thickness direction is, for example, the (1-100) plane (m-plane) or the (11-20) plane (a-plane).
- each ridge portion 8U of the first semiconductor portion 8F is separated from the second semiconductor portion 8B. Since the first opening KF is separated from the second opening KB arranged along the edge E (closer to the edge than the first opening KF), it overlaps with the second opening KB in plan view. Even if the second semiconductor portion 8B becomes an unintended deformed shape, the first semiconductor portion 8F that overlaps the first opening portion FK in a plan view is less likely to associate with the second semiconductor portion 8B and is less likely to be affected. That is, in the present embodiment, by using the second semiconductor portion 8B as a sacrificial layer, the shape of the first semiconductor portion 8F can be ensured. As shown in FIGS. 4 and 5, when the second semiconductor portion 8B has an unintended deformed shape, the average thickness of the second semiconductor portion 8B is reduced to that of the first semiconductor portion 8F due to an increase in raw material consumption. It may be smaller than the average thickness.
- FIG. 6 is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment.
- the semiconductor substrate 10 can be formed by removing the second semiconductor portion 8B, which is the sacrificial layer.
- FIG. 7 is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment.
- the semiconductor substrate 10 of FIG. 7 has a functional layer 9 above the first and second semiconductor portions 8F and 8B.
- the functional layer 9 may be, for example, a compound semiconductor portion containing a nitride semiconductor, and may be a single layer or a laminate.
- the portion including the second semiconductor portion 8B that is the sacrificial layer is the unusable portion NP, and the portion including the first semiconductor portion 8F is the usable portion DP.
- FIG. 8 is a flow chart showing an example of a method for manufacturing a template substrate according to this embodiment.
- the step of preparing the main substrate 1 after the step of preparing the main substrate 1, the step of forming the mask pattern 6 above the main substrate 1 is performed.
- FIG. 9 is a block diagram showing an example of a template substrate manufacturing apparatus according to this embodiment.
- the mask pattern forming portion 62 includes the mask portion 5, a plurality of first openings KF having a width direction in the X direction and a longitudinal direction in the Y direction, overlapping the non-peripheral edge portion 1P in plan view, and along the edge E in plan view. forming one or more second openings KB arranged in a manner such as;
- the mask pattern forming section 62 may include a CVD device or a PECVD device, and the control section 64 may include a processor and memory.
- the control unit 64 may be configured to control the mask pattern forming unit 62 by executing a program stored in an internal memory, a communicable communication device, or an accessible network.
- a storage medium or the like in which the data is stored is also included in this embodiment.
- FIG. 10 is a flow chart showing an example of a method for manufacturing a semiconductor substrate according to this embodiment. 10, after the step of preparing the template substrate 7, the step of forming the first and second semiconductor portions 8F and 8B on the template substrate 7 using the ELO method is performed. After the step of forming the first and second semiconductor portions 8F and 8B, the step of forming the functional layer 9 can be performed as necessary.
- FIG. 11 is a block diagram showing an example of a semiconductor substrate manufacturing apparatus according to this embodiment.
- a semiconductor substrate manufacturing apparatus 70 of FIG. 11 includes a semiconductor portion forming portion 72 for forming first and second semiconductor portions 8F and 8B on a template substrate 7 by the ELO method, and a control portion 74 for controlling the semiconductor portion forming portion 72. and The configuration may be such that the semiconductor substrate manufacturing apparatus 70 forms the functional layer 9 .
- FIG. 12 is a flow chart showing an example of a method for manufacturing a semiconductor device according to this embodiment.
- FIG. 13 is a plan view showing an example of separation of the element portion.
- FIG. 14 is a cross-sectional view (cross-sectional view of FIG. 13) showing an example of separation and spacing of the element portions.
- a plurality of trenches TR are formed in the semiconductor substrate 10 to isolate the element portion DS (including the low defect portion EK of the ridge portion 8U and the functional layer 9). carry out the process.
- Trench TR penetrates functional layer 9 and first semiconductor portion 8F.
- Base layer 4 and mask portion 5 may be exposed in trench TR.
- the device portion DS is van der Waals coupled with the mask portion 5 and is a part of the semiconductor substrate 10 .
- the element portion DS (including at least part of the ridge portion 8U) of the usable portion DP is separated from the template substrate 7, and a step of forming the semiconductor device 20 is performed.
- the step of preparing the semiconductor substrate 10 of FIG. 12 may include each step of the semiconductor substrate manufacturing method shown in FIG.
- Isolation of the element portion DS can be achieved by removing the portion of the first semiconductor portion 8F and the functional layer 9 overlapping the first opening portion KF in plan view by vapor-phase etching and peeling off the element portion DS from the template substrate 7. good.
- the first semiconductor portion 8F and the functional layer 9 can be easily peeled off from the mask portion 5 using, for example, a stamp.
- the stamp may be a viscoelastic elastomer stamp, a PDMS (Polydimethylsiloxane) stamp, an electrostatic adhesive stamp, or the like.
- a semiconductor device 20 including, for example, a GaN-based crystal
- the semiconductor device 20 include light emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, transistors (including power transistors and high electron mobility transistors), and the like.
- FIG. 15 is a schematic diagram showing the configuration of the electronic device according to this embodiment.
- the electronic device 30 of FIG. 15 includes a semiconductor substrate 10 (a configuration that functions as a semiconductor device while including the template substrate 7, for example, when the template substrate 7 is translucent) and a driving substrate on which the semiconductor substrate 10 is mounted. 23 and a control circuit 25 that controls the drive board 23 .
- FIG. 16 is a schematic diagram showing another configuration of the electronic device according to this embodiment.
- An electronic device 30 of FIG. 16 includes a semiconductor device 20 including a first semiconductor portion 8F, a drive substrate 23 on which the semiconductor device 20 is mounted, and a control circuit 25 that controls the drive substrate 23.
- FIG. 16 is a schematic diagram showing another configuration of the electronic device according to this embodiment.
- An electronic device 30 of FIG. 16 includes a semiconductor device 20 including a first semiconductor portion 8F, a drive substrate 23 on which the semiconductor device 20 is mounted, and a control circuit 25 that controls the drive substrate 23.
- Examples of the electronic device 30 include a display device, a laser emitting device (including a Fabry-Perot type and a surface emitting type), a lighting device, a communication device, an information processing device, a sensing device, a power control device, and the like.
- Example 1 17 is a plan view showing the structure of the template substrate according to the first embodiment;
- FIG. 18 is a cross-sectional view taken along line dd of FIG. 17.
- FIG. 19 is a plan view showing the configuration of the semiconductor substrate according to Example 1.
- the mask pattern 6 of the template substrate 7 according to the first embodiment has a mask portion 5 and a non-peripheral portion 1P in a plan view with the X direction as the width direction and the Y direction as the longitudinal direction. It has a plurality of overlapping first openings KF1 and KF2 and a plurality of second openings KB1 to KB4 arranged along the edge E in plan view.
- the peripheral portion 1S can be a region within 2 [mm] from the edge E, for example.
- a heterosubstrate having a lattice constant different from that of the GaN-based semiconductor can be used for the main substrate 1 .
- hetero-substrates include single-crystal silicon (Si) substrates, sapphire (Al 2 O 3 ) substrates, silicon carbide (SiC) substrates, and the like.
- the plane orientation of the main substrate 1 is, for example, the (111) plane of a silicon substrate, the (0001) plane of a sapphire substrate, and the 6H—SiC (0001) plane of a SiC substrate. These are just examples, and any main substrate and plane orientation may be used as long as the first and second semiconductor portions 8F and 8B can be grown by the ELO method.
- a buffer layer 2 and a seed layer 3 can be provided in order from the main substrate side.
- the buffer layer 2 has a function of reducing the direct contact between the main substrate 1 and the seed layer 3 and the melting thereof.
- a silicon substrate or the like is used for the main substrate 1, it melts with the GaN-based semiconductor that is the seed layer 3. Therefore, by providing the buffer layer 2 such as an AlN layer, the melting is reduced.
- the main substrate 1 that does not melt together with the seed layer 3, which is a GaN-based semiconductor is used, a configuration without the buffer layer 2 is possible.
- An AlN layer which is an example of the buffer layer 2 can be formed to a thickness of about 10 nm to about 5 ⁇ m using, for example, an MOCVD apparatus.
- the buffer layer 2 may have at least one of the effect of increasing the crystallinity of the seed layer 3 and the effect of relieving the internal stress of the ELO semiconductor portion 8 .
- Hexagonal layer system or cubic system silicon carbide (SiC) can also be used for the buffer layer 2 .
- the seed layer 3 for example, a GaN-based semiconductor such as GaN, a nitride such as AlN, or hexagonal silicon carbide (SiC) can be used.
- the seed layer 3 includes seed portions 3S (growing starting points of the ELO semiconductor portions 8) overlapping the first and second openings (KF1 to KF2 and KB1 to KB4) of the mask pattern 6. As shown in FIG.
- a graded layer whose Al composition is graded and approaches GaN may be used.
- the graded layer is, for example, a laminate in which an Al 0.7 Ga 0.3 N layer as a first layer and an Al 0.3 Ga 0.7 N layer as a second layer are provided in order from the buffer layer side is.
- the graded layer can be easily formed by MOCVD, and may be composed of three or more layers.
- the seed layer 3 can be configured to include a GaN layer.
- the seed layer 3 may be a single layer of GaN, or the uppermost layer of the graded layer that is the seed layer 3 may be a GaN layer.
- the seed layer 3 may not be arranged on the main substrate 1.
- the ELO semiconductor section 8 can be formed directly on the main substrate 1 on which the mask pattern 6 is arranged even without the seed layer.
- the first opening KF of the mask pattern 6 (mask layer) exposes the seed portion 3S and has the function of a growth start hole for starting the growth of the ELO semiconductor portion 8. may have the function of a selective growth mask for laterally growing the .
- the opening of the mask pattern is a portion (non-formation portion) where there is no mask portion, and may or may not be surrounded by the mask portion. .
- a film of platinum, rhodium, iridium, ruthenium, osmium, tungsten, molybdenum, etc. or a laminated film containing at least two of them can be used.
- a silicon oxide film having a thickness of about 100 nm to 4 ⁇ m (preferably about 150 nm to 2 ⁇ m) is formed on the underlying layer 4 by sputtering, and a resist is applied to the entire surface of the silicon oxide film.
- the resist is patterned by photolithography to form a resist having a plurality of striped openings.
- a part of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings (including KF1 to KF2 and KB1 to KB4), and the resist is organic.
- a mask pattern 6 is formed by removing by washing.
- the widths of the first openings KF1 and KF2 are about 0.1 ⁇ m to 20 ⁇ m. As the widths of the first openings KF1 and KF2 are smaller, the number of threading dislocations propagating from the first openings KF1 and KF2 to the ELO semiconductor portion 8 decreases. In addition, it becomes easy to separate (separate) the ELO semiconductor section 8 from the template substrate 7 in a post-process. Furthermore, the area of the low-defect portion EK with few surface defects can be increased in the ELO semiconductor portion 8 (ridge portion 8U).
- the mask portion 5 may be a single layer film of a silicon nitride film or a silicon oxynitride film, or may be a laminated film in which a silicon oxide film and a silicon nitride film are formed in this order on the underlying layer 4.
- ⁇ 4 may be a laminated film in which a silicon nitride film and a silicon oxide film are formed in this order, or a laminated film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order on an underlying layer.
- Abnormal portions such as pinholes in the mask portion 5 can be eliminated by performing organic cleaning after film formation, introducing the film into the film forming apparatus again, and forming the same type of film.
- a good quality mask portion 5 can also be formed by using a general silicon oxide film (single layer) and using such a film formation method.
- Example 1 the minimum distance between the plurality of first openings KF1 and KF2 and the edge E is greater than the distance between the plurality of second openings KB1 to KB4 and the edge E in plan view.
- a plurality of first openings (including KF1 and KF2) whose length is in the Y direction are arranged in the X direction, and the lengths in the Y direction become smaller as they move away from the main substrate center MC in the X direction.
- the first opening KF2 has a larger distance in the X direction from the main substrate center MC and a smaller length in the Y direction than the first opening KF1.
- the minimum length Yf in the Y direction of the plurality of first openings is greater than the length Yb in the Y direction of the plurality of second openings (including KB1 to KB4).
- the number of the plurality of second openings is equal to twice the number of the plurality of first openings (including KF1 and KF2).
- first opening KF1 and the second opening KB1 are adjacent to each other and overlap each other when viewed in the Y direction. located between That is, the second opening KB1, the first opening KF1, and the second opening KB3 are arranged in the Y direction, one tip of the first opening KF1 is adjacent to the second opening KB1, and the other tip is the second opening KB1. Adjacent to opening KB3.
- the distance between the first opening KF1 and the second opening KB1 and the distance between the first opening KF1 and the second opening KB3 are larger than the distance between the second openings KB1 and KB3 and the edge E.
- the width (length in the X direction) of the second openings KB1 and KB3 may be the same, larger, or smaller than the width of the first opening KF1.
- the widths of the plurality of second openings KB1 to KB4 may be different.
- the opening pattern including the plurality of first openings KF1 and KF2 and the plurality of second openings KB1 to KB4 passes through the main substrate center MC and is symmetrical with respect to a line parallel to the X direction. It's okay.
- the edge E of the main substrate 1 has a curved surface portion Er and a flat surface portion Ef connected to the curved surface portion Er and having a normal line parallel to the X direction, but is not limited to this.
- the main substrate 1 may be disc-shaped.
- the plane portion Ef may have a function as a plane orientation indicator (orientation flat).
- the orientation indicator can also be configured with a notch (notch).
- a layered body in which a silicon oxide film (SiO 2 ) and a silicon nitride film (SiN) are formed in this order is used for the mask portion 5 .
- the thickness of the silicon oxide film is, for example, 0.3 ⁇ m, and the thickness of the silicon nitride film is, for example, 70 nm.
- a plasma-enhanced chemical vapor deposition (CVD) method was used to form each of the silicon oxide film and the silicon nitride film.
- the semiconductor substrate 10 of Example 1 includes a first semiconductor portion 8F that overlaps the first openings KF1 and KF2 in plan view, and a second semiconductor portion 8F that overlaps the second openings KB1 and KB2 in plan view. and part 8B.
- the first and second semiconductor portions 8F and 8B can be ELO semiconductor portions containing a nitride semiconductor (for example, GaN-based).
- the first semiconductor portion 8F has the Y direction as its longitudinal direction and includes a plurality of ridges 8U arranged in the X direction.
- a plurality of second openings KB1 and KB2 are provided along the edge E in the first embodiment, in which the end of each ridge 8U is tapered.
- Example 1 the first and second semiconductor portions 8F and 8B were GaN layers, and ELO film formation was performed on the aforementioned template substrate 7 using the MOCVD apparatus included in the semiconductor formation portion 72 of FIG.
- the first and second semiconductor portions 8F and 8B are selectively grown on the seed portion 3S (the uppermost GaN layer of the seed layer 3) exposed in the first and second openings KF1, KF2, KB1, and KB2. Then, it grows laterally on the mask portion 5 . Then, the lateral growth was stopped before the films (ridges 8U) laterally grown on both sides of the mask portion 5 were brought together.
- the width Wm of the mask portion 5 is 50 ⁇ m
- the width of the first openings KF1 and KF2 is 5 ⁇ m
- the width of each ridge portion 8U of the first semiconductor portion 8F is 53 ⁇ m
- the width (size in the X direction) of the low defect portion EK is 24 ⁇ m.
- the layer thickness of the ridge portion 8U was 5 ⁇ m.
- first semiconductor portion 8F In the film formation of the first semiconductor portion 8F, it is possible to reduce mutual reaction between the first semiconductor portion 8F and the mask portion 5 so that the first semiconductor portion 8F and the mask portion 5 are brought into contact with each other due to van der Waals force. preferable.
- the method for increasing the film formation rate in the lateral direction is as follows. First, a vertical growth layer growing in the Z direction (c-axis direction) is formed on the seed portion 3S, and then a lateral growth layer growing in the X direction (a-axis direction) is formed. At this time, by setting the thickness of the vertical growth layer to 10 ⁇ m or less, 5 ⁇ m or less, 3 ⁇ m or less, or 1 ⁇ m or less, the thickness of the horizontal growth layer can be kept low and the horizontal film formation rate can be increased.
- FIG. 20 is a cross-sectional view showing an example of lateral growth of the first semiconductor section.
- an initial growth layer (longitudinal growth layer) SL is formed on the seed portion 3S, and then the first semiconductor portion 8F (a plurality of ridges 8U) is laterally grown from the initial growth layer SL. is desirable.
- the initial growth layer SL serves as a starting point for lateral growth of the first semiconductor portion 8F.
- the initial growth is performed immediately before the edge of the initial growth layer SL climbs over the upper surface of the mask portion 5 (at the stage where it is in contact with the upper end of the side surface of the mask portion 5) or immediately after it climbs over the upper surface of the mask portion 5.
- a method of stopping the film formation of the layer SL that is, switching the ELO film formation conditions from the c-axis direction film formation conditions to the a-axis direction film formation conditions at this timing) can be used.
- the initial growth layer SL can be formed with a thickness of, for example, 50 nm to 5.0 ⁇ m (eg, 80 nm to 2 ⁇ m).
- the thickness of the mask portion 5 and the thickness of the initial growth layer SL may be 500 nm or less.
- the initial growth layer SL (part of the dislocation inheriting portion NS) is formed and then grown laterally, thereby increasing the non-uniformity inside the low defect portion EK. Threading dislocations can be increased (threading dislocation density on the surface of the low defect portion EK can be reduced). In addition, it is possible to control the distribution of impurity concentration (for example, silicon, oxygen) inside the low-defect portion EK. If the method of FIG.
- the first semiconductor portion 8F shown in FIG. 20 can be a nitride semiconductor crystal (for example, GaN crystal, AlGaN crystal, InGaN crystal, or InAlGaN crystal).
- a temperature of 1150°C or less is preferable to a temperature exceeding 1200°C. It is possible to form the ELO semiconductor portion 8 even at a low temperature of less than 1000° C., which is preferable from the viewpoint of reducing the mutual reaction.
- TMG trimethylgallium
- the source is not sufficiently decomposed, and more gallium atoms and carbon atoms than usual are taken into the ELO semiconductor portion 8 at the same time.
- TMG trimethylgallium
- the carbon taken into the ELO semiconductor portion 8 reduces the reaction with the mask portion 5 and reduces adhesion between the mask portion 5 and the ELO semiconductor portion 8 . Therefore, in the low-temperature film formation of the ELO semiconductor section 8, the supply amount of ammonia is reduced and the film is formed at a low V/III ( ⁇ 1000) so that the raw material or the carbon element in the chamber atmosphere is taken into the ELO semiconductor section 8. , the reaction with the mask portion 5 can be reduced.
- the ELO semiconductor portion 8 is configured to contain carbon.
- TEG triethylgallium
- FIG. 21 is a plan view showing another configuration example of the template substrate according to the first embodiment.
- 22 is a plan view showing the configuration of a semiconductor substrate including the template substrate of FIG. 21.
- the first opening KF1 and the second opening KB1 are adjacent to each other and overlap when viewed in the Y direction, but the invention is not limited to this.
- the mask pattern 6 includes a plurality of first openings KF1 and KF2 and second openings KB1 to KB6 arranged along the edge E. KB1 may be adjacent to each other and overlap when viewed in the X direction.
- one end of the first opening KF2 is located between the second openings KB1 and KB2 aligned in the X direction, and the other end is located between the second openings KB3 and KB4 aligned in the X direction.
- the number of the plurality of second openings is more than twice the number of the plurality of first openings (including KF1 and KF2), and the number of the second openings KB5 and KB6 is positioned outside the two outermost first openings of all the first openings.
- the semiconductor substrate 10 of FIG. 22 includes a first semiconductor portion 8F overlapping the mask portion 5 and the first openings KF1 and KF2 in plan view, and a second semiconductor portion overlapping the mask portion 5 and the second opening portions KB1 and KB2 in plan view.
- the first semiconductor portion 8F includes a plurality of ridges 8U overlapping the first openings KF1 and KF2 in plan view.
- each ridge 8U of the first semiconductor portion 8F has an irregular shape. is separated from the second semiconductor portion 8B (sacrificial layer) of , and the shape of each ridge portion 8U is ensured.
- edge growth generated at the tip of the ridge 8U overlapping the first opening KF2 part
- FIG. 23 is a plan view showing another configuration example of the template substrate according to the first embodiment.
- the mask pattern is provided with a plurality of first openings KF1 and KF2 and second openings KB1 to KB6 arranged along the edge E of the main substrate 1 in plan view.
- KB2 the first opening KF1, and the second opening KB5 are arranged in the Y direction, and one end of the first opening KF1 is adjacent to the second opening KB2, and the other end is adjacent to the second opening KB5. .
- one end of the first opening KF1 is positioned between the second openings KB1 and KB3 aligned in the X direction, and the other end is positioned between the second openings KB4 and KB6 aligned in the X direction. do.
- FIG. 24 is a plan view showing another configuration example of the template substrate according to the first embodiment. As shown in FIG. 24, using the main substrate 1 including the curved surface portion Er, a plurality of second openings KB having a curved longitudinal shape are formed in the mask pattern 6 along the edge E of the main substrate 1 in plan view. can also be placed in
- FIG. 25 is a plan view showing another configuration example of the template substrate according to the second embodiment.
- 26 is a plan view showing the configuration of a semiconductor substrate including the template substrate of FIG. 25.
- the mask pattern is provided with a plurality of second openings in the first embodiment, the present invention is not limited to this.
- Example 2 the minimum distance between the plurality of first openings KF1 and KF2 and the edge E is greater than the distance between the annular second opening KBL and the edge E in plan view.
- a plurality of first openings (including KF1 and KF2) whose length is in the Y direction are arranged in the X direction, and the lengths in the Y direction become smaller as they move away from the main substrate center MC in the X direction.
- first opening KF1 and the second opening KBL are adjacent to each other and overlap when viewed in the Y direction.
- the opening pattern including the plurality of first openings KF1 and KF2 and the annular second opening KBL may have a line-symmetrical shape with respect to a line passing through the main substrate center MC and parallel to the X direction. .
- the semiconductor substrate 10 of FIG. 26 includes a first semiconductor portion 8F that overlaps the first openings KF1 and KF2 in plan view, and a second semiconductor portion 8B that overlaps the second opening KBL in plan view.
- 8F includes a plurality of ridges 8U overlapping the first openings KF1 and KF2 in plan view.
- each ridge 8U of the first semiconductor portion 8F is formed by the deformed second semiconductor. It is separated from the portion 8B (sacrificial layer), and the shape of each ridge portion 8U is ensured.
- FIG. 27 is a plan view showing another configuration example of the template substrate according to the second embodiment.
- the mask pattern 6 includes a plurality of first openings KF1 and KF2, an annular second opening KBL arranged along the edge E, and a second opening KBL arranged along the edge E.
- the first opening KF1 and the second opening KB1 may be adjacent to each other and overlap when viewed in the X direction.
- one end of the first opening KF2 is located between the second openings KB1 and KB2 aligned in the X direction, and the other end is located between the second openings KB3 and KB4 aligned in the X direction.
- the number of the plurality of second openings is less than twice the number of the plurality of first openings (including KF1 and KF2), and all the first openings in the X direction There are no island-shaped second openings outside the two outermost first openings, and only the annular second openings KBL are present.
- FIG. 28 is a plan view showing another configuration example of the template substrate according to the second embodiment.
- the mask portion 5 exists at the edge of the template substrate 7, but it is not limited to this.
- the edge of the template substrate 7 may have no mask portion. That is, at the time of patterning the mask pattern 6, by penetrating the ring-shaped region having the edge E of the main substrate 1 as the outer periphery in plan view (providing the ring-shaped edge opening KE), the ring-shaped edge of the template substrate 7 is formed. The seed portion 3S is exposed.
- the annular sacrificial layer is formed on the edge thereof, the shape of the first semiconductor portion 8F overlapping the first openings KF1 and KF2 is ensured.
- the ELO semiconductor portion 8 is a GaN layer, but it is not limited to this.
- InGaN layers which are GaN-based semiconductor portions, can also be formed. Lateral deposition of the InGaN layer is performed at low temperatures, eg, below 1000.degree. This is because, at high temperatures, the vapor pressure of indium increases and it is not effectively incorporated into the film. Lowering the film formation temperature has the effect of reducing the mutual reaction between the mask portion 5 and the InGaN layer. In addition, the InGaN layer has the effect of being less reactive with the mask portion 5 than the GaN layer.
- TAG triethylgallium
- FIG. 29 is a schematic cross-sectional view showing the configuration of Example 4.
- the functional layer 9 forming the LED is formed on the base semiconductor portion 8S obtained as all or part of the ridge portion 8U of the first semiconductor portion 8F.
- the base semiconductor portion 8S is of n-type doped with silicon or the like, for example.
- the functional layer 9 includes an active layer 34, an electron blocking layer 35, and a GaN-based p-type semiconductor portion 36 in order from the lower layer side.
- the active layer 34 is an MQW (Multi-Quantum Well) and includes an InGaN layer and a GaN layer.
- the electron blocking layer 35 is, for example, an AlGaN layer.
- the GaN-based p-type semiconductor portion 36 is, for example, a GaN layer.
- the anode 38 is arranged so as to be in contact with the GaN-based p-type semiconductor portion 36, and the cathode 39 is arranged so as to be in contact with the base semiconductor portion 8S.
- a semiconductor device 20 including a GaN-based crystal
- FIG. 30 is a cross-sectional view showing an example of application of the sixth embodiment to an electronic device.
- a red micro-LED 20R, a green micro-LED 20G, and a blue micro-LED 20B can be obtained, and by mounting these on a drive substrate (TFT substrate) 23, a micro LED display 30D (electronic device) can be configured. can be done.
- a red micro-LED 20R, a green micro-LED 20G, and a blue micro-LED 20B are mounted on a plurality of pixel circuits 27 of the driving substrate 23 via a conductive resin 24 (for example, an anisotropic conductive resin) or the like, and then mounted on the driving substrate 23.
- a control circuit 25, a driver circuit 29, and the like are mounted.
- a portion of the driver circuit 29 may be included in the drive substrate 23 .
- FIG. 31 is a schematic cross-sectional view showing the configuration of Example 5.
- a functional layer 9 forming a semiconductor laser is formed on the base semiconductor portion 8S.
- the functional layer 9 includes, from the lower layer side, an n-type optical cladding layer 41, an n-type optical guide layer 42, an active layer 43, an electron blocking layer 44, a p-type optical guide layer 45, a p-type optical cladding layer 46, and a GaN-based layer.
- a p-type semiconductor portion 47 is included.
- An InGaN layer can be used for each of the guide layers 42 and 45 .
- a GaN layer or an AlGaN layer can be used for each of the clad layers 41 and 46 .
- the anode 48 is arranged so as to be in contact with the GaN-based p-type semiconductor portion 47, and the cathode 49 is arranged so as to be in contact with the base semiconductor portion 8S.
- the semiconductor device 20 can be obtained.
- FIG. 32 is a cross-sectional view showing the configuration of the sixth embodiment.
- a sapphire substrate having an uneven surface is used as the main substrate 1 .
- Underlayer 4 has buffer layer 2 and seed layer 3 .
- a GaN layer having a (20-21) plane is deposited as the base layer 4 on the main substrate 1 .
- the first semiconductor portion 8F becomes the (20-21) plane, which is the main crystal plane in the underlying layer 4, and the first semiconductor portion 8F having a semipolar plane can be obtained.
- a GaN layer having a (11-22) plane can also be formed as the base layer 4 on the main substrate 1 by using a sapphire substrate having an uneven surface.
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Abstract
Description
図1は、本実施形態に係るテンプレート基板の構成を示す平面図である。図2は、図1のa-a矢視断面図(非周縁部)である。図3は、図1のb-b矢視断面図(周縁部)である。
図4は、本実施形態に係る半導体基板の構成を示す平面図である。図5Aは、図4のA-A矢視断面図である。図5Bは、図4のc-c矢視断面図である。図4、図5Aおよび図5Bに示すように、半導体基板10は、テンプレート基板7と、マスクパターン6よりも上層に位置する、第1および第2半導体部8F・8Bとを備える。半導体基板とは、半導体部を含む基板という意味であり、主基板1は、半導体であってもよいし、非半導体であってもよい。第1および第2半導体部8F・8Bの少なくとも一方が層状の半導体層であってもよい。
図8は、本実施形態にかかるテンプレート基板の製造方法の一例を示すフローチャートである。図8のテンプレート基板の製造方法では、主基板1を準備する工程の後に、主基板1よりも上方にマスクパターン6を形成する工程を行う。
図10は、本実施形態にかかる半導体基板の製造方法の一例を示すフローチャートである。図10の半導体基板の製造方法では、テンプレート基板7を準備する工程の後に、テンプレート基板7上に、ELO法を用いて第1および第2半導体部8F・8Bを形成する工程を行う。第1および第2半導体部8F・8Bを形成する工程の後に、必要に応じて、機能層9を形成する工程を行うことができる。
図12は、本実施形態にかかる半導体デバイスの製造方法の一例を示すフローチャートである。図13は、素子部の分離の一例を示す平面図である。図14は、素子部の分離および離隔の一例を示す断面図(図13の矢視断面図)である。図12の半導体デバイスの製造方法では、半導体基板10を準備する工程の後に、必要に応じて、第1および第2半導体部8F・8B上に機能層9を形成する工程を行う。その後、図13および図14に示すように、半導体基板10に複数のトレンチTR(分離溝)を形成して素子部DS(畝部8Uの低欠陥部EKおよび機能層9を含む)を分離する工程を行う。トレンチTRは、機能層9および第1半導体部8Fを貫通する。トレンチTR内に下地層4およびマスク部5が露出してもよい。この段階では、素子部DSはマスク部5とファンデルワールス結合しており、半導体基板10の一部である。その後、図14に示すように、利用可能部分DPの素子部DS(畝部8Uの少なくとも一部を含む)をテンプレート基板7から離隔し、半導体デバイス20とする工程を行う。図12の半導体基板10を準備する工程に、図10に示される、半導体基板の製造方法の各工程が含まれていてもよい。
図14に示すように、素子部DSをテンプレート基板7から離隔することで、半導体デバイス20(例えば、GaN系結晶体を含む)を形成することができる。半導体デバイス20の具体例として、発光ダイオード(LED)、半導体レーザ、ショットキーダイオード、フォトダイオード、トランジスタ(パワートランジスタ、高電子移動度トランジスタを含む)等を挙げることができる。
図15は、本実施形態に係る電子機器の構成を示す模式図である。図15の電子機器30は、半導体基板10(テンプレート基板7を含んだ状態で半導体デバイスとして機能する構成、例えばテンプレート基板7が透光性である場合)と、半導体基板10が実装される駆動基板23と、駆動基板23を制御する制御回路25とを含む。
図17は、実施例1に係るテンプレート基板の構成を示す平面図である。図18は、図17のd-d矢視断面図である。図19は、実施例1に係る半導体基板の構成を示す平面図である。
主基板1には、GaN系半導体と異なる格子定数を有する異種基板を用いることができる。異種基板としては、単結晶のシリコン(Si)基板、サファイア(Al2O3)基板、シリコンカーバイド(SiC)基板等を挙げることができる。主基板1の面方位は、例えば、シリコン基板の(111)面、サファイア基板の(0001)面、SiC基板の6H-SiC(0001)面である。これらは例示であって、第1および第2半導体部8F・8BをELO法で成長させることができる主基板および面方位であれば何でもよい。
下地層4として、主基板側から順に、バッファ層2およびシード層3を設けることができる。バッファ層2は、主基板1とシード層3とがダイレクトに接触して互いに溶融することを低減する機能を有する。主基板1にシリコン基板等を用いた場合、シード層3であるGaN系半導体と溶融し合うため、例えば、AlN層等のバッファ層2を設けることで、溶融が低減される。例えば、GaN系半導体であるシード層3と溶融し合わない主基板1を用いた場合には、バッファ層2を設けない構成も可能である。バッファ層2の一例であるAlN層は、例えばMOCVD装置を用いて、厚さ10nm程度~5μm程度に形成することができる。バッファ層2が、シード層3の結晶性を高める効果、およびELO半導体部8の内部応力を緩和する効果の少なくとも一方を有していてもよい。バッファ層2に、六方晶層系あるいは立方晶系の炭化シリコン(SiC)を用いることもできる。
マスクパターン6(マスク層)の第1開口部KFは、シード部3Sを露出させ、ELO半導体部8の成長を開始させる、成長開始用ホールの機能を有し、マスク部5は、半導体部8を横方向成長させるための選択成長用マスクの機能を有していてもよい。マスクパターンの開口部は、マスク部がない部分(非形成部)であり、マスク部に囲まれていてもよいし、囲まれていなくてもよい。
。マスクパターン6として、例えば、シリコン酸化膜(SiOx)、窒化チタン膜(TiN等)、シリコン窒化膜(SiNx)、シリコン酸窒化膜(SiON)、および高融点(例えば1000度以上)をもつ金属膜(例えば、プラチナ、ロジウム、イリジウム、ルテニウム、オスミウム、タングステン、モリブデン等の膜)のいずれか1つを含む単層膜、またはこれらの少なくとも2つを含む積層膜を用いることができる。
主基板1には、(111)面を有するシリコン基板を用い、下地層4のバッファ層2は、AlN層(例えば、30nm)とした。下地層4は、第1層であるAl0.6Ga0.4N層(例えば、300nm)と、第2層であるGaN層(例えば、1~2μm)とがこの順に形成されたグレーデッド層とする。すなわち、第2層(Ga:N=1:1)におけるGaの組成比(1/2=0.5)は、第1層(Al:Ga:N=0.6:0.4:1)におけるGaの組成比(0.6/2=0.3)よりも大きい。
図19に示すように、実施例1の半導体基板10は、平面視で第1開口部KF1・KF2と重なる第1半導体部8Fと、平面視で第2開口部KB1・KB2と重なる第2半導体部8Bとを含む。第1および第2半導体部8F・8Bは、窒化物半導体を含む(例えばGaN系の)ELO半導体部とすることができる。
図25は、実施例2に係るテンプレート基板の別構成例を示す平面図である。図26は、図25のテンプレート基板を含む半導体基板の構成を示す平面図である。実施例1ではマスクパターンに複数の第2開口部を設けているが、これに限定されない。図26に示すように、曲面部Erを含む主基板1を用い、マスクパターン6に、環状の第2開口部KBLを、平面視で主基板1のエッジEに沿うように配することもできる。
実施例1~2では、ELO半導体部8をGaN層としているがこれに限定されない。実施例1~2の第1および第2半導体部8F・8B(ELO半導体部8)として、GaN系半導体部であるInGaN層を形成することもできる。InGaN層の横方向成膜は、例えば1000℃を下回るような低温で行う。高温ではインジウムの蒸気圧が高くなり、膜中に有効に取り込まれないためである。成膜温度が低温になることで、マスク部5とInGaN層の相互反応が低減される効果がある。また、InGaN層は、GaN層よりもマスク部5との反応性が低いという効果もある。InGaN層にインジウムがIn組成レベル1%以上で取り込まれるようになると、マスク部5との反応性がさらに低下するため、望ましい。ガリウム原料ガスとしては、トリエチルガリウム(TEG)を用いることが好ましい。
図29は、実施例4の構成を示す模式的断面図である。実施例4では、第1半導体部8Fの畝部8Uの全部または一部として得られるベース半導体部8Sの上に、LEDを構成する機能層9を成膜する。ベース半導体部8Sは、例えばシリコン等がドープされたn型である。機能層9は、下層側から順に、活性層34、電子ブロッキング層35、およびGaN系p型半導体部36を含む。活性層34は、MQW(Multi-Quantum Well)であり、InGaN層およびGaN層を含む。電子ブロッキング層35は、例えばAlGaN層である。GaN系p型半導体部36は、例えばGaN層である。アノード38は、GaN系p型半導体部36と接触するように配され、カソード39は、ベース半導体部8Sと接触するように配される。ベース半導体部8Sおよび機能層10をテンプレート基板7から離隔することで半導体デバイス20(GaN系結晶体を含む)を得ることができる。
図31は、実施例5の構成を示す模式的断面図である。実施例5では、ベース半導体部8S上に、半導体レーザを構成する機能層9を成膜する。機能層9は、下層側から順に、n型光クラッド層41、n型光ガイド層42、活性層43、電子ブロッキング層44、p型光ガイド層45、p型光クラッド層46、およびGaN系p型半導体部47を含む。各ガイド層42・45には、InGaN層を用いることができる。各クラッド層41・46には、GaN層もしくはAlGaN層を用いることができる。アノード48はGaN系p型半導体部47と接触するように配され、カソード49はベース半導体部8Sと接触するように配される。ベース半導体部8Sおよび機能層10をテンプレート基板7から離隔することで半導体デバイス20を得ることができる。
図32は実施例6の構成を示す断面図である。実施例6では、主基板1に、表面凹凸加工されたサファイア基板を用いる。下地層4は、バッファ層2およびシード層3を有する。図32では、主基板1上に(20-21)面を持つGaN層を下地層4として成膜する。この場合、第1半導体部8Fは下地層4において結晶主面である(20-21)面となり、半極性面の第1半導体部8Fを得ることができる。半極性面上に、レーザ、LED用の機能層を設けることで、活性層において、電子とホールの再結合確率が高まるといったメリットがある。なお、表面凹凸加工されたサファイア基板を用いることで、主基板1上に(11-22)面をもつGaN層を下地層4として成膜することもできる。
2 バッファ層
3 シード層
3S シード部
4 下地層
5 マスク部
6 マスクパターン
8F 第1半導体部
8B 第2半導体部
8U 畝部
9 機能層
10 半導体基板
20 半導体デバイス
30 電子機器
KF KF1・KF2 第1開口部
KB KB1~KB6 第2開口部
Claims (34)
- エッジ、前記エッジを含む周縁部、および前記周縁部よりも内側に位置する非周縁部を有する主基板と、
前記主基板よりも上方に位置するマスクパターンと、を備え、
前記マスクパターンは、マスク部と、第1方向を幅方向、第2方向を長手方向とし、平面視において前記非周縁部と重なる複数の第1開口部と、平面視において前記エッジに沿うように配された、1つまたは複数の第2開口部とを有している、テンプレート基板。 - 前記複数の第1開口部の少なくとも1つと、前記複数の第2開口部の少なくとも1つとが互いに隣接し、かつ前記第2方向に視たときに重なる、請求項1に記載のテンプレート基板。
- 前記複数の第1開口部の少なくとも1つが、前記第2方向に並ぶ2つの第2開口部の間に位置する、請求項2に記載のテンプレート基板。
- 前記複数の第1開口部の少なくとも1つと、前記複数の第2開口部の少なくとも1つとが互いに隣接し、かつ前記第1方向に視たときに重なる、請求項1に記載のテンプレート基板。
- 前記複数の第1開口部が第1方向に並ぶ、請求項1~4のいずれか1項に記載のテンプレート基板。
- 前記複数の第1開口部は、主基板中央からの前記第1方向の距離が異なる2つの第1開口部を含み、前記2つの第1開口部の一方は他方に比べて前記距離が大きく、かつ前記第2方向の長さが小さい、請求項5に記載のテンプレート基板。
- 前記複数の第1開口部の第2方向の最小の長さが、前記1つまたは複数の第2開口部の第2方向の長さよりも大きい、請求項6に記載のテンプレート基板。
- 前記複数の第1開口部の少なくとも1つと、前記2つの第2開口部の一方との距離は、平面視における前記2つの第2開口部の一方と前記エッジとの距離よりも大きい、請求項3に記載のテンプレート基板。
- 前記エッジが曲面部を含む、請求項1に記載のテンプレート基板。
- 前記複数の第2開口部が湾曲形状を有する、請求項9に記載のテンプレート基板。
- 前記1つの第2開口部、または前記複数の第2開口部の1つが環状を有する、請求項1または4に記載のテンプレート基板。
- 前記エッジが前記曲面部と繋がり、前記第1方向に平行な法線を有する平面部を含む、請求項9に記載のテンプレート基板。
- 平面視で前記複数の第1開口部と重なるシード層を有する、請求項1~12のいずれか1項に記載のテンプレート基板。
- 前記周縁部は、前記エッジから2〔mm〕以内の領域である、請求項1~13のいずれか1項に記載のテンプレート基板。
- 前記主基板はシリコン基板である、請求項1~14のいずれか1項に記載のテンプレート基板。
- GaN系半導体部のELO形成に用いられる、請求項1~15のいずれか1項に記載のテンプレート基板。
- エッジ、前記エッジを含む周縁部、および前記周縁部よりも内側に位置する非周縁部を有する主基板と、前記主基板よりも上方に位置するマスクパターンと、を備えるテンプレート基板の製造方法であって、
前記マスクパターンに、マスク部と、第1方向を幅方向、第2方向を長手方向とし、平面視において前記非周縁部と重なる複数の第1開口部と、平面視において前記エッジに沿うように配された、1つまたは複数の第2開口部とを形成する、テンプレート基板の製造方法。 - エッジ、前記エッジを含む周縁部、および前記周縁部よりも内側に位置する非周縁部を有する主基板と、前記主基板よりも上方に位置するマスクパターンと、を備えるテンプレート基板の製造装置であって、
マスク部と、第1方向を幅方向、第2方向を長手方向とし、平面視において前記非周縁部と重なる複数の第1開口部と、平面視において前記エッジに沿うように配された、1つまたは複数の第2開口部とを含むマスクパターンを形成するマスクパターン形成部を備える、テンプレート基板の製造装置。 - 請求項1~16のいずれか1項に記載のテンプレート基板と、前記マスク部と重なる第1半導体部とを備える半導体基板。
- 平面視において前記1つまたは複数の第2開口部と重なる第2半導体部を備え、
前記第1半導体部は、前記複数の第1開口部と重なる、請求項19に記載の半導体基板。 - 前記第1半導体部と前記第2半導体部とが分離している、請求項20に記載の半導体基板。
- 前記第1半導体部は、前記複数の第1開口部それぞれに対応する複数の畝部を含み、
各畝部は、前記第2方向を長手方向とし、前記第2半導体部から分離されている、請求項21に記載の半導体基板。 - 前記第2半導体部は、前記第1半導体部よりも平均厚みが小さい、請求項20~22のいずれか1項に記載の半導体基板。
- 平面視において、各畝部の端部が先細り形状である、請求項22に記載の半導体基板。
- 前記第1半導体部はGaN系半導体を含む、請求項19~24のいずれか1項に記載の半導体基板。
- 前記主基板は、GaN系半導体と格子定数が異なる異種基板である、請求項25に記載の半導体基板。
- 前記第1方向は、前記GaN系半導体の<11-20>方向であり、
前記第2方向は、前記GaN系半導体の<1-100>方向である、請求項25に記載の半導体基板。 - 前記第1半導体部よりも上層に位置する機能層を含む、請求項20に記載の半導体基板。
- 請求項19~28のいずれか1項に記載の第1半導体部を含む、半導体デバイス。
- 請求項29に記載の半導体デバイスを含む、電子機器。
- 請求項19に記載の半導体基板の製造方法であって、
前記第1半導体部をELO法で形成する、半導体基板の製造方法。 - 請求項19に記載の半導体基板の製造装置であって、
前記第1半導体部をELO法で形成する、半導体基板の製造装置。 - 請求項28に記載の半導体基板を準備する工程と、前記第2半導体部を含む部分を利用不可部分とし、前記第1半導体部および前記機能層を含む部分から半導体デバイスを得る工程とを含む、半導体デバイスの製造方法。
- 請求項28に記載の半導体基板を準備する工程と、前記第2半導体部を含む部分を利用不可部分とし、前記第1半導体部を含む部分から半導体デバイスを得る工程とを行う、半導体デバイスの製造装置。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000294827A (ja) * | 1999-04-02 | 2000-10-20 | Nichia Chem Ind Ltd | 窒化物半導体の成長方法 |
JP2011066390A (ja) * | 2009-08-20 | 2011-03-31 | Pawdec:Kk | 半導体素子の製造方法 |
JP2012134243A (ja) * | 2010-12-20 | 2012-07-12 | Fujitsu Ltd | 化合物半導体装置及びその製造方法 |
JP2014111527A (ja) * | 2012-11-26 | 2014-06-19 | Soraa Inc | Iii族金属窒化物結晶およびその形成方法 |
US20170263440A1 (en) * | 2016-03-10 | 2017-09-14 | Infineon Technologies Ag | Method of reducing defects in an epitaxial layer |
WO2018030311A1 (ja) * | 2016-08-08 | 2018-02-15 | 三菱ケミカル株式会社 | 導電性C面GaN基板 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000294827A (ja) * | 1999-04-02 | 2000-10-20 | Nichia Chem Ind Ltd | 窒化物半導体の成長方法 |
JP2011066390A (ja) * | 2009-08-20 | 2011-03-31 | Pawdec:Kk | 半導体素子の製造方法 |
JP2012134243A (ja) * | 2010-12-20 | 2012-07-12 | Fujitsu Ltd | 化合物半導体装置及びその製造方法 |
JP2014111527A (ja) * | 2012-11-26 | 2014-06-19 | Soraa Inc | Iii族金属窒化物結晶およびその形成方法 |
US20170263440A1 (en) * | 2016-03-10 | 2017-09-14 | Infineon Technologies Ag | Method of reducing defects in an epitaxial layer |
WO2018030311A1 (ja) * | 2016-08-08 | 2018-02-15 | 三菱ケミカル株式会社 | 導電性C面GaN基板 |
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