WO2022270309A1 - 半導体デバイスの製造方法および製造装置、半導体デバイスならびに電子機器 - Google Patents
半導体デバイスの製造方法および製造装置、半導体デバイスならびに電子機器 Download PDFInfo
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
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Definitions
- the present disclosure relates to a method of manufacturing a semiconductor device and the like.
- Patent Literature 1 discloses a method of forming through holes in a sapphire substrate and a GaN buffer layer grown thereon, and extracting an electrode in contact with a GaN contact layer through the through holes to the lower side of the sapphire substrate.
- a method of manufacturing a semiconductor device includes steps of preparing a template substrate having a main substrate and a mask pattern located above the main substrate and including a mask portion and an opening, and employing an ELO method. removing a portion of the main substrate overlapping the opening in plan view; and removing the opening in plan view of the first semiconductor part. and removing the portion that overlaps the portion.
- FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment;
- FIG. It is a flow chart which shows an example of a manufacturing method of a semiconductor device concerning this embodiment. It is a sectional view showing an example of a manufacturing method of a semiconductor device concerning this embodiment.
- 1 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to an embodiment;
- FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to Example 1;
- FIG. 1 is a cross-sectional view showing the configuration of an electronic device according to Example 1;
- FIG. 4 is a flow chart showing an example of a method for manufacturing a semiconductor device according to Example 1;
- FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to Example 1;
- FIG. 2 is a plan view showing an example of a method for manufacturing a semiconductor device according to Example 1;
- FIG. 2 is a plan view showing an example of a method for manufacturing a semiconductor device according to Example 1;
- FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to Example 1;
- FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to Example 1;
- FIG. 2 is a plan view showing an example of a method for manufacturing a semiconductor device according to Example 1;
- FIG. 4 is a cross-sectional view showing another example of the method for manufacturing the semiconductor device according to Example 1;
- FIG. 11 is a cross-sectional view showing another example of the method for manufacturing a semiconductor device according to Example 2; 10 is a flow chart showing an example of a method for manufacturing a semiconductor device according to Example 3; FIG. 11 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to Example 3;
- FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment.
- a semiconductor device 20 includes a first semiconductor portion 8 and a second semiconductor portion 9 located in an upper layer (above) than the first semiconductor portion 8 and including an active layer.
- the first semiconductor section 8 may be a first semiconductor layer containing a nitride semiconductor (for example, a GaN-based semiconductor), and the second semiconductor section 9 may be a second semiconductor layer containing a nitride semiconductor.
- the first semiconductor portion 8 includes an upper surface 8a that is the (0001) plane and a lower surface 8b that is the (000-1) plane.
- the length of the upper surface 8a in the ⁇ 11-20> direction can be longer than the length of the lower surface 8b in the ⁇ 11-20> direction. This facilitates the manufacturing process of the semiconductor device 20 .
- FIG. 2 is a flow chart showing an example of a method for manufacturing a semiconductor device according to this embodiment.
- FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to this embodiment. 2 and 3, after the step of preparing a template substrate (ELO growth substrate) 7, an ELO film is formed on the template substrate 7 including the mask portion 5 and the mask pattern 6 including the opening K. A first semiconductor portion 8 is formed using a method. Next, a step of forming the second semiconductor portion 9 is performed. After that, the main substrate 1 is etched from its back surface to remove the portion of the main substrate 1 that overlaps the opening K of the mask pattern 6 in plan view.
- a step of removing the portion of the first semiconductor portion 8 that overlaps the opening K of the mask pattern 6 in plan view is performed. This makes it easier to separate the semiconductor device from the template substrate 7 .
- "two members overlap in plan view” means that "at least a part of one member overlaps the other in plan view (including transparent plan view) viewed in the normal direction of the main substrate 1". is.
- FIG. 4 is a block diagram showing an example of a semiconductor device manufacturing apparatus according to this embodiment.
- the formation unit 72 may include a MOCVD (Metal Organic Chemical Vapor Deposition) device, and the control unit 74 may include a processor and memory.
- the control unit 74 may be configured to control the forming unit 72 and the processing unit 73 by executing a program stored in an internal memory, a communicable communication device, or an accessible network, for example.
- the above program and a recording medium storing the above program are also included in this embodiment.
- FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment.
- a semiconductor device 20 according to Example 1 includes a first semiconductor portion 8, and is positioned on the first semiconductor portion 8 and includes an n-type semiconductor layer 9N, an active layer 9E, and a p-type semiconductor layer 9P.
- a first electrode E1 located on the p-type semiconductor layer 9P; and a second electrode E2 located on the first semiconductor part 8.
- the active layer 9E is, for example, a light emitting layer.
- the first electrode E1 is the anode.
- the second semiconductor portion 9 is provided on the first semiconductor portion 8, but the second semiconductor portion 9 is not formed above a portion of the first semiconductor portion 8, and the portion of the first semiconductor portion 8 is not formed above the portion of the first semiconductor portion 8.
- a second electrode E2 which is a cathode, may be provided so as to be in contact with the .
- the first semiconductor portion 8 includes a nitride semiconductor (eg, GaN-based semiconductor).
- a GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.
- GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N)
- the ⁇ 0001> direction (thickness direction, c-axis direction) of the GaN-based semiconductor is the Z direction
- the ⁇ 11-20> direction (a-axis direction) of the GaN-based semiconductor is the X-direction
- the ⁇ 1- 100> direction (m-axis direction) can be the Y direction.
- the first semiconductor portion 8 can be formed by an ELO (Epitaxial Lateral Overgrowth) method.
- the first semiconductor section 8 may contain an n-type dopant such as Si.
- the first semiconductor portion 8 includes an upper surface 8a that is the (0001) plane and a lower surface 8b that is the (000-1) plane.
- the second semiconductor portion 9 includes an upper surface 9a that is the (0001) plane and a lower surface 9b that is the (000-1) plane.
- the length of the upper surface 8a of the first semiconductor portion 8 in the ⁇ 11-20> direction (X direction) may be longer than the length of the lower surface 8b in the ⁇ 11-20> direction (X direction).
- the length of the ⁇ 11-20> direction (X direction) of the upper surface 9a of the second semiconductor portion 9 is less than the length of the lower surface 9b of the second semiconductor portion 9 (n-type semiconductor layer 9N).
- 11-20> direction (X direction) This facilitates the manufacturing process of the semiconductor device 20 (described later).
- semiconductor device 20 include light emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, transistors (including power transistors and high electron mobility transistors), and the like.
- LEDs light emitting diodes
- semiconductor lasers semiconductor lasers
- Schottky diodes Schottky diodes
- photodiodes transistors (including power transistors and high electron mobility transistors), and the like.
- FIG. 6 is a cross-sectional view showing the configuration of the electronic device according to the first embodiment.
- a micro LED display 30 (electronic device) includes the semiconductor device 20 described above fabricated as a red micro LED 20R, a green micro LED 20G, and a blue micro LED 20B.
- the micro LED display 30 also includes a drive board 23 on which these semiconductor devices 20 are mounted, a control circuit 25 that controls the drive board 23, and a driver circuit 29 that drives the semiconductor devices 20.
- the red micro-LED 20R, the green micro-LED 20G, and the blue micro-LED 20B are mounted on the plurality of pixel circuits 27 of the drive substrate 23 with conductive resin (for example, anisotropic conductive resin) or the like.
- conductive resin for example, anisotropic conductive resin
- a portion of the driver circuit 29 may be included in the drive substrate 23 .
- examples of electronic devices include display devices, laser emitting devices (including Fabry-Perot type and surface emitting type), lighting devices, communication devices, information processing devices, sensing devices, power control devices, and the like. can be done.
- FIG. 7 is a flow chart showing an example of a method for manufacturing a semiconductor device according to the first embodiment.
- FIG. 8 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to Example 1.
- FIG. 9 and 10 are plan views showing an example of the method for manufacturing the semiconductor device according to the first embodiment.
- a step of preparing a template substrate (ELO growth substrate) 7 is performed.
- the template substrate 7 includes the main substrate 1, the underlying portion 4, and the mask pattern 6 in this order, and the mask pattern 6 includes the mask portion 5 and the opening portion K.
- the first semiconductor section 8 is formed on the template substrate 7 using the ELO method.
- a step of forming the second semiconductor portion 9 and the first and second electrodes E1 and E2 is performed. Thereby, the semiconductor substrate 10 is formed.
- etching deep etching
- a step of removing the portion of the main substrate 1 overlapping the opening K of the mask pattern 6 in plan view is performed.
- the thickness of the main substrate 1 may be reduced by polishing the back surface of the main substrate 1 or the like. By doing so, the etching depth is reduced and the etching accuracy is improved.
- the portions of the underlying portion 4, the first semiconductor portion 8, and the second semiconductor portion 9 that overlap with the opening portion K of the mask pattern 6 in plan view are removed.
- a step of forming trenches TY extending in the direction is performed.
- the connecting portion between the base portion 4 (seed portion 3) and the first semiconductor portion 8 is removed.
- the partial removal of the first semiconductor section 8 may be followed (continuously) by the partial removal of the second semiconductor section 9 .
- Etching in this step may be dry etching or wet etching. In the case of dry etching, side etching can be suppressed. For wet etching, phosphoric acid or a mixed solution of phosphoric acid can be used.
- a GaN-based semiconductor has an N face (bottom face) and a Ga face (top face), which are polar faces, in the c-axis direction. It has a characteristic that the etching rate from the N surface ((000-1) surface), which is the lower surface, is higher. Etching (especially, dry etching) from the rear surface (lower surface) of the first semiconductor section 8 can increase the etching speed and accuracy.
- the back surface (lower surface) of the first semiconductor portion 8 is not limited to a polar surface. It may be a semipolar plane inclined from the c-plane. A combination surface of a polar surface and a semi-polar surface may be used.
- the trench TY extending in the Y direction is formed, but as shown in FIG. 10, the trench TX extending in the X direction may be formed in the same process as the formation of the trench TY.
- a step of separating the template substrate 7 and the first semiconductor portion 8 is performed. Since the adhesive force between the mask portion 5 and the first semiconductor portion 8 is weak (mainly due to von der Waals force), for example, the first and second semiconductor portions 8 and 9 are adhered to a flexible adhesive sheet. In this state, the first semiconductor section 8 can be peeled off from the mask section 5 . That is, it is easy to separate the template substrate 7 and the first semiconductor portion 8 . As a result, the first and second semiconductor parts 8 and 9, etc. are singulated, and a plurality of semiconductor devices 20 are formed.
- trench TY has a tapered shape that tapers upward (in the direction from main substrate 1 to mask pattern 6)
- the ⁇ 11-20> direction (X direction) of first semiconductor portion upper surface 8a ) is longer than the length of the first semiconductor portion lower surface 8b in the ⁇ 11-20> direction (X direction).
- the length of the second semiconductor portion upper surface 9a in the ⁇ 11-20> direction (X direction) is longer than the length of the second semiconductor portion lower surface 9b in the ⁇ 11-20> direction (X direction).
- FIG. 11 and 12 are cross-sectional views showing an example of the method for manufacturing the semiconductor device according to the first embodiment.
- the step of removing the portion of the first semiconductor portion 8 that overlaps with the opening K of the mask pattern 6 in plan view may be performed in a state where the main substrate 1 is positioned vertically upward, as shown in FIG.
- an anchor film AF for example, an inorganic film such as a silicon oxide film, a silicon nitride film, etc.
- insulating film may be formed. This reduces the risk that the first semiconductor portion 8 will drop from the mask pattern 6 when the joint portion between the first semiconductor portion 8 and the underlying portion 4 is removed.
- FIG. 13 is a plan view showing an example of a method for manufacturing a semiconductor device according to Example 1.
- the first and second electrodes E1 and E2 are arranged in the X direction in FIGS. 8 and 9, etc., the arrangement is not limited to this.
- the first and second electrodes E1 and E2 may be arranged in the Y direction.
- the area of the first electrode E1 may be larger than that of the second electrode E2.
- a heterosubstrate having a lattice constant different from that of the GaN-based semiconductor can be used for the main substrate 1 .
- hetero-substrates include single-crystal silicon (Si) substrates, sapphire (Al 2 O 3 ) substrates, silicon carbide (SiC, silicon carbide) substrates, and the like.
- the plane orientation of the main substrate 1 is, for example, the (111) plane of a silicon substrate, the (0001) plane of a sapphire substrate, and the 6H—SiC (0001) plane of a SiC substrate. These are just examples, and any main substrate and plane orientation may be used as long as the first semiconductor portion 8 can be grown by the ELO method.
- the main substrate 1 is not limited to a heterosubstrate, and may be a GaN substrate (bulk).
- the base portion 4 As the base portion 4, as shown in FIG. 8, the buffer portion 2 and the seed portion 3 can be provided in order from the main substrate 1 side.
- the base portion 4 may be a base layer.
- the buffer section 2 may be a buffer layer.
- the seed portion 3 may be a seed layer.
- the buffer section 2 has, for example, a function of reducing the direct contact between the main substrate 1 and the seed section 3 and the mutual melting. For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed portion 3, both (the main substrate and the seed layer) melt together. By providing a buffer portion 2 containing one side, melting is reduced.
- An AlN layer which is an example of the buffer section 2, can be formed to a thickness of about 10 nm to about 5 ⁇ m using, for example, an MOCVD apparatus.
- the buffer portion 2 may have at least one of the effect of increasing the crystallinity of the seed portion 3 and the effect of relieving the internal stress of the first semiconductor portion 8 (relieving the warp of the semiconductor substrate 10).
- a configuration without the buffer portion 2 is also possible.
- At least one of the buffer portion 2 (eg, aluminum nitride) and the seed portion 3 (eg, GaN-based semiconductor) can be deposited using a sputtering device (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.).
- PLD pulse sputter deposition
- PLD pulse laser deposition
- the opening K of the mask pattern 6 exposes the seed portion 3 and functions as a growth start hole for starting the growth of the first semiconductor portion 8.
- the mask portion 5 allows the first semiconductor portion 8 to grow laterally. It has the function of a mask for selective growth that allows Mask pattern 6 may be mask layer 6 .
- the opening K may be a portion without the mask portion 5 , and the opening K may not be surrounded by the mask portion 5 .
- SiOx silicon oxide film
- TiN titanium nitride film
- SiNx silicon nitride film
- SiON silicon oxynitride film
- metal film having a high melting point for example, 1000° C. or higher.
- a silicon oxide film having a thickness of about 100 nm to 4 ⁇ m (preferably about 150 nm to 2 ⁇ m) is formed on the underlying portion 4 by sputtering, and a resist is applied to the entire surface of the silicon oxide film.
- the resist is patterned by photolithography to form a resist having a plurality of striped openings.
- a part of the silicon oxide film is removed with a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings (including K), and the resist is removed by organic cleaning to form a mask.
- a pattern 6 is formed.
- the openings K have a longitudinal shape (slit shape) and are periodically arranged in the a-axis direction (X direction) of the first semiconductor portion 8 .
- the width of the opening K is about 0.1 ⁇ m to 20 ⁇ m. The smaller the width of each opening K, the smaller the number of threading dislocations propagating from each opening K to the first semiconductor portion 8 . Also, the low-defect portion in the first semiconductor portion 8 can be enlarged.
- the silicon oxide film decomposes and evaporates in small amounts during the film formation of the first semiconductor part 8, and may be incorporated into the first semiconductor part 8.
- the silicon nitride film and the silicon oxynitride film decompose at high temperatures. , has the advantage of being difficult to evaporate.
- the mask portion 5 may be a single layer film of a silicon nitride film or a silicon oxynitride film, or may be a laminated film in which a silicon oxide film and a silicon nitride film are formed in this order on the base portion 4.
- 4 may be a laminated film in which a silicon nitride film and a silicon oxide film are formed in this order, or a laminated film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order on an underlying layer.
- a good mask pattern 6 can also be formed by using a general silicon oxide film (single layer) and using such a film formation method.
- the seed portion 3 of the base portion 4 is formed by a first layer of Al 0.6 Ga 0.4 N layer (for example, 300 nm) and a second layer of GaN layer (for example, 1 to 2 ⁇ m), which are formed in this order. and graded layer.
- a layered body in which a silicon oxide film (SiO 2 ) and a silicon nitride film (SiN) are formed in this order is used for the mask portion 5 .
- the thickness of the silicon oxide film is, for example, 0.3 ⁇ m, and the thickness of the silicon nitride film is, for example, 70 nm.
- a plasma-enhanced chemical vapor deposition (CVD) method was used to form each of the silicon oxide film and the silicon nitride film.
- the first semiconductor portion 8 is formed by an ELO (Epitaxial Lateral Overgrowth) method, overlaps the mask portion 5 in plan view, and includes a low dislocation portion SD with relatively few threading dislocations and an opening K of the mask pattern 6 in plan view. and includes a high dislocation portion HD having relatively more threading dislocations than a low dislocation portion (see FIG. 8).
- the threading dislocation density of the low dislocation portion SD may be 1 ⁇ 5 or less of the threading dislocation density of the high dislocation portion HD.
- the threading dislocation density of the low dislocation portion SD may be 5 ⁇ 10 6 /cm 2 or less. In the low dislocation portion SD, the non-threading dislocation density may be higher than the threading dislocation density.
- Threading dislocations are dislocations (defects) that extend from the lower surface or inside of the first semiconductor part 8 to its surface or superficial layer along the thickness direction (Z direction) of the first semiconductor part 8 . Threading dislocations can be observed by performing CL (Cathode Luminescence) measurement on the surface layer (parallel to the c-plane) of the first semiconductor portion 8 .
- Non-threading dislocations are dislocations that are CL-measured in a cross section along a plane (eg, m-plane) parallel to the thickness direction, and are mainly basal plane (c-plane) dislocations.
- the luminous efficiency of the active layer 9E can be increased by overlapping the light emitting region (the portion under the anode) of the active layer 9E with the low dislocation portion SD in plan view. This is because the portion of the second semiconductor portion 9 that overlaps the low dislocation portion SD in plan view inherits the low dislocation property of the first semiconductor portion 8 .
- the first semiconductor portion 8 was a GaN layer, and an ELO film of gallium nitride (GaN) was formed on the template substrate 7 using the MOCVD apparatus provided in the formation portion 72 .
- the first semiconductor portion 8 is selectively grown (vertically grown) on the seed portion 3 (the GaN layer that is the second layer) exposed in the opening K, and subsequently grown laterally on the mask portion 5 . . Then, the lateral growth was stopped before the first semiconductor portion 8 growing laterally from both sides of the mask portion 5 joined together.
- the width Wm of the mask portion 5 is 50 ⁇ m
- the width of the opening K is 5 ⁇ m
- the width of the first semiconductor portion 8 is 53 ⁇ m
- the width of the low defect portion (size in the X direction) is 24 ⁇ m
- the layer thickness of the first semiconductor portion 8 is was 5 ⁇ m.
- the lateral film formation rate is increased.
- a technique for increasing the lateral film formation rate is as follows. First, a vertical growth layer growing in the Z direction (c-axis direction) is formed on the seed portion 3 exposed from the opening K, and then a lateral growth layer growing in the X direction (a-axis direction) is formed. At this time, by setting the thickness of the vertical growth layer to 10 ⁇ m or less, preferably 5 ⁇ m or less, and more preferably 3 ⁇ m or less, the thickness of the horizontal growth layer can be kept low and the horizontal film formation rate can be increased.
- the second semiconductor section 9 includes an n-type semiconductor layer 9N, an active layer 9E, and a p-type semiconductor layer 9P in order from the lower layer side.
- the active layer 9E is, for example, an MQW (Multi-Quantum Well) structure and contains, for example, InGaN or GaN.
- the n-type semiconductor layer 9N is, for example, an AlGaN layer.
- the p-type semiconductor layer 9P is, for example, a p-type GaN layer.
- a first electrode E1, which is an anode, is arranged so as to be in contact with the p-type semiconductor layer 9P.
- the first and second semiconductor parts 8 and 9 may be continuously formed by the same apparatus (for example, MOCVD apparatus), or after the formation of the first semiconductor part 8, the substrate is once removed from the apparatus and the surface of the first semiconductor part 8 is removed.
- the second semiconductor section 9 may be formed after performing polishing or the like.
- a sputtering apparatus in addition to the MOCVD apparatus, a sputtering apparatus, a remote plasma CVD apparatus (RPCVD), a PSD (Pulse Sputter Deposition) apparatus, or the like can be used. Since the remote plasma CVD apparatus and the PSD apparatus do not use hydrogen as a carrier gas, a p-type GaN-based semiconductor with low resistance can be formed.
- the MQW structure of the active layer 9E can be, for example, a structure of 5 to 6 cycles of InGaN/GaN.
- the In composition differs depending on the target emission wavelength. For blue (around 450 nm), the In concentration can be about 15-20%, and for green (about 530 nm), the In concentration can be about 30%.
- An electron blocking layer eg, AlGaN layer
- the surface (about 10 nm) of the p-type semiconductor layer 9P may be a p-type highly doped layer.
- the first and second electrodes E1 and E2 have, for example, a single layer structure containing at least one of Au, Ag, Pd, Pt, Ni, Ti, V, W, Cr, Al, Cu, Zn, Sn and In, or It may have a multilayer structure.
- FIG. 14 and 15 are cross-sectional views showing another example of the semiconductor device manufacturing method according to the first embodiment.
- the underlying portion 4 is formed entirely on the main substrate 1, but the present invention is not limited to this.
- the underlying portion 4 can also be locally formed so as to overlap with the opening portion K of the mask pattern 6 in plan view.
- FIG. 15 by using, for example, a GaN substrate (bulk crystal of GaN) or a 6H—SiC substrate as the main substrate 1, the base portion 4 is not provided, and the upper surface of the main substrate 1 is used as a seed.
- One semiconductor portion 8 can also be grown.
- the template substrate 7 including the main substrate 1 and the mask pattern 6 on the main substrate 1 may be used.
- the template substrate 7 may have a growth suppression region (for example, a region for suppressing crystal growth in the Z direction) corresponding to the mask portion 5 and a seed region corresponding to the opening K.
- a growth suppression region and a seed region can be formed on the main substrate 1, and the first semiconductor section 8 can be formed on the growth suppression region and the seed region using the ELO method.
- FIG. 16 is a flow chart showing an example of a method for manufacturing a semiconductor device according to the second embodiment.
- 17A and 17B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the second embodiment.
- a step of preparing a template substrate (ELO growth substrate) 7 is performed.
- the template substrate includes a main substrate 1, an underlying portion 4 and a mask pattern 6 in this order, and the mask pattern 6 includes the mask portion 5 and the opening K.
- the first semiconductor section 8 is formed on the template substrate 7 using the ELO method.
- a step of forming the second semiconductor portion 9 and the first and second electrodes E1 and E2 is performed.
- a step of removing the entire main substrate 1 and a step of removing the entire base portion 4 are performed.
- the mask portion 5, which is a selective growth mask, is used (made to function) as an etching mask, and the portions of the first and second semiconductor portions 8 and 9 overlapping the opening portion K of the mask pattern 6 in plan view are removed. carry out the process.
- a step of removing the mask portion 5 using hydrogen fluoride (HF) is performed.
- HF hydrogen fluoride
- FIG. 18 and 19 are cross-sectional views showing another example of the semiconductor device manufacturing method according to the second embodiment.
- the underlying portion 4 is formed entirely on the main substrate 1, but it is not limited to this.
- the underlying portion 4 can also be locally formed so as to overlap with the opening portion K of the mask pattern 6 in plan view.
- FIG. 19 by using, for example, a GaN substrate (bulk crystal of GaN) or a 6H—SiC substrate as the main substrate 1, the base portion 4 is not provided, and the upper surface of the main substrate 1 is used as a seed.
- One semiconductor portion 8 can also be grown.
- FIG. 20 is a flow chart showing another example of the semiconductor device manufacturing method according to the second embodiment.
- FIG. 21 is a cross-sectional view showing another example of the semiconductor device manufacturing method according to the second embodiment.
- 20 and 21 after the semiconductor substrate 10 including the first and second semiconductor portions 8 and 9 is formed, the support substrate FK is bonded to the opposite side of the main substrate 1. As shown in FIG. As a result, the first and second semiconductor parts 8 and 9 and the first and second electrodes E and E2 are held by the support substrate FK. After that, the entire main substrate 1 is removed. This facilitates handling after the main substrate 1 is removed. In this case, the mounting process can be omitted by using the support substrate FK as a mounting substrate (sub-mount substrate or driving substrate). Note that the first and second semiconductor parts 8 and 9 may be transferred from the support substrate FK to another mounting substrate.
- FIG. 22 is a flow chart showing an example of a method for manufacturing a semiconductor device according to the third embodiment.
- 23A and 23B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.
- a step of preparing a template substrate (ELO growth substrate) 7 is performed.
- the first semiconductor section 8 is formed on the template substrate 7 using the ELO method.
- a step of forming the second semiconductor portion 9 and the first and second electrodes E1 and E2 is performed.
- the main substrate 1 is etched (deep etching) from its back surface to remove the portion of the main substrate 1 that overlaps the opening K of the mask pattern 6 in plan view.
- the portions of the underlying portion 4, the first semiconductor portion 8, and the second semiconductor portion 9 that overlap with the opening portion K of the mask pattern 6 in plan view are removed. Then, a step of forming trenches TY extending in the direction is performed. Thereafter, a step of removing the entire main substrate 1 and a step of separating the first semiconductor portion 8 from the mask pattern 6 are performed.
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Abstract
Description
図1は、本実施形態に係る半導体デバイスの構成を示す断面図である。図1に示すように、本実施形態に係る半導体デバイス20は、第1半導体部8と、第1半導体部8よりも上層(上方)に位置し、活性層を含む第2半導体部9とを備える。第1半導体部8は、窒化物半導体(例えば、GaN系半導体)を含む第1半導体層であってもよく、第2半導体部9は窒化物半導体を含む第2半導体層であってもよい。第1半導体部8は、(0001)面である上面8aと、(000-1)面である下面8bとを含む。半導体デバイス20では、上面8aの<11-20>方向の長さが、下面8bの<11-20>方向の長さよりも大きい構成とすることができる。こうすれば、半導体デバイス20の製造工程が容易になる。
図2は、本実施形態に係る半導体デバイスの製造方法の一例を示すフローチャートである。図3は、本実施形態に係る半導体デバイスの製造方法の一例を示す断面図である。図2および図3の半導体デバイスの製造方法では、テンプレート基板(ELO成長用基板)7を準備する工程の後に、マスク部5および開口部Kを含むマスクパターン6を含むテンプレート基板7上に、ELO法を用いて第1半導体部8を形成する。次いで、第2半導体部9を形成する工程を行う。その後、主基板1をその裏面からエッチングすることで、主基板1の、平面視でマスクパターン6の開口部Kと重なる部分を除去する工程を行う。その後、第1半導体部8の、平面視でマスクパターン6の開口部Kと重なる部分を除去する工程を行う。これにより、テンプレート基板7から半導体デバイスを離隔させ易くできる。なお、「平面視で2つの部材が重なる」とは、「主基板1の法線方向に視る平面視(透視的平面視を含む)において一方の部材の少なくとも一部が他方と重なる」ことである。
(全体構成)
図5は、実施例1に係る半導体デバイスの構成を示す断面図である。図5に示すように、実施例1に係る半導体デバイス20は、第1半導体部8と、第1半導体部8上に位置し、n型半導体層9N、活性層9Eおよびp型半導体層9Pを含む第2半導体部9と、p型半導体層9P上に位置する第1電極E1と、第1半導体部8上に位置する第2電極E2とを備える。活性層9Eは、例えば発光層である。第1電極E1はアノードである。第2半導体部9は第1半導体部8上に設けられるが、第1半導体部8の一部の上方には第2半導体部9が形成されておらず、この第1半導体部8の一部と接するように、カソードである第2電極E2が設けられていてよい。
図6は、実施例1に係る電子機器の構成を示す断面図である。図6に示すように、マイクロLEDディスプレイ30(電子機器)は、赤色マイクロLED20R、緑色マイクロLED20G、青色マイクロLED20Bとして作製された上記の半導体デバイス20を含む。また、マイクロLEDディスプレイ30は、これらの半導体デバイス20を実装する駆動基板23と、駆動基板23を制御する制御回路25と、半導体デバイス20を駆動するドライバ回路29とを含む。赤色マイクロLED20R、緑色マイクロLED20G、青色マイクロLED20Bは、駆動基板23の複数の画素回路27に、導電樹脂(例えば異方性導電樹脂)等により実装される。ドライバ回路29の一部は、駆動基板23に含まれていてもよい。
主基板1には、GaN系半導体と異なる格子定数を有する異種基板を用いることができる。異種基板としては、単結晶のシリコン(Si)基板、サファイア(Al2O3)基板、シリコンカーバイド(SiC,炭化シリコン)基板等を挙げることができる。主基板1の面方位は、例えば、シリコン基板の(111)面、サファイア基板の(0001)面、SiC基板の6H-SiC(0001)面である。これらは例示であって、第1半導体部8をELO法で成長させることができる主基板および面方位であれば何でもよい。主基板1は、異種基板に限定されず、GaN基板(バルク)でもよい。
下地部4としては、図8に示すように、主基板1側から順に、バッファ部2およびシード部3を設けることができる。下地部4が下地層であってもよい。バッファ部2がバッファ層であってもよい。シード部3がシード層であってもよい。
マスクパターン6の開口部Kは、シード部3を露出させ、第1半導体部8の成長を開始させる成長開始用ホールの機能を有し、マスク部5は、第1半導体部8を横方向成長させる選択成長用マスクの機能を有する。マスクパターン6は、マスク層6であってもよい。開口部Kはマスク部5がない部分であってよく、開口部Kがマスク部5で囲まれていなくてもよい。
主基板1には、(111)面を有するシリコン基板を用い、下地部4のバッファ部2は、AlN層(例えば、30nm)とした。下地部4のシード部3は、第1層であるAl0.6Ga0.4N層(例えば、300nm)と、第2層であるGaN層(例えば、1~2μm)とがこの順に形成されたグレーデット層とした。
第1半導体部8は、ELO(Epitaxial Lateral Overgrowth)法によって形成され、平面視でマスク部5と重なり、相対的に貫通転位の少ない低転位部SDと、平面視においてマスクパターン6の開口部Kと重なり、低転位部よりも相対的に貫通転位の多い高転位部HDとを含む(図8参照)。低転位部SDの貫通転位密度は、高転位部HDの貫通転位密度の1/5以下であってもよい。低転位部SDの貫通転位密度が、5×106/cm2以下であってもよい。低転位部SDでは、貫通転位密度よりも非貫通転位密度の方が大きくてもよい。
第2半導体部9は、図5に示すように、下層側から順に、n型半導体層9Nと、活性層9Eと、p型半導体層9Pとを含む。活性層9Eは、例えば、MQW(Multi-Quantum Well)構造であり、例えば、InGaNまたはGaNを含む。n型半導体層9Nは、例えばAlGaN層である。p型半導体層9Pは、例えばp型のGaN層である。アノードである第1電極E1は、p型半導体層9Pと接触するように配される。
図16は、実施例2に係る半導体デバイスの製造方法の一例を示すフローチャートである。図17は、実施例2に係る半導体デバイスの製造方法の一例を示す断面図である。図16および図17の半導体デバイスの製造方法では、テンプレート基板(ELO成長用基板)7を準備する工程を行う。テンプレート基板は、主基板1、下地部4およびマスクパターン6をこの順に備え、マスクパターン6は、マスク部5および開口部Kを含む。その後、テンプレート基板7上に、ELO法を用いて第1半導体部8を形成する。次いで、第2半導体部9並びに第1および第2電極E1・E2を形成する工程を行う。
図22は、実施例3に係る半導体デバイスの製造方法の一例を示すフローチャートである。図23は、実施例3に係る半導体デバイスの製造方法の一例を示す断面図である。図22および図23の半導体デバイスの製造方法では、テンプレート基板(ELO成長用基板)7を準備する工程を行う。その後、テンプレート基板7上に、ELO法を用いて第1半導体部8を形成する。次いで、第2半導体部9並びに第1および第2電極E1・E2を形成する工程を行う。その後、主基板1をその裏面からエッチング(深堀エッチング)することで、主基板1のうち、平面視でマスクパターン6の開口部Kと重なる部分を除去する工程を行う。その後、主基板1の残余の部分をエッチングマスクとして、下地部4、第1半導体部8および第2半導体部9のうち、平面視でマスクパターン6の開口部Kと重なる部分を除去し、Y方向に伸びるトレンチTYを形成する工程を行う。その後、主基板1の全部を除去する工程と、第1半導体部8をマスクパターン6から離隔する工程とを行う。
以上、本開示に係る発明について、諸図面および実施例に基づいて説明してきた。しかし、本開示に係る発明は上述した各実施形態に限定されるものではない。すなわち、本開示に係る発明は本開示で示した範囲で種々の変更が可能であり、異なる実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本開示に係る発明の技術的範囲に含まれる。つまり、当業者であれば本開示に基づき種々の変形または修正を行うことが容易であることに注意されたい。また、これらの変形または修正は本開示の範囲に含まれることに留意されたい。
3 シード部
4 下地部
5 マスク部
6 マスクパターン
7 テンプレート基板
8 第1半導体部
9 第2半導体部
9E 活性層
20 半導体デバイス
30 マイクロLEDディスプレイ(電子機器)
70 製造装置
72 形成部
73 加工部
E1 第1電極
E2 第2電極
K 開口部
FK 支持基板
Claims (21)
- 主基板と、前記主基板よりも上方に位置し、マスク部および開口部を含むマスクパターンとを有したテンプレート基板を準備する工程と、
前記マスクパターン上に第1半導体部を形成する工程と、
前記主基板のうち、平面視で前記開口部と重なる部分を除去する工程と、
前記第1半導体部のうち、平面視で前記開口部と重なる部分を除去する工程と、を含む、半導体デバイスの製造方法。 - 前記主基板を部分的に除去し、前記主基板の残余の部分をエッチングマスクとして前記第1半導体部を除去する、請求項1に記載の半導体デバイスの製造方法。
- 前記第1半導体部を部分的に除去する工程の前に、前記主基板の全部を除去する、請求項1または2記載の半導体デバイスの製造方法。
- 前記主基板の全部を除去し、前記マスク部をエッチングマスクとして前記第1半導体部を除去する、請求項1に記載の半導体デバイスの製造方法。
- 前記第1半導体部よりも上層に第2半導体部を形成する工程を含み、
前記第2半導体部のうち、平面視で前記開口部と重なる部分を除去する、請求項1~4のいずれか1項に記載の半導体デバイスの製造方法。 - 前記第1半導体部を部分的に除去する工程に続いて、前記第2半導体部を部分的に除去する、請求項5に記載の半導体デバイスの製造方法。
- 前記テンプレート基板を準備する工程において、前記主基板と前記マスクパターンとの間に下地層を有したテンプレート基板を準備し、
前記下地層のうち、少なくとも平面視で前記開口部と重なる部分を除去する工程を含む、請求項1~6のいずれか1項に記載の半導体デバイスの製造方法。 - 前記主基板を部分的に除去する工程の前に、
前記主基板の裏面を研磨して厚みを減少させる工程を含む、請求項2に記載の半導体デバイスの製造方法。 - 前記第1半導体部は窒化物半導体を含み、
前記第1半導体部を部分的に除去する工程では、前記第1半導体部の(000-1)面からエッチングを行う、請求項1~8のいずれか1項に記載の半導体デバイスの製造方法。 - 支持基板によって前記第1半導体部を支持する工程をさらに含む、請求項4に記載の半導体デバイスの製造方法。
- 前記支持基板が実装基板である、請求項10に記載の半導体デバイスの製造方法。
- 前記第1半導体部を部分的に除去する工程の後に、前記第1半導体部と前記マスクパターンとを離隔する、請求項1~11のいずれか1項に記載の半導体デバイスの製造方法。
- 前記第1半導体部を部分的に除去する工程の後に、前記主基板の全部を除去する、請求項1または2記載の半導体デバイスの製造方法。
- 前記マスク部は選択成長用マスクであり、
前記第1半導体部がGaN系半導体を含み、
前記主基板が、シリコン基板または炭化シリコン基板である、請求項1~13のいずれか1項に記載の半導体デバイスの製造方法。 - 前記下地層は、平面視で前記開口部と重なるシード部を含み、
前記第1半導体部を部分的に除去する工程では、前記シード部と前記第1半導体部との結合部を除去する、請求項7に記載の半導体デバイスの製造方法。 - 前記第1半導体部を部分的に除去する工程の前に、前記マスク部並びに前記第1半導体部の上面および側面に接するアンカー膜を形成する、請求項1に記載の半導体デバイスの製造方法。
- 主基板よりも上層にマスク部および開口部を含むマスクパターンを形成した後に、ELO法を用いて前記マスクパターン上に第1半導体部を形成する形成部と、
前記主基板のうち、少なくとも平面視で前記開口部と重なる部分を除去した後に、前記第1半導体部のうち、平面視で前記開口部と重なる部分を除去する加工部と、を備える、半導体デバイスの製造装置。 - GaN系半導体を含む第1半導体部と、前記第1半導体部よりも上層に位置する活性層とを備えた半導体デバイスであって、
前記第1半導体部は、(0001)面である上面と、(000-1)面である下面とを含み、
前記第1半導体部上面の<11-20>方向の長さが、前記第1半導体部下面の<11-20>方向の長さよりも大きい、半導体デバイス。 - 前記第1半導体部上に、前記活性層を含む第2半導体部を備え、
前記第2半導体部に接する第1電極と、前記第1半導体部に接する第2電極とを含む、請求項18に記載の半導体デバイス。 - 前記第2半導体部は、(0001)面である上面と、(000-1)面である下面とを含み、
前記第2半導体部上面の<11-20>方向の長さが、前記第2半導体部下面の<11-20>方向の長さよりも大きい、請求項19に記載の半導体デバイス。 - 請求項18~20のいずれか1項に記載の半導体デバイスを含む電子機器。
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Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6218730A (ja) * | 1985-07-17 | 1987-01-27 | Nec Corp | 半導体装置の製造方法 |
JPH1145892A (ja) | 1997-05-28 | 1999-02-16 | Sony Corp | 半導体装置およびその製造方法 |
JP2002231734A (ja) * | 2001-02-06 | 2002-08-16 | Oki Data Corp | 基板ユニット、半導体素子、半導体素子の実装方法及びその製造方法 |
JP2005244172A (ja) * | 2004-01-30 | 2005-09-08 | Sumitomo Electric Ind Ltd | 半導体素子の製造方法 |
WO2005106977A1 (ja) * | 2004-04-27 | 2005-11-10 | Matsushita Electric Industrial Co., Ltd. | 窒化物半導体素子およびその製造方法 |
JP2006273716A (ja) * | 1997-10-30 | 2006-10-12 | Sumitomo Electric Ind Ltd | GaN単結晶基板の製造方法 |
JP2008226871A (ja) * | 2007-03-08 | 2008-09-25 | Nec Corp | 半導体装置及びその製造方法 |
JP2012114263A (ja) * | 2010-11-25 | 2012-06-14 | Pawdec:Kk | 半導体素子およびその製造方法 |
JP2020202351A (ja) * | 2019-06-13 | 2020-12-17 | 日亜化学工業株式会社 | 発光素子の製造方法 |
US20210090885A1 (en) * | 2018-05-17 | 2021-03-25 | The Regents Of The University Of California | Method for dividing a bar of one or more devices |
JP6986645B1 (ja) * | 2020-12-29 | 2021-12-22 | 京セラ株式会社 | 半導体基板、半導体デバイス、電子機器 |
-
2022
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- 2022-06-08 EP EP22828226.5A patent/EP4362115A1/en active Pending
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Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6218730A (ja) * | 1985-07-17 | 1987-01-27 | Nec Corp | 半導体装置の製造方法 |
JPH1145892A (ja) | 1997-05-28 | 1999-02-16 | Sony Corp | 半導体装置およびその製造方法 |
JP2006273716A (ja) * | 1997-10-30 | 2006-10-12 | Sumitomo Electric Ind Ltd | GaN単結晶基板の製造方法 |
JP2002231734A (ja) * | 2001-02-06 | 2002-08-16 | Oki Data Corp | 基板ユニット、半導体素子、半導体素子の実装方法及びその製造方法 |
JP2005244172A (ja) * | 2004-01-30 | 2005-09-08 | Sumitomo Electric Ind Ltd | 半導体素子の製造方法 |
WO2005106977A1 (ja) * | 2004-04-27 | 2005-11-10 | Matsushita Electric Industrial Co., Ltd. | 窒化物半導体素子およびその製造方法 |
JP2008226871A (ja) * | 2007-03-08 | 2008-09-25 | Nec Corp | 半導体装置及びその製造方法 |
JP2012114263A (ja) * | 2010-11-25 | 2012-06-14 | Pawdec:Kk | 半導体素子およびその製造方法 |
US20210090885A1 (en) * | 2018-05-17 | 2021-03-25 | The Regents Of The University Of California | Method for dividing a bar of one or more devices |
JP2020202351A (ja) * | 2019-06-13 | 2020-12-17 | 日亜化学工業株式会社 | 発光素子の製造方法 |
JP6986645B1 (ja) * | 2020-12-29 | 2021-12-22 | 京セラ株式会社 | 半導体基板、半導体デバイス、電子機器 |
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