WO2024113650A1 - 一种实现模拟触发的示波器 - Google Patents

一种实现模拟触发的示波器 Download PDF

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Publication number
WO2024113650A1
WO2024113650A1 PCT/CN2023/089487 CN2023089487W WO2024113650A1 WO 2024113650 A1 WO2024113650 A1 WO 2024113650A1 CN 2023089487 W CN2023089487 W CN 2023089487W WO 2024113650 A1 WO2024113650 A1 WO 2024113650A1
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Prior art keywords
trigger
signal
edge
clock
analog
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PCT/CN2023/089487
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English (en)
French (fr)
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陈报
宋民
李振军
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深圳市鼎阳科技股份有限公司
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Publication of WO2024113650A1 publication Critical patent/WO2024113650A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms
    • G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
    • G01R13/0218—Circuits therefor
    • G01R13/0254—Circuits therefor for triggering, synchronisation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
    • G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
    • G01R29/0276—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being rise time

Definitions

  • the invention relates to the technical field of digital oscilloscopes, and in particular to an oscilloscope for realizing analog triggering.
  • analog trigger channels that is, external trigger channels
  • analog triggers are discrete systems
  • analog triggers are continuous signal triggers
  • the main technical problem solved by the present invention is how to determine the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal under analog triggering.
  • an oscilloscope for implementing analog triggering comprising:
  • a data acquisition module is used to collect data of the signal input by the signal channel
  • the analog trigger channel is used to obtain a trigger input signal and compare the trigger input signal with a preset trigger level to obtain an analog trigger signal;
  • a trigger module comprising a trigger pulse expansion circuit and a digital TDC circuit
  • the trigger pulse extension circuit is used to delay and adjust the trigger edge of the analog trigger signal after starting to collect data from the signal input into the signal channel, so as to obtain a third trigger synchronization signal, wherein the trigger edge of the third trigger synchronization signal is synchronized with the clock edge of the clock signal of the oscilloscope; the trigger pulse extension circuit is also used to generate a trigger pulse signal according to the trigger edge of the analog trigger synchronization signal and the trigger edge of the third trigger synchronization signal, wherein the rising edge of the trigger pulse signal is the trigger edge of the analog trigger synchronization signal, and the falling edge of the trigger pulse signal is the trigger edge of the third trigger synchronization signal;
  • the digital TDC circuit is used to obtain the pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope contained in the pulse width of the trigger pulse signal, and determine the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope contained in the pulse width of the trigger pulse signal;
  • a compensation module is used to adjust the trigger edge of the analog trigger signal based on the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal, so that the trigger edge of the analog trigger signal is synchronized with the clock edge of the clock signal.
  • the trigger module in the oscilloscope includes a trigger pulse expansion circuit and a digital TDC circuit.
  • the trigger pulse expansion circuit is used to convert the analog trigger signal into a trigger pulse signal. Since the pulse width of the trigger pulse signal includes the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal and a fixed number of clock signal cycles, the digital TDC circuit determines the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal according to the pulse width of the trigger pulse signal and the number of clock signal cycles of the oscilloscope included in the pulse width of the trigger pulse signal.
  • the compensation module can adjust the trigger edge of the analog trigger signal so that the trigger edge of the analog trigger signal is synchronized with the clock edge of the clock signal, thereby solving the problem of jitter of the sampled waveform during analog triggering.
  • FIG1 is a schematic diagram of measuring the time difference between the trigger edge of an analog trigger signal and the clock edge of a clock signal by using an analog TDC technology
  • FIG2 is a schematic diagram of measuring the time difference between the trigger edge of an analog trigger signal and the clock edge of a clock signal by using a high-speed clock multi-phase sampling technique
  • FIG3 is a schematic diagram of the structure of a trigger module of an oscilloscope according to an embodiment
  • FIG. 4 is a schematic diagram of a clock signal, an analog trigger signal w, a first trigger synchronization signal w1, a second trigger synchronization signal w2, a third trigger synchronization signal w3 and a trigger pulse signal p;
  • FIG5 is a schematic diagram of the structure of a digital TDC circuit according to an embodiment
  • FIG6 is a schematic diagram showing the principle of existence of a metastable state
  • FIG7 is a schematic structural diagram of a digital TDC circuit according to another embodiment.
  • FIG8 is a decoding timing diagram
  • FIG9 is a schematic diagram of a clock signal, signals of various delay taps and a valid signal valid1;
  • FIG10 is a schematic diagram of a clock signal, signals of various delay taps and a valid signal valid2;
  • FIG11 is a schematic diagram of the waveform of the oscilloscope under analog triggering.
  • connection and “coupling” mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).
  • FIG. 1 shows an example of measuring the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal by analog TDC technology.
  • the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal is ⁇ T.
  • the pulse signal composed of the analog trigger signal and the analog trigger synchronization signal is sent to the analog TDC circuit for widening to obtain ⁇ t.
  • ⁇ t the distance from the analog trigger signal to the clock edge can be calculated.
  • this method requires additional hardware analog circuit support.
  • the components in the analog circuit are easily affected by temperature, which affects the final output result.
  • FIG 2 shows an example of measuring the time difference from the trigger edge of the analog trigger signal to the clock edge of the clock signal through the high-speed clock multi-phase sampling technology.
  • clock 1 is the FPGA master clock
  • a higher-speed clock 2 can be used to sample the analog trigger signal.
  • Clock 1 and clock 2 have a certain relationship, assuming it is 1:2.
  • the sampling frequency can be increased and multiple phases can be used to sample the analog trigger signal.
  • the distance from the trigger edge of the analog trigger signal to the clock edge is analyzed based on the obtained results.
  • the sampling frequency of 1G only has a resolution of 1ns, assuming a resolution of 20ps is required, the sampling clock needs a speed of 50G, and the FPGA cannot support such a high sampling speed.
  • an embodiment of the present invention converts an analog trigger signal into a trigger pulse signal, and determines the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of cycles of the clock signal contained therein, and implements the analog trigger function through a digital circuit, and integrates the digital circuit into the FPGA chip of the oscilloscope, without the need for additional hardware analog circuits.
  • An embodiment of the present invention provides an oscilloscope for implementing analog triggering, hereinafter referred to as the oscilloscope, and the oscilloscope includes: a data acquisition module, an analog trigger channel, a trigger module and a compensation module, wherein the data acquisition module is used to perform data acquisition on a signal input by a signal channel; the analog trigger channel is used to obtain a trigger input signal, and compare the trigger input signal with a preset trigger level to obtain an analog trigger signal; the trigger module is used to determine the time difference between a trigger edge of the analog trigger signal and a clock edge of a clock signal; the compensation module is used to adjust the trigger edge of the analog trigger signal based on the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal, so that the trigger edge of the analog trigger signal is synchronized with the clock edge of the clock signal.
  • the trigger module includes a T trigger 101, a first two-choice switch 102, a trigger pulse expansion circuit 103, a second two-choice switch 104 and a digital TDC circuit 105, which is described in detail below.
  • the T trigger 101 is used to clear the output when starting to collect data for the signal input into the signal channel, and receive and output the analog trigger signal after the pre-trigger depth is full.
  • the D pin of the T trigger 101 is connected to the power supply VCC
  • the C pin (input pin) of the T trigger 101 is used to receive the analog trigger signal
  • the CE pin of the T trigger 101 is used to obtain the pre-trigger signal
  • the RS pin of the T trigger 101 is used to obtain the acquisition start signal, wherein the acquisition start signal is used to indicate that the data acquisition module of the oscilloscope starts data acquisition.
  • the analog trigger signal is output through an analog comparator, which includes a positive input terminal and an inverting input terminal.
  • the positive input terminal is used to obtain an external trigger input signal
  • the inverting input terminal is used to obtain a preset trigger level.
  • the analog comparator is used to compare the trigger input signal with the preset trigger level and output an analog trigger signal.
  • the first two-to-one switch 102 includes a first end, a second end and a third end.
  • the first end of the first two-to-one switch 102 is used to obtain the analog trigger signal output by the T trigger
  • the second end of the first two-to-one switch 102 is used to obtain the digital trigger signal
  • the third end of the first two-to-one switch 102 is connected to the input end of the trigger pulse expansion circuit.
  • the third end is used to output an analog trigger signal or a digital trigger signal under the trigger of the trigger selection signal, that is, the first two-to-one switch 102 is used to switch the trigger mode between analog triggering and digital triggering.
  • the trigger pulse expansion circuit 103 is used to delay and adjust the trigger edge of the analog trigger signal after starting to collect data from the signal input to the signal channel, so as to obtain a third trigger synchronization signal; wherein the trigger edge of the third trigger synchronization signal is synchronized with the clock edge of the clock signal of the oscilloscope.
  • the clock signal of the oscilloscope refers to the local clock signal used by the oscilloscope for sampling, which is generated by the FPGA.
  • the trigger pulse expansion circuit 103 is also used to generate a trigger pulse signal according to the trigger edge of the analog trigger synchronization signal and the trigger edge of the third trigger synchronization signal, the rising edge of the trigger pulse signal is the trigger edge of the analog trigger synchronization signal, and the falling edge of the trigger pulse signal is the trigger edge of the third trigger synchronization signal.
  • the second two-to-one switch 104 includes a first end, a second end and a third end.
  • the first end of the second two-to-one switch 104 is used to obtain a trigger pulse signal
  • the second end of the second two-to-one switch 104 is used to obtain a calibration sequence signal
  • the third end of the second two-to-one switch 104 is connected to the input end of the digital TDC circuit, and the third end is used to correct the trigger pulse signal under the triggering of the correction selection signal.
  • the digital TDC circuit 105 is used to obtain the pulse width of the trigger pulse signal and the number of oscilloscope clock signal cycles contained in the pulse width of the trigger pulse signal, and determine the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal based on the pulse width of the trigger pulse signal and the number of oscilloscope clock signal cycles contained in the pulse width of the trigger pulse signal.
  • the trigger module provided in the embodiment of the present invention is a digital circuit and can be directly integrated into the FPGA of the oscilloscope. No external analog circuit is required to measure the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal. The measurement accuracy is high and is not affected by environmental factors such as temperature.
  • the trigger pulse expansion circuit 103 and the digital TDC circuit 105 are described in detail below.
  • the trigger pulse expansion circuit 103 delays and adjusts the trigger edge of the analog trigger signal to obtain a third trigger synchronization signal, including: obtaining the period of the clock signal at which the trigger edge of the analog trigger signal is located, and using the clock signal corresponding to the period of the obtained clock signal as the synchronization clock signal; based on the synchronization clock signal, generating a first trigger synchronization signal, the trigger edge of the first trigger synchronization signal is synchronized with the clock edge of the synchronization clock signal; based on the first trigger synchronization signal, generating a second trigger synchronization signal, the trigger edge of the second trigger synchronization signal is delayed by one clock signal period relative to the trigger edge of the first trigger synchronization signal; based on the second trigger synchronization signal, generating a third trigger synchronization signal, the trigger edge of the third trigger synchronization signal is delayed by one clock signal period relative to the trigger edge of the second trigger synchronization signal.
  • FIG 4 is a timing diagram of a clock signal, an analog trigger signal w, a first trigger synchronization signal w1, a second trigger synchronization signal w2, a third trigger synchronization signal w3 and a trigger pulse signal p.
  • the trigger edge of the analog trigger signal falls within the holding time window of the clock edge, it can be considered to be synchronized with the clock edge of the clock signal, wherein the holding time window of the clock edge is a preset time range centered on the clock edge.
  • the trigger edge of the third trigger synchronization signal is not completely aligned with the clock edge of the clock signal, and the time difference between it and the clock edge is T4, but considering the holding time window of the clock edge, the trigger edge of the third trigger synchronization signal is also considered to be synchronized with the clock edge of the clock signal.
  • T3 is the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal. Considering the holding window time, T3 is not the complete time difference between the trigger edge and the clock edge.
  • the T time interval in FIG4 represents the interval in which the analog trigger signal may appear.
  • the trigger edge of the third trigger synchronization signal is synchronized with the clock edge of the clock signal of the oscilloscope, including: the trigger edge of the third trigger synchronization signal is within the hold time window of the clock edge of the clock signal of the oscilloscope; the trigger edge of the first trigger synchronization signal is synchronized with the clock edge of the synchronization clock signal, including: the trigger edge of the first trigger synchronization signal is within the hold time window of the clock edge of the synchronization clock signal.
  • the trigger pulse expansion circuit 103 can be implemented by a digital circuit, for example, it can be implemented by three D flip-flops, the first trigger synchronization signal is a signal output by one D flip-flop, the second trigger synchronization signal is a signal output by two D flip-flops, and the third trigger synchronization signal is a signal output by three D flip-flops.
  • the digital TDC circuit 105 includes a delay chain 1051 , a plurality of D flip-flops 1052 , and a first thermometer code decoder 1053 , which will be described in detail below.
  • An input end of the delay chain 1051 is connected to the third end of the second two-to-one switch 104 , and is used to receive a signal output by the third end of the second two-to-one switch 104 .
  • the delay chain 1051 includes a plurality of delay taps, and the delay taps 11 correspond to the D flip-flops 1052 one by one. Each delay tap is connected to the input pin of the corresponding D flip-flop 1052; each delay tap is used to perform a delay operation with a different delay time on the signal received by the delay chain 1051, wherein:
  • Delay tap 1 is used to perform a delay operation of a delay time t on the signal received by delay chain 1051;
  • Delay tap 2 is used to perform a delay operation of a delay time of 2t on the signal received by delay chain 1051;
  • the delay tap n is used to perform a delay operation on the signal received by the delay chain 1051 for a delay time nt.
  • Each D flip-flop 1052 is used to receive the signal output by the corresponding delay tap, and outputs a valid level signal when the signal received by the delay chain 1051 is a trigger pulse signal; otherwise, it outputs an invalid level signal. That is, when the delay chain 1051 does not receive the trigger pulse signal, all D flip-flops output invalid level signals. After the delay chain 1051 receives the trigger pulse signal, since the pulse width of the trigger pulse signal is limited, some D flip-flops 1052 will output valid level signals. Then, according to the number of D flip-flops corresponding to these output valid level signals and the delay time of the corresponding connected delay tap, the width of the trigger pulse signal can be obtained. In another embodiment, if the number of D flip-flops 1052 matches the pulse width of the trigger pulse signal, it is also possible that all D flip-flops 1052 output valid level signals.
  • the first thermometer code decoder is used to receive the level signal output by each D flip-flop and output a corresponding first decoding value sequence, wherein the first decoding value sequence includes multiple first decoding values, and each first decoding value corresponds one-to-one to the level signal output by each D flip-flop; the first thermometer code decoder determines the pulse width of the trigger pulse signal according to the number of valid decoding values in the first decoding value sequence.
  • the number of oscilloscope clock signal cycles included in the pulse width of the trigger pulse signal is 2; then, based on the pulse width of the trigger pulse signal and the number of oscilloscope clock signal cycles included in the pulse width of the trigger pulse signal, determining the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal includes: subtracting two clock signal cycles from the pulse width of the trigger pulse signal to obtain the time difference between the trigger edge of the analog trigger signal and the clock edge of the clock signal.
  • the analog trigger signal when the analog trigger signal falls into the holding time window of the clock edge, the analog trigger signal may be synchronized to the synchronization signal 1 by the current clock edge, or may be synchronized to the synchronization signal 2 by the next clock edge. That is, when the trigger pulse expansion circuit 103 delays and adjusts the trigger edge of the analog trigger signal, the third trigger synchronization signal obtained may contain two clock signal cycles between the analog trigger signal and the trigger signal, or may contain three clock signal cycles. If the number of clock signal cycles of the oscilloscope contained in the pulse width of the trigger pulse signal is all taken as 2, it may cause the waveform displayed by the oscilloscope to jitter by one clock signal cycle.
  • the digital TDC circuit shown in FIG5 is improved in this embodiment. Please refer to FIG7.
  • the digital TDC circuit also includes: a second thermometer code decoder 1054, an AND gate logic circuit 1055 and a counter 1056.
  • the first thermometer code decoder 1053 is also used to receive the signal output by each delay tap of the delay chain, and output the first decoded value when the first non-zero data is detected.
  • the second thermometer code decoder 1054 is used to receive the inverse signal of the signal output by each delay tap of the delay chain, and output the second decoded value when the first non-zero data is detected. Please refer to FIG8, which is a decoding timing, wherein valid1 is the first decoded value, valid2 is the second decoded value, data1 is the original code signal output by the delay chain, and data2 is the inverse signal of the original code signal.
  • the AND gate logic circuit 1055 is used to obtain the inverse value of the first decoded value and the second decoded value, and perform a subtraction operation on the first decoded value and the second decoded value to obtain a first signal.
  • the counter 1056 is used to receive the first signal and count the first signal to obtain a count value, where the count value is the number of oscilloscope clock signal cycles contained in the pulse width of the trigger pulse signal.
  • D(0), D(1)...D(n-1) represent the signals of each delay tap.
  • Each clock signal samples the signal on the delay chain. After the first non-zero value is detected on the tap, the valid signal valid1 is pulled high and the value is output, and no further detection is performed afterwards.
  • D(0)’, D(1)’...D(n-1)’ represent the inverse signal of each delay tap.
  • Each clock signal samples the signal on the delay chain. After the first non-zero value is detected on the tap, the valid signal valid2 is pulled high and the value is output, and no further detection is performed afterwards.
  • the inverse code detection timing is to convert the falling edge of the trigger pulse signal p into a rising edge for detection.
  • the analog trigger signal w is in a metastable state, and the third trigger synchronization signal w3 is already a steady-state signal.
  • the present invention widens the trigger edge of the analog trigger signal into a trigger pulse signal, and then performs AND gate logic calculation.
  • the principle of eliminating the metastable state by such conversion calculation is to avoid detecting the specific delay tap position of the trigger edge in the delay chain, but to detect the relative position.
  • the metastable state occurs, the relative position of the trigger edge does not change, but belongs to different clock cycles. In this way, by detecting the relative position, the delay value of the occurrence of the metastable state can be combined into the next clock calculation.
  • Figure 11 is a waveform diagram of the oscilloscope under analog triggering.
  • LSB means that the measured resolution is 18.5ps. It can be seen from Figure 11 that the peak-to-peak value of the waveform jitter is approximately 300ps, which is a significant improvement over the prior art jitter performance.

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Abstract

一种实现模拟触发的示波器，示波器中的触发模块包括触发脉冲扩展电路（103）和数字TDC电路（105），触发脉冲扩展电路（103）用于将模拟触发信号转换为触发脉冲信号，由于触发脉冲信号的脉宽包括模拟触发信号的触发沿和时钟信号的时钟沿之间的时间差以及固定数量的时钟信号的周期，因此，数字TDC电路（105）根据触发脉冲信号的脉宽和触发脉冲信号的脉宽中所包含示波器的时钟信号周期的数量，确定模拟触发信号的触发沿与时钟信号的时钟沿之间的时间差，由此，基于该时间差，补偿模块能够对模拟触发信号的触发沿进行调整，以使模拟触发信号的触发沿与时钟信号的时钟沿同步，从而解决了模拟触发时所采样波形抖动的问题。

Description

一种实现模拟触发的示波器 技术领域
本发明涉及数字示波器技术领域，具体涉及一种实现模拟触发的示波器。
 背景技术
目前，数字示波器为了兼容以前的模拟示波器以及用于通道扩展，还保留有模拟触发通道，即外触发通道；由于数字示波器属于离散系统，而模拟触发属于连续信号触发，使得模拟触发信号的触发沿到数字时钟信号的时钟沿在帧与帧之间会存在一个不确定的时间差，从而导致通过模拟触发所采样的波形出现抖动。因此，为了稳定模拟触发所采样的波形，需要测出该时间差来补偿因触发沿和时钟沿不对齐引起的波形抖动问题。
 技术问题
本发明主要解决的技术问题是在模拟触发下，如何确定模拟触发信号的触发沿和时钟信号的时钟沿之间的时间差。
 技术解决方案
一种实施例中提供一种实现模拟触发的示波器，包括：
数据采集模块，用于对信号通道所输入的信号进行数据采集；
模拟触发通道，用于获取触发输入信号，并将触发输入信号与预设的触发电平进行比较，得到模拟触发信号；
触发模块，所述触发模块包括触发脉冲扩展电路和数字TDC电路；
所述触发脉冲扩展电路用于在开始对信号通道输入的信号开始进行数据采集后，对所述模拟触发信号的触发沿进行延迟调整，得到第三触发同步信号，所述第三触发同步信号的触发沿与所述示波器的时钟信号的时钟沿同步；所述触发脉冲扩展电路还用于根据所述模拟触发同步信号的触发沿和所述第三触发同步信号的触发沿，产生触发脉冲信号，所述触发脉冲信号的上升沿为所述模拟触发同步信号的触发沿，所述触发脉冲信号的下降沿为所述第三触发同步信号的触发沿；
所述数字TDC电路用于获取所述触发脉冲信号的脉宽和所述触发脉冲信号的脉宽中所包含所述示波器的时钟信号周期的数量，并基于所述触发脉冲信号的脉宽和所述触发脉冲信号的脉宽中所包含所述示波器的时钟信号周期的数量，确定所述模拟触发信号的触发沿与所述时钟信号的时钟沿之间的时间差；
补偿模块，用于基于所述模拟触发信号的触发沿与所述时钟信号的时钟沿之间的时间差，对所述模拟触发信号的触发沿进行调整，以使所述模拟触发信号的触发沿与所述时钟信号的时钟沿同步。
 有益效果
依据上述实施例的实现模拟触发的示波器，示波器中的触发模块包括触发脉冲扩展电路和数字TDC电路，触发脉冲扩展电路用于将模拟触发信号转换为触发脉冲信号，由于触发脉冲信号的脉宽包括模拟触发信号的触发沿和时钟信号的时钟沿之间的时间差以及固定数量的时钟信号的周期，因此，数字TDC电路根据触发脉冲信号的脉宽和触发脉冲信号的脉宽中所包含所述示波器的时钟信号周期的数量，确定模拟触发信号的触发沿与所述时钟信号的时钟沿之间的时间差，由此，基于该时间差，补偿模块能够对模拟触发信号的触发沿进行调整，以使模拟触发信号的触发沿与时钟信号的时钟沿同步，从而解决了模拟触发时所采样波形抖动的问题。
 附图说明
图1为通过模拟TDC技术测量模拟触发信号的触发沿到时钟信号的时钟沿的时间差的示意图；
图2为通过高速时钟多相位采样技术测量模拟触发信号的触发沿到时钟信号的时钟沿的时间差的示意图；
图3为一种实施例的示波器的触发模块的结构示意图；
图4为时钟信号、模拟触发信号w、第一触发同步信号w1、第二触发同步信号w2、第三触发同步信号w3和触发脉冲信号p的示意图；
图5为一种实施例的数字TDC电路的结构示意图；
图6为亚稳态存在原理示意图；
图7为另一种实施例的数字TDC电路的结构示意图；
图8为解码时序图；
图9为时钟信号、各个延时抽头的信号和有效信号valid1的示意图；
图10为时钟信号、各个延时抽头的信号和有效信号valid2的示意图；
图11为示波器在模拟触发下的波形示意图。
 本发明的实施方式
下面通过具体实施方式结合附图对本发明作进一步详细说明。其中不同实施方式中类似元件采用了相关联的类似的元件标号。在以下的实施方式中，很多细节描述是为了使得本申请能被更好的理解。然而，本领域技术人员可以毫不费力的认识到，其中部分特征在不同情况下是可以省略的，或者可以由其他元件、材料、方法所替代。在某些情况下，本申请相关的一些操作并没有在说明书中显示或者描述，这是为了避免本申请的核心部分被过多的描述所淹没，而对于本领域技术人员而言，详细描述这些相关操作并不是必要的，他们根据说明书中的描述以及本领域的一般技术知识即可完整了解相关操作。
另外，说明书中所描述的特点、操作或者特征可以以任意适当的方式结合形成各种实施方式。同时，方法描述中的各步骤或者动作也可以按照本领域技术人员所能显而易见的方式进行顺序调换或调整。因此，说明书和附图中的各种顺序只是为了清楚描述某一个实施例，并不意味着是必须的顺序，除非另有说明其中某个顺序是必须遵循的。
本文中为部件所编序号本身，例如“第一”、“第二”等，仅用于区分所描述的对象，不具有任何顺序或技术含义。而本申请所说“连接”、“联接”，如无特别说明，均包括直接和间接连接（联接）。
请参考图1，图1示出了通过模拟TDC技术测量模拟触发信号的触发沿到时钟信号的时钟沿的时间差的一个例子，示波器中的可编程逻辑器件（FPGA）发送一个时钟宽度的脉冲1clk到模拟TDC电路进行展宽，得到T1；再发送两个时钟宽度的脉冲2clk到模拟TDC电路进行展宽，得到T2；假设模拟TDC电路是线性的，展宽系数是A，那么一个时钟信号被分成A份，每份的宽度t=(T2–T1)/A。如图1所示，模拟触发信号的触发沿到时钟信号的时钟沿的时间差是ΔT，把模拟触发信号和模拟触发同步信号组成的脉冲信号送到模拟TDC电路展宽，得到Δt，根据t就可以算出模拟触发信号到时钟沿的距离。然而，该方式需要额外的硬件模拟电路进行支持，此外模拟电路中的元器件易受温度影响，从而影响最终输出的结果。
请参考图2，图2示出了通过高速时钟多相位采样技术测量模拟触发信号的触发沿到时钟信号的时钟沿的时间差的一个例子，假如时钟1是FPGA主时钟，可以用一个更高速的时钟2来采样模拟触发信号，时钟1和时钟2有确定的关系，假设是1:2，那么根据时钟2的采样结果就能分辨出模拟触发信号在时钟1的前半个周期还是后半个周期，同类，可以提高采样频率和采用多个相位采样模拟触发信号，根据所得结果分析模拟触发信号的触发沿到时钟沿的距离。然而，由于1G的采样频率才有1ns的分辨率，假设需要20ps的分辨率，采样时钟需要50G的速度，FPGA无法支撑这么高的采样速度。
基于上述问题，本发明实施例通过将模拟触发信号转换为触发脉冲信号，并基于触发脉冲信号的脉宽以及其所包含的时钟信号的周期的数量，确定模拟触发信号的触发沿与时钟信号的时钟沿之间的时间差，并且，通过数字电路实现模拟触发功能，并将数字电路集成到示波器的FPGA芯片中，不需要额外的硬件模拟电路。
本发明实施例提供了一种实现模拟触发的示波器，以下简称示波器，示波器包括：数据采集模块、模拟触发通道、触发模块和补偿模块，其中，数据采集模块用于对信号通道输入的信号进行数据采集；模拟触发通道用于获取触发输入信号，并将触发输入信号与预设的触发电平进行比较，得到模拟触发信；触发模块用于确定模拟触发信号的触发沿与时钟信号的时钟沿之间的时间差；补偿模块用于基于模拟触发信号的触发沿与时钟信号的时钟沿之间的时间差，对模拟触发信号的触发沿进行调整，以使模拟触发信号的触发沿与时钟信号的时钟沿同步。
请参考图3，图3为一种实施例的触发模块的结构示意图，触发模块包括T触发器101、第一二选一开关102、触发脉冲扩展电路103、第二二选一开关104和数字TDC电路105，下面详细说明。
T触发器101用于在开始对信号通道输入的信号开始进行数据采集时，输出被清零，并在预触发深度满后，接收并输出模拟触发信号。T触发器101的D引脚连接电源VCC，T触发器101的C引脚（输入引脚）用于接收模拟触发信号，T触发器101的CE引脚用于获取预触发信号，T触发器101的RS引脚用于获取采集开始信号，其中，采集开始信号用于表征示波器的数据采集模块开始进行数据采集。
在本实施例中，模拟触发信号是通过一模拟比较器输出的，模拟比较器包括正相输入端和反相输入端，正相输入端用于获取外部输入的触发输入信号，反相输入端用于获取预设的触发电平，模拟比较器用于对触发输入信号和预设的触发电平进行比较，输出模拟触发信号。
第一二选一开关102包括第一端、第二端和第三端，第一二选一开关102的第一端用于获取T触发器输出的模拟触发信号，第一二选一开关102的第二端用于获取数字触发信号，第一二选一开关102的第三端连接触发脉冲扩展电路的输入端，该第三端用于在触发选择信号的触发下，输出模拟触发信号或数字触发信号，即，第一二选一开关102用于切换模拟触发和数字触发的触发方式。
触发脉冲扩展电路103用于在开始对信号通道输入的信号开始进行数据采集后，对模拟触发信号的触发沿进行延迟调整，得到第三触发同步信号；其中，第三触发同步信号的触发沿与示波器的时钟信号的时钟沿同步。需要说明的是，示波器的时钟信号是指示波器用于采样的本地时钟信号，其通过FPGA产生。
此外，触发脉冲扩展电路103还用于根据模拟触发同步信号的触发沿和第三触发同步信号的触发沿，产生触发脉冲信号，触发脉冲信号的上升沿为模拟触发同步信号的触发沿，触发脉冲信号的下降沿为第三触发同步信号的触发沿。
第二二选一开关104包括第一端、第二端和第三端，第二二选一开关104的第一端用于获取触发脉冲信号，第二二选一开关104的第二端用于获取校准序列信号，第二二选一开关104的第三端连接数字TDC电路的输入端，该第三端用于在校正选择信号的触发下，对触发脉冲信号进行校正。
数字TDC电路105用于获取触发脉冲信号的脉宽和触发脉冲信号的脉宽中所包含示波器的时钟信号周期的数量，并基于触发脉冲信号的脉宽和触发脉冲信号的脉宽中所包含示波器的时钟信号周期的数量，确定模拟触发信号的触发沿与时钟信号的时钟沿之间的时间差。
本发明实施例提供的触发模块为数字电路，可直接集成在示波器的FPGA内，无需外设模拟电路来测量模拟触发信号的触发沿与时钟信号的时钟沿之间的时间差，且测量精度较高，不受温度等环境因素影响。
下面对触发脉冲扩展电路103和数字TDC电路105进行详细说明。
在一实施例中，触发脉冲扩展电路103对所述模拟触发信号的触发沿进行延迟调整，得到第三触发同步信号包括：获取模拟触发信号的触发沿所处的时钟信号的周期，将所获取的时钟信号的周期对应时钟信号作为同步时钟信号；基于同步时钟信号，产生第一触发同步信号，所述第一触发同步信号的触发沿与所述同步时钟信号的时钟沿相同步；基于第一触发同步信号，产生第二触发同步信号，第二触发同步信号的触发沿相对于第一触发同步信号的触发沿延迟一个时钟信号的周期；基于第二触发同步信号，产生第三触发同步信号，第三触发同步信号的触发沿相对于第二触发同步信号的触发沿延迟一个时钟信号的周期。
请参考图4，图4为时钟信号、模拟触发信号w、第一触发同步信号w1、第二触发同步信号w2、第三触发同步信号w3和触发脉冲信号p的时序示意图。由于模拟触发信号和示波器的时钟信号之间是异步的关系，本实施例先对模拟触发信号w进行异步信号同步化，依次通过产生第一触发同步信号w1、第二触发同步信号w2、第三触发同步信号w3，以使得到的第三触发同步信号w3与时钟信号的时钟沿同步，然后取模拟触发信号w的触发沿作为上升沿，第三触发同步信号w3的触发沿作为下降沿，组成触发脉冲信号p，其中，触发脉冲信号p的表达式p=!w3&w，&表示逻辑与，！表示逻辑取反。
需要说明的是，对于时钟信号来说，时钟信号的时钟沿存在一个保持时间窗口，若模拟触发信号的触发沿落在时钟沿的保持时间窗口内时，即可认为其与时钟信号的时钟沿同步，其中，时钟沿的保持时间窗口为以时钟沿为中心的预设时间范围。在图4中，第三触发同步信号的触发沿并没有与时钟信号的时钟沿完全对齐，其与时钟沿之间的时间差为T4，但考虑到时钟沿的保持时间窗口，同样认为第三触发同步信号的触发沿与时钟信号的时钟沿的同步，同理，T3为模拟触发信号的触发沿到时钟信号的时钟沿之间的时间差，考虑到保持窗口时间，因此，T3并不是完全的触发沿到时钟沿之间的时间差。此外，图4中的T时间区间表示模拟触发信号可能出现的区间。
综上，第三触发同步信号的触发沿与示波器的时钟信号的时钟沿同步包括：第三触发同步信号的触发沿处于所述示波器的时钟信号的时钟沿的保持时间窗口内；第一触发同步信号的触发沿与所述同步时钟信号的时钟沿相同步包括：第一触发同步信号的触发沿处于同步时钟信号的时钟沿的保持时间窗口内。
还需要说明的是，本实施例提供的触发脉冲扩展电路103可通过数字电路实现，例如，可通过三个D触发器实现，第一触发同步信号为经过一个D触发器输出的信号，第二触发同步信号为经过两个D触发器输出的信号，第三触发同步信号为经过三个D触发器输出的信号。
在一实施例中，请参考图5，数字TDC电路105包括延时链1051、多个D触发器1052和第一温度计码解码器1053，下面详细说明。
延时链1051的输入端与第二二选一开关104的第三端连接，其用于接收第二二选一开关104的第三端输出的信号。
延时链1051包括多个延时抽头，延时抽头11与D触发器1052一一对应，各个延时抽头与其相对应的D触发器1052的输入引脚连接；各个延时抽头用于对延时链1051接收的信号进行不同延时时间的延时操作，其中：
延时抽头1用于对延时链1051接收的信号进行延时时间t的延时操作；
延时抽头2用于对延时链1051接收的信号进行延时时间2t的延时操作；
…
延时抽头n用于对延时链1051接收的信号进行延时时间nt的延时操作。
各个D触发器1052用于接收对应的延时抽头输出的信号，并在延时链1051接收到的信号为触发脉冲信号时，输出有效电平信号；否则，输出无效电平信号。也就是，当延时链1051未接收到触发脉冲信号时，所有D触发器均输出无效电平信号，在延时链1051接收到触发脉冲信号后，由于触发脉冲信号的脉宽是有限的，因此会有部分D触发器1052输出有效电平信号，则根据这些输出有效电平信号对应的D触发器的数量以及相应的所连接的延时抽头的延时时间，即可得到触发脉冲信号的宽度，在另一实施例中，若D触发器1052的数量与触发脉冲信号的脉宽相匹配，则也有可能所有D触发器1052均输出有效电平信号。
第一温度计码解码器用于接收各个D触发器输出的电平信号，输出对应的第一解码值序列，第一解码值序列中包括多个第一解码值，各个第一解码值与各个D触发器输出的电平信号一一对应；第一温度计码解码器根据第一解码值序列中有效解码值的数量，确定触发脉冲信号的脉宽。
在一实施例中，触发脉冲信号的脉宽中所包含示波器的时钟信号周期的数量为2；那么，基于触发脉冲信号的脉宽和触发脉冲信号的脉宽中所包含示波器的时钟信号周期的数量，确定模拟触发信号的触发沿与时钟信号的时钟沿之间的时间差包括：将触发脉冲信号的脉宽减去两个时钟信号周期，得到模拟触发信号的触发沿与时钟信号的时钟沿之间的时间差。
请参考图6，由于亚稳态的存在，模拟触发信号落到时钟沿的保持时间窗口内时，模拟触发信号可能被当前的时钟沿同步为同步信号1，也可能被下一个时钟沿同步为同步信号2，也就是，触发脉冲扩展电路103在对模拟触发信号的触发沿进行延迟调整时，得到的第三触发同步信号可能与模拟触发信号之间包含有两个时钟信号周期，也可能包含有三个时钟信号周期。若将触发脉冲信号的脉宽中所包含示波器的时钟信号周期的数量都作为2，可能会导致示波器显示的波形有一个时钟信号周期的抖动，为了避免这种亚稳态的存在，本实施例对图5所示数字TDC电路进行了改进，请参考图7，数字TDC电路还包括：第二温度计码解码器1054、与门逻辑电路1055和计数器1056。
第一温度计码解码器1053还用于接收延时链的各个延时抽头输出的信号，并在检测到第一不为0的数据时，输出第一解码值。第二温度计码解码器1054用于接收延时链的各个延时抽头输出的信号的反码信号，并在检测到第一个不为0的数据时，输出第二解码值。请参考图8，图8为解码时序，其中，valid1为第一解码值，valid2为第二解码值，data1为延时链输出的原码信号，data2为原码信号的反码信号。
与门逻辑电路1055用于获取第一解码值和第二解码值的反码值，并对第一解码值和第二解码值进行相减操作，得到第一信号。
计数器1056用于接收第一信号，并对第一信号进行计数，得到计数值，计数值为所述触发脉冲信号的脉宽中所包含示波器的时钟信号周期的数量。
在本实施例中，第一信号为k，则号k=!valid2&valid1，对信号k进行计数，计数值为s，那么：Tedge1 = (s– 2) * Tclk + T3 – T4，其中，Tedge1为消除亚稳态后的模拟触发信号的触发沿与；时钟信号的时钟沿之间的时间差；若第三触发同步信号w3与时钟沿完全对齐，也即是T4=0，那么消除亚稳态后的最终时间差Tfinal为：Tfinal = (s– 2) * Tclk + T3。
请参考图9，假如触发脉冲信号输入到延时链，那么D(0),D(1)……D(n-1)表示各个延时抽头的信号，每个时钟信号都对延时链上的信号进行采样，抽头上检测到第一个不为0的数值后，有效信号valid1拉高，输出该值，后面也不再继续检测。
请参考图10，假如触发脉冲信号输入到延时链，那么D(0)’,D(1)’……D(n-1)’表示各个延时抽头的反码信号，每个时钟信号都对延时链上的信号进行采样，抽头上检测到第一个不为0的数值后，有效信号valid2拉高，输出该值，后面也不再继续检测。
从图9和图10的对比可以看出，反码检测时序是把触发脉冲信号p的下降沿转成上升沿来检测。模拟触发信号w存在亚稳态，第三触发同步信号w3已经是稳态信号，通过逻辑关系可得，触发脉冲信号p的上升沿和下降沿之间存在2个完整的时钟信号周期，这样就可以计算模拟触发信号到时钟沿的时间差。
本发明将模拟触发信号的触发沿展宽成触发脉冲信号，再做与门逻辑计算，这样转换计算能消除亚稳态的原理是避免检测触发沿在延时链中的具体哪个延时抽头位置，而是检测相对位置，发生亚稳态的时候触发沿的相对位置没有改变，只是分属于不同的时钟周期，这样通过检测相对位置可以把发生亚稳态的延时值合到下个时钟计算。
请参考图11，图11为示波器在模拟触发下的波形示意图，发送20000次和时钟信号存在固定相位差的测试信号，算出样本标准差σ=0.9LSB=16.6ps，LSB表示实测的分辨率为18.5ps，从图11中可以看出，波形的抖动峰峰值大约是300ps，相对现有技术抖动性能提升了很多。
以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发明，并不用以限制本发明。对于本发明所属技术领域的技术人员，依据本发明的思想，还可以做出若干简单推演、变形或替换。

Claims (8)

  1. 一种实现模拟触发的示波器，其特征在于，包括：
    数据采集模块，用于对信号通道所输入的信号进行数据采集；
    模拟触发通道，用于获取触发输入信号，并将触发输入信号与预设的触发电平进行比较，得到模拟触发信号；
    触发模块，所述触发模块包括触发脉冲扩展电路和数字TDC电路；
    所述触发脉冲扩展电路用于在开始对信号通道输入的信号开始进行数据采集后，对所述模拟触发信号的触发沿进行延迟调整，得到第三触发同步信号，所述第三触发同步信号的触发沿与所述示波器的时钟信号的时钟沿同步；所述触发脉冲扩展电路还用于根据所述模拟触发同步信号的触发沿和所述第三触发同步信号的触发沿，产生触发脉冲信号，所述触发脉冲信号的上升沿为所述模拟触发同步信号的触发沿，所述触发脉冲信号的下降沿为所述第三触发同步信号的触发沿；
    所述数字TDC电路用于获取所述触发脉冲信号的脉宽和所述触发脉冲信号的脉宽中所包含所述示波器的时钟信号周期的数量，并基于所述触发脉冲信号的脉宽和所述触发脉冲信号的脉宽中所包含所述示波器的时钟信号周期的数量，确定所述模拟触发信号的触发沿与所述时钟信号的时钟沿之间的时间差；
    补偿模块，用于基于所述模拟触发信号的触发沿与所述时钟信号的时钟沿之间的时间差，对所述模拟触发信号的触发沿进行调整，以使所述模拟触发信号的触发沿与所述时钟信号的时钟沿同步；
    所述数字TDC电路包括：延时链、多个D触发器和第一温度计码解码器；
    所述延时链包括多个延时抽头，所述延时抽头与D触发器一一对应，各个所述延时抽头与其相对应的D触发器的输入引脚连接；各个所述延时抽头用于对所述延时链接收的信号进行不同延时时间的延时操作，其中：
    延时抽头1用于对所述延时链接收的信号进行延时时间t的延时操作；
    延时抽头2用于对所述延时链接收的信号进行延时时间2t的延时操作；
    …
    延时抽头n用于对所述延时链接收的信号进行延时时间nt的延时操作；
    各个所述D触发器用于接收对应的所述延时抽头输出的信号，并在接收到的信号为所述触发脉冲信号时，输出有效电平信号；否则，输出无效电平信号；
    所述第一温度计码解码器用于接收各个所述D触发器输出的电平信号，输出对应的第一解码值序列，所述第一解码值序列中包括多个第一解码值，各个第一解码值与各个D触发器输出的电平信号一一对应；所述第一温度计码解码器根据第一解码值序列中有效解码值的数量，确定所述触发脉冲信号的脉宽；
    所述数字TDC电路还包括：第二温度计码解码器、与门逻辑电路和计数器；
    所述第一温度计码解码器还用于接收延时链的各个延时抽头输出的信号，并在检测到第一个不为0的信号时，输出第一解码值；
    第二温度计码解码器用于接收延时链的各个延时抽头输出的信号的反码信号，并在检测到第一个不为0的数据时，输出第二解码值；
    所述与门逻辑电路用于获取第一解码值和第二解码值的反码值，并对第一解码值和第二解码值进行相减操作，得到第一信号；
    所述计数器用于接收第一信号，并对第一信号进行计数，得到计数值，所述计数值为所述触发脉冲信号的脉宽中所包含所述示波器的时钟信号周期的数量。
  2.  如权利要求1所述的示波器，其特征在于，所述对所述模拟触发信号的触发沿进行延迟调整，得到第三触发同步信号包括：
    获取所述模拟触发信号的触发沿所处的所述时钟信号的周期，将所获取的时钟信号的周期对应时钟信号作为同步时钟信号；
    基于所述同步时钟信号，产生第一触发同步信号，所述第一触发同步信号的触发沿与所述同步时钟信号的时钟沿相同步；
    基于所述第一触发同步信号，产生第二触发同步信号，所述第二触发同步信号的触发沿相对于所述第一触发同步信号的触发沿延迟一个时钟信号的周期；
    基于所述第二触发同步信号，产生第三触发同步信号，所述第三触发同步信号的触发沿相对于所述第二触发同步信号的触发沿延迟一个时钟信号的周期。
  3.  如权利要求2所述的示波器，其特征在于，所述第三触发同步信号的触发沿与所述示波器的时钟信号的时钟沿同步包括：
    所述第三触发同步信号的触发沿处于所述示波器的时钟信号的时钟沿的保持时间窗口内；其中，所述时钟沿的保持时间窗口为以所述时钟沿为中心的预设时间范围；
    所述第一触发同步信号的触发沿与所述同步时钟信号的时钟沿相同步包括：
    所述第一触发同步信号的触发沿处于所述同步时钟信号的时钟沿的保持时间窗口内。
  4.  如权利要求1所述的示波器，其特征在于，所述触发脉冲信号的脉宽中所包含所述示波器的时钟信号周期的数量为2；
    所述基于所述触发脉冲信号的脉宽和所述触发脉冲信号的脉宽中所包含所述示波器的时钟信号周期的数量，确定所述模拟触发信号的触发沿与所述时钟信号的时钟沿之间的时间差包括：
    将所述触发脉冲信号的脉宽减去两个时钟信号周期，得到所述模拟触发信号的触发沿与所述时钟信号的时钟沿之间的时间差。
  5.  如权利要求1所述的示波器，其特征在于，所述基于所述触发脉冲信号的脉宽和所述触发脉冲信号的脉宽中所包含所述示波器的时钟信号周期的数量，确定所述模拟触发信号的触发沿与所述时钟信号的时钟沿之间的时间差包括：
    将所述触发脉冲信号的脉宽减去计数值个时钟信号周期，得到所述模拟触发信号的触发沿与所述时钟信号的时钟沿之间的时间差。
  6.  如权利要求1所述的示波器，其特征在于，所述触发模块还包括：T触发器、第一二选一开关和第二二选一开关；
    所述T触发器用于在开始对信号通道输入的信号开始进行数据采集时，输出被清零，并在预触发深度满后，接收并输出所述模拟触发信号；
    所述第一二选一开关包括第一端、第二端和第三端，第一端用于获取T触发器输出的所述模拟触发信号，第二端用于获取数字触发信号，第三端连接触发脉冲扩展电路的输入端，所述第三端用于在触发选择信号的触发下，输出所述模拟触发信号或所述数字触发信号；
    所述第二二选一开关包括第一端、第二端和第三端，第一端用于获取所述触发脉冲信号，第二端用于获取校准序列信号，第三端连接所述数字TDC电路的输入端，所述第三端用于在校正选择信号的触发下，对所述触发脉冲信号进行校正。
  7.  如权利要求1所述的示波器，其特征在于，所述模拟触发通道包括：
    模拟比较器，包括正相输入端和反相输入端，所述正相输入端用于获取所述触发输入信号，所述反相输入端用于获取预设的触发电平，所述模拟比较器用于对触发输入信号和预设的触发电平进行比较，输出所述模拟触发信号。
  8.  如权利要求1所述的示波器，其特征在于，包括：
    可编程逻辑器件，所述触发模块集成在可编程逻辑器件中。
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090322574A1 (en) * 2006-02-17 2009-12-31 Verigy (Singapore) Pte. Ltd. Time-to-digital conversion with delay contribution determination of delay elements
JP2010028600A (ja) * 2008-07-23 2010-02-04 Sony Corp Ｔｄｃ回路、ｐｌｌ回路、並びに無線通信装置
CN104702249A (zh) * 2013-12-10 2015-06-10 苏州普源精电科技有限公司 一种具有猝发同步功能的信号发生器
CN206489205U (zh) * 2017-02-16 2017-09-12 深圳市鼎阳科技有限公司 降低示波器外触发波形抖动的系统、数字芯片和示波器
CN108267628A (zh) * 2016-12-30 2018-07-10 北京普源精电科技有限公司 具有等效采样功能的混合信号示波器
CN108982940A (zh) * 2018-06-13 2018-12-11 深圳市鼎阳科技有限公司 一种基于串行接收器的外触发装置及外触发方法、示波器
CN110445493A (zh) * 2019-06-27 2019-11-12 中国科学技术大学 一种基于fpga tdc的数据采集同步装置及方法
CN113315521A (zh) * 2021-05-07 2021-08-27 清华大学 一种数字时间转换器及电子装置
CN115541955A (zh) * 2022-12-01 2022-12-30 深圳市鼎阳科技股份有限公司 一种实现模拟触发的示波器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7564284B2 (en) * 2007-03-26 2009-07-21 Infineon Technologies Ag Time delay circuit and time to digital converter
CN103018512B (zh) * 2011-09-23 2016-09-07 北京普源精电科技有限公司 一种具有外触发功能的示波器
CN102435809B (zh) * 2011-10-12 2013-12-04 秦轲 一种多通道数字示波器及其信号同步方法
CN102830610B (zh) * 2012-09-17 2015-01-07 中国电子科技集团公司第四十一研究所 一种基于tdc-gp21的精密时间自动测量电路及方法
CN103092098B (zh) * 2012-12-28 2015-10-14 沈阳东软医疗系统有限公司 一种多通道时序控制的方法和装置
US9294237B2 (en) * 2014-07-30 2016-03-22 Tektronix, Inc. Method for performing joint jitter and amplitude noise analysis on a real time oscilloscope
CN110749763A (zh) * 2019-12-24 2020-02-04 深圳市鼎阳科技股份有限公司 一种基于i2s信号的触发方法及示波器

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090322574A1 (en) * 2006-02-17 2009-12-31 Verigy (Singapore) Pte. Ltd. Time-to-digital conversion with delay contribution determination of delay elements
JP2010028600A (ja) * 2008-07-23 2010-02-04 Sony Corp Ｔｄｃ回路、ｐｌｌ回路、並びに無線通信装置
CN104702249A (zh) * 2013-12-10 2015-06-10 苏州普源精电科技有限公司 一种具有猝发同步功能的信号发生器
CN108267628A (zh) * 2016-12-30 2018-07-10 北京普源精电科技有限公司 具有等效采样功能的混合信号示波器
CN206489205U (zh) * 2017-02-16 2017-09-12 深圳市鼎阳科技有限公司 降低示波器外触发波形抖动的系统、数字芯片和示波器
CN108982940A (zh) * 2018-06-13 2018-12-11 深圳市鼎阳科技有限公司 一种基于串行接收器的外触发装置及外触发方法、示波器
CN110445493A (zh) * 2019-06-27 2019-11-12 中国科学技术大学 一种基于fpga tdc的数据采集同步装置及方法
CN113315521A (zh) * 2021-05-07 2021-08-27 清华大学 一种数字时间转换器及电子装置
CN115541955A (zh) * 2022-12-01 2022-12-30 深圳市鼎阳科技股份有限公司 一种实现模拟触发的示波器

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