WO2024108695A1 - 芯片级底部填充胶用二氧化硅填料及其制备方法与应用 - Google Patents

芯片级底部填充胶用二氧化硅填料及其制备方法与应用 Download PDF

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WO2024108695A1
WO2024108695A1 PCT/CN2022/139185 CN2022139185W WO2024108695A1 WO 2024108695 A1 WO2024108695 A1 WO 2024108695A1 CN 2022139185 W CN2022139185 W CN 2022139185W WO 2024108695 A1 WO2024108695 A1 WO 2024108695A1
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chip
preparation
solution
aqueous solution
source compound
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PCT/CN2022/139185
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French (fr)
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张磊聪
孙蓉
朱朋莉
赵涛
王宁
张传奇
杜晓蒙
杜明勇
强倩倩
杨柳
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中国科学院深圳先进技术研究院
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    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B33/00—Silicon; Compounds thereof
    • C01B33/113—Silicon oxides; Hydrates thereof
    • C01B33/12—Silica; Hydrates thereof, e.g. lepidoic silicic acid
    • C01B33/18—Preparation of finely divided silica neither in sol nor in gel form; After-treatment thereof
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J11/00—Features of adhesives not provided for in group C09J9/00, e.g. additives
    • C09J11/02—Non-macromolecular additives
    • C09J11/04—Non-macromolecular additives inorganic

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  • the present application relates to the field of semiconductor technology, for example, silicon dioxide, and in particular to a silicon dioxide filler for chip-level bottom filling glue and a preparation method and application thereof.
  • SiO 2 Silicon dioxide
  • SiO 2 is widely used as an inorganic filler in chip-level bottom filler, which is crucial for stress matching, mechanical protection and reliability after chip packaging.
  • ICs integrated circuits
  • the packaging form of integrated circuits (ICs) has begun to transition from 2D packaging to 2.1D, 2.5D and 3D packaging.
  • the spacing between chips, between micro-bumps and between chips and substrates is getting narrower and narrower, which puts forward new requirements for the particle size, impurity elements and radioactive element content of SiO 2.
  • the methods for preparing SiO 2 include melting method, combustion and explosion method and chemical synthesis method. Although all methods can prepare SiO 2 of different particle sizes, they still have certain disadvantages.
  • the melting method for producing SiO2 uses crystalline silicon dioxide as raw material. Before preparing SiO2 , the crystalline silicon dioxide needs to be crushed, ultra-finely ground, screened and purified. The purified powder is then sent into a high-temperature field generated by combustible gas-oxygen. After high-temperature melting, the surface tension of the powder is regulated during the cooling process by controlling the conditions, and finally it is cooled and solidified into spherical SiO2 .
  • the average particle size of SiO2 obtained by the melting method is large and the sphericity is not high.
  • the crystalline silica comes from natural quartz ore, the content of radioactive element U is relatively high.
  • the combustion and explosion method uses ultrafine silicon powder as raw material. Before preparing spherical SiO2 , the silicon powder needs to be ultrafinely crushed and screened.
  • the combustion and explosion method uses a burner to burn combustible gases such as methane, propane, hydrogen or acetylene in an oxygen-containing atmosphere to form a flame, and at the same time, ultrafine silicon powder is sent into the flame to form a dust cloud, which triggers the combustion and explosion to obtain spherical SiO2 ultrafine particles.
  • the SiO2 obtained by the combustion and explosion method has a high sphericity and a smooth surface, but ultrafine silicon powder is prone to cause dust explosions, and has extremely high safety requirements for space and equipment.
  • the SiO2 product needs to be reclassified, screened and graded, and the production process is relatively cumbersome.
  • the chemical synthesis method uses silicon compounds as raw materials, and obtains high-purity spherical SiO 2 through nucleation and growth processes under the action of dispersants, control agents and catalysts.
  • the chemical synthesis method can control the morphology and particle size of SiO 2 by controlling factors such as reaction temperature, raw material ratio and addition order.
  • the content of impurity ions and radioactive elements in SiO 2 can be further reduced by purifying the raw materials.
  • the present application provides a method for preparing SiO2 based on the chemical synthesis method.
  • the SiO2 obtained by the preparation method has high purity, high sphericity, low impurity ion content, and the particle size distribution meets the requirements of flip chip packaging scenarios.
  • the preparation method provided by the present application can flexibly control the average particle size and cut-off point of SiO2 , without the need for subsequent classification, screening and grading process treatment.
  • the embodiment of the present application provides a silicon dioxide filler for chip-level bottom filling glue and its preparation method and application.
  • the chip-level silicon dioxide filler obtained by the preparation method has high purity and good sphericity, and the preparation conditions are easy to control, which facilitates the control of the average particle size of the final chip-level silicon dioxide filler.
  • an embodiment of the present application provides a method for preparing a silicon dioxide filler for chip-level underfill, the preparation method comprising the following steps:
  • step (3) (4) calcining the powder A obtained in step (3) to obtain the chip-grade silica filler.
  • the preparation method provided in the present application first mixes a silicon source compound and a co-solvent. Under the catalytic action of an aqueous catalyst solution, the silicon source compound is gradually hydrolyzed and condensed to obtain a stable sol system. The gel formed by sol polymerization is subjected to solid-liquid separation, drying and sintering to form a chip-grade silicon dioxide with high purity and good sphericity, and the particle size distribution meets the packaging requirements of flip-chips.
  • the co-solvent solution in step (1) comprises a co-solvent and water in a mass ratio of (10-50):(10-100), for example, it can be 50:10, 50:25, 50:30, 50:40, 10:10, 10:20, 10:30, 10:40, 10:50, 10:60, 10:70, 10:80, 10:90 or 10:100, but is not limited to the listed values, and other values not listed within the numerical range are also applicable.
  • the co-solvent comprises any one of methanol, ethanol, isopropanol or cyclohexane or a combination of at least two thereof, typical but non-limiting combinations comprising a combination of methanol and ethanol, a combination of ethanol and isopropanol, a combination of isopropanol and cyclohexane, a combination of methanol, ethanol and isopropanol, a combination of ethanol, isopropanol and cyclohexane, or a combination of methanol, ethanol, isopropanol and cyclohexane.
  • the mass ratio of the co-solvent solution to the silicon source compound in step (1) is (1-50):1, for example, it can be 1:1, 5:1, 10:1, 20:1, 30:1, 40:1 or 50:1, but is not limited to the listed values, and other unlisted values within the numerical range are also applicable.
  • the silicon source compound in step (1) includes any one of organosilicon, siloxane or silicate, or a combination of at least two of them, for example, a combination of organosilicon and siloxane, a combination of siloxane and silicate, a combination of organosilicon and silicate, or a combination of organosilicon, siloxane and silicate.
  • the organic silicon comprises any one of vinyl trimethoxysilane, vinyl triethoxysilane, (3-mercaptopropyl) trimethoxysilane, allyl trimethoxysilane, 3-glycidyloxypropyl trimethoxysilane or dodecyl trimethoxysilane, or a combination of at least two thereof.
  • Typical but non-limiting combinations include a combination of vinyl trimethoxysilane and vinyl triethoxysilane, a combination of (3-mercaptopropyl) trimethoxysilane and allyl trimethoxysilane, a combination of 3-glycidyloxypropyl trimethoxysilane and dodecyl trimethoxysilane.
  • trimethoxysilane and dodecyltrimethoxysilane a combination of vinyltrimethoxysilane, vinyltriethoxysilane and (3-mercaptopropyl)trimethoxysilane, a combination of allyltrimethoxysilane, 3-glycidyloxypropyltrimethoxysilane and dodecyltrimethoxysilane, or a combination of vinyltrimethoxysilane, vinyltriethoxysilane, (3-mercaptopropyl)trimethoxysilane, allyltrimethoxysilane, 3-glycidyloxypropyltrimethoxysilane and dodecyltrimethoxysilane.
  • the siloxane includes any one of tetramethoxysilane, tetraethoxysilane or tetrapropoxysilane or a combination of at least two thereof, and typical but non-limiting combinations include a combination of tetramethoxysilane and tetraethoxysilane, a combination of tetraethoxysilane and tetrapropoxysilane, a combination of tetramethoxysilane and tetrapropoxysilane, or a combination of tetramethoxysilane, tetraethoxysilane and tetrapropoxysilane.
  • the silicate comprises sodium silicate.
  • the mixing temperature in step (2) is 30-60°C, for example, 30°C, 35°C, 40°C, 45°C, 50°C, 55°C or 60°C, but is not limited to the listed values, and other values not listed within the numerical range are also applicable.
  • the mass ratio of the catalyst aqueous solution to the silicon source compound in step (2) is (1-20):1, for example, it can be 1:1, 3:1, 5:1, 8:1, 10:1, 12:1, 15:1, 18:1 or 20:1, but is not limited to the listed values, and other unlisted values within the numerical range are also applicable.
  • the concentration of the catalyst aqueous solution in step (2) is 0.1-20wt%, for example, it can be 0.1wt%, 1wt%, 3wt%, 5wt%, 8wt%, 10wt%, 12wt%, 15wt%, 16wt%, 18wt% or 20wt%, but is not limited to the listed values, and other unlisted values within the numerical range are also applicable.
  • the catalyst aqueous solution in step (2) comprises any one of an inorganic acid aqueous solution, an inorganic base aqueous solution or an organic acid aqueous solution, or a combination of at least two of them.
  • the mixing in step (2) comprises stirring and mixing until a suspension is obtained, and then continuing to stir for 10-300 min, for example, 10 min, 30 min, 50 min, 60 min, 80 min, 100 min, 120 min, 150 min, 160 min, 180 min, 200 min, 210 min, 240 min, 250 min, 270 min, 280 min or 300 min, but is not limited to the listed values, and other values not listed within the numerical range are also applicable.
  • the stirring and mixing rotation speed is 150-250 rpm, for example, it can be 150 rpm, 160 rpm, 180 rpm, 200 rpm, 210 rpm, 240 rpm or 250 rpm, but is not limited to the listed values, and other values not listed within the numerical range are also applicable.
  • the suspension obtained in step (2) is a white suspension.
  • the solid-liquid separation method in step (3) comprises any one of filter pressing, centrifugation or sedimentation, or a combination of at least two of them.
  • Typical but non-limiting combinations include a combination of filter pressing and centrifugation, a combination of centrifugation and sedimentation, a combination of filter pressing and sedimentation, or a combination of filter pressing, centrifugation and sedimentation.
  • the drying temperature in step (3) is 30-220°C, for example, it can be 30°C, 50°C, 60°C, 80°C, 100°C, 120°C, 150°C, 160°C, 180°C, 200°C or 220°C, but is not limited to the listed values, and other values not listed within the numerical range are also applicable.
  • the drying time in step (3) is 1-24 h, for example, 1 h, 2 h, 3 h, 5 h, 6 h, 8 h, 10 h, 12 h, 15 h, 16 h, 18 h, 20 h, 21 h or 24 h, but is not limited to the listed values, and other unlisted values within the numerical range are also applicable.
  • the present application achieves the removal of physically adsorbed water by drying after solid-liquid separation, thereby obtaining powder A.
  • the preparation method includes washing the obtained solid after solid-liquid separation to remove impurities present in the silicon source compound, thereby reducing the purity requirement for the silicon source compound and ensuring the purity of the final chip-grade silica filler.
  • the temperature of the calcination treatment in step (4) is 500-1300°C, for example, it can be 500°C, 600°C, 700°C, 800°C, 900°C, 1000°C, 1100°C, 1200°C or 1300°C, but is not limited to the listed values, and other unlisted values within the numerical range are also applicable.
  • the calcination time in step (4) is 10-300 min, for example, 10 min, 30 min, 50 min, 60 min, 80 min, 100 min, 120 min, 150 min, 160 min, 180 min, 200 min, 210 min, 240 min, 250 min, 270 min, 280 min or 300 min, but is not limited to the listed values, and other values not listed within the numerical range are also applicable.
  • the calcination device used in step (4) comprises any one of a tube furnace, a box furnace, a tunnel furnace, a push plate furnace or a track furnace, or a combination of at least two of them.
  • the present application obtains dense spherical silica by calcining powder A, removing organic matter in powder A, and densifying powder A, which is the chip-grade silica filler described in the present application.
  • the preparation method comprises the following steps:
  • step (2) stirring the catalyst aqueous solution and the solution A obtained in step (1) at 30-60° C. at a speed of 150-250 rpm until a white suspension is obtained, and then continuing to stir for 10-300 min; the mass ratio of the catalyst aqueous solution to the silicon source compound is (1-20):1;
  • step (3) (4) calcining the powder A obtained in step (3) at 500-1300° C. to obtain the chip-grade silica filler, with the calcination time being 10-300 min.
  • an embodiment of the present application provides a silicon dioxide filler for chip-level bottom filling glue, and the chip-level silicon dioxide filler is obtained by the preparation method described in the first aspect.
  • the silicon dioxide filler for chip-level bottom filling glue provided in the present application has a purity of ⁇ 99.9wt% and a sphericity of ⁇ 98%; its particle size distribution D50 is 0.3-8 ⁇ m, and D100 is 1-20 ⁇ m, which meets the requirements of flip chip packaging.
  • an embodiment of the present application provides an application of a silicon dioxide filler for a chip-level bottom filling adhesive, wherein the silicon dioxide filler for a chip-level bottom filling adhesive is used for chip packaging.
  • the silicon dioxide filler for chip-level bottom filling glue prepared by the preparation method described in the embodiment of the present application has a purity of ⁇ 99.9%, a sphericity of 98 ⁇ %, and a low impurity ion content; and the particle size distribution D50 is 0.3-8 ⁇ m, and D100 is 1-20 ⁇ m, which meets the requirements of flip chip packaging.
  • the average particle size and the cut-off point of the prepared silicon dioxide can be controlled, without the need for subsequent classification, screening and grading process operations.
  • FIG1 is a scanning electron microscope image of the chip-level silica filler obtained in Example 1 of the present application.
  • FIG2 is a particle size distribution diagram of the chip-grade silica filler obtained in Example 1 of the present application.
  • FIG3 is a scanning electron microscope image of the chip-level silica filler obtained in Example 2 of the present application.
  • FIG. 4 is a particle size distribution diagram of the chip-grade silica filler obtained in Example 2 of the present application.
  • This embodiment provides a method for preparing a chip-level silica filler, the preparation method comprising the following steps:
  • a co-solvent solution is composed of a co-solvent and deionized water in a mass ratio of 2:5; the co-solvent is cyclohexane; and the silicon source compound is (3-mercaptopropyl)trimethoxysilane;
  • step (2) stirring and mixing a 10 wt % aqueous catalyst solution and the solution A obtained in step (1) at 40° C. and 200 rpm until a white suspension is obtained, and then stirring is continued for 120 min;
  • the aqueous catalyst solution is ammonia water; and the mass ratio of the aqueous catalyst solution to the silicon source compound is 10:1;
  • step (3) Centrifuging the white suspension obtained in step (2) to obtain a white muddy substance, drying at 60° C. for 14 h to remove physically adsorbed water to obtain powder A;
  • step (3) The powder A obtained in step (3) is calcined in a tunnel furnace, and the temperature in the tunnel furnace rises to 1000° C. in 100 minutes. Powder A stays in the tunnel furnace for 120 minutes. During this process, organic matter in powder A is removed and powder A is densified to obtain the chip-grade silica filler.
  • FIG1 The SEM image of the chip-grade silica filler obtained in this example is shown in FIG1 , and its particle size distribution diagram is shown in FIG2 .
  • This embodiment provides a method for preparing a chip-level silica filler, the preparation method comprising the following steps:
  • a co-solvent solution is composed of a co-solvent and deionized water in a mass ratio of 1:5; the co-solvent is cyclohexane; and the silicon source compound is (3-mercaptopropyl)trimethoxysilane;
  • step (2) stirring a 5 wt % catalyst aqueous solution and the solution A obtained in step (1) at 35° C. and 180 rpm until a white suspension is obtained, and then stirring is continued for 200 min;
  • the catalyst aqueous solution is ammonia water; and the mass ratio of the catalyst aqueous solution to the silicon source compound is 15:1;
  • step (3) filtering the white suspension obtained in step (2) to obtain white blocks, drying at 120° C. for 12 h to remove physically adsorbed water to obtain powder A;
  • step (3) The powder A obtained in step (3) is calcined in a box furnace, and the temperature in the tunnel furnace rises to 1100° C. in 120 min, and the powder A stays therein for 90 min. During this process, the organic matter in the powder A is removed, and the powder A is densified to obtain the chip-grade silica filler.
  • the SEM image of the chip-grade silica filler obtained in this example is shown in FIG3 , and its particle size distribution diagram is shown in FIG4 .
  • This embodiment provides a method for preparing a chip-level silica filler, the preparation method comprising the following steps:
  • a co-solvent solution is composed of a co-solvent and deionized water in a mass ratio of 1:8; the co-solvent is cyclohexane; and the silicon source compound is (3-mercaptopropyl)trimethoxysilane;
  • step (2) stirring and mixing a 15 wt % catalyst aqueous solution and the solution A obtained in step (1) at 210 rpm at 50° C. until a white suspension is obtained, and then stirring is continued for 300 min; the catalyst aqueous solution is ammonia water; and the mass ratio of the catalyst aqueous solution to the silicon source compound is 5:1;
  • step (3) filtering the white suspension obtained in step (2) to obtain white blocks, drying at 180° C. for 9 h to remove physically adsorbed water to obtain powder A;
  • step (3) The powder A obtained in step (3) is calcined in a push plate furnace, and the temperature in the tunnel furnace rises to 1000° C. in 240 minutes, and the powder A stays therein for 300 minutes. During this process, the organic matter in the powder A is removed, and the powder A is densified to obtain the chip-grade silica filler.
  • This embodiment provides a method for preparing a chip-level silica filler, the preparation method comprising the following steps:
  • a co-solvent solution is composed of a co-solvent and deionized water in a mass ratio of 1:10; the co-solvent is cyclohexane; and the silicon source compound is (3-mercaptopropyl)trimethoxysilane;
  • step (2) stirring a 0.1 wt% catalyst aqueous solution and the solution A obtained in step (1) at 60° C. and 150 rpm until a white suspension is obtained, and then stirring is continued for 60 min;
  • the catalyst aqueous solution is ammonia water; and the mass ratio of the catalyst aqueous solution to the silicon source compound is 20:1;
  • step (3) filtering the white suspension obtained in step (2) to obtain white blocks, drying at 200° C. for 16 h to remove physically adsorbed water to obtain powder A;
  • step (3) The powder A obtained in step (3) is calcined in a push plate furnace, and the temperature in the tunnel furnace rises to 900° C. in 160 min, and the powder A stays therein for 240 min. During this process, the organic matter in the powder A is removed, and the powder A is densified to obtain the chip-grade silica filler.
  • This embodiment provides a method for preparing a chip-level silica filler, the preparation method comprising the following steps:
  • a co-solvent solution is composed of a co-solvent and deionized water in a mass ratio of 1:1;
  • the co-solvent is cyclohexane;
  • the silicon source compound is (3-mercaptopropyl)trimethoxysilane;
  • step (2) stirring and mixing a 20 wt % catalyst aqueous solution and the solution A obtained in step (1) at 250 rpm at 30° C. until a white suspension is obtained, and then stirring is continued for 100 min;
  • the catalyst aqueous solution is ammonia water; and the mass ratio of the catalyst aqueous solution to the silicon source compound is 1:1;
  • step (3) filtering the white suspension obtained in step (2) to obtain white blocks, drying at 120° C. for 20 h to remove physically adsorbed water to obtain powder A;
  • step (3) The powder A obtained in step (3) is calcined in a box furnace, and the temperature in the tunnel furnace rises to 1200° C. in 200 min, and the powder A stays therein for 180 min. During this process, the organic matter in the powder A is removed, and the powder A is densified to obtain the chip-grade silica filler.
  • This embodiment provides a method for preparing a chip-level silica filler, which is the same as that of Embodiment 1 except that the co-solvent and other components are replaced with isopropanol.
  • This embodiment provides a method for preparing a chip-level silica filler, which is the same as that of Embodiment 1 except that the mass of the co-solvent and the like is replaced by methanol.
  • This embodiment provides a method for preparing a chip-level silica filler, which is the same as that of Embodiment 1 except that the mass of the co-solvent and the like is replaced by ethanol.
  • This embodiment provides a method for preparing a chip-level silica filler, which is the same as that of Embodiment 1 except that the mass of the silicon source compound is replaced by vinyltrimethoxysilane.
  • This embodiment provides a method for preparing a chip-level silica filler, which is the same as that of Embodiment 1 except that the mass of the silicon source compound is replaced by tetramethoxysilane.
  • This embodiment provides a method for preparing a chip-level silica filler, which is the same as that of Embodiment 1 except that the mass of the silicon source compound is replaced by tetrapropoxysilane.
  • This embodiment provides a method for preparing a chip-level silica filler, which is the same as that of Embodiment 1 except that the mass of the silicon source compound is replaced by sodium silicate.
  • This comparative example provides a method for preparing a silica filler, which is the same as Example 1 except that the co-solvent solution is not used, but the silicon source compound is directly mixed with the catalyst aqueous solution.
  • the purity, sphericity and particle size distribution of the silica fillers obtained in the above embodiments and comparative examples were tested.
  • the purity was tested in accordance with SJ/T 3228.4-2016, the sphericity was tested in accordance with GB/T 32661-2016, and the particle size distribution was tested in accordance with GB/T 19077-2016.
  • the purity of the silicon dioxide filler for chip-level bottom filling glue prepared by the preparation method described in the present application is ⁇ 99.9%, the sphericity is 98 ⁇ %, and the impurity ion content is low; and the particle size distribution D50 is 0.3-8 ⁇ m, and D100 is 1-20 ⁇ m, which meets the requirements of flip chip packaging.
  • the ratio of the co-solvent, the catalyst and the silicon source compound the average particle size and the cut-off point of the prepared silicon dioxide can be controlled, without the need for subsequent classification, screening and grading process operations.

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Abstract

一种芯片级底部填充胶用二氧化硅填料及其制备方法与应用，所述制备方法包括如下步骤：混合助溶剂溶液与硅源化合物，得到溶液 A；混合催化剂水溶液与所得溶液 A，得到悬浊液；固液分离所得悬浊液，干燥后，得到粉体 A；煅烧所得粉体 A，得到所述芯片级 SiO 2填料。所述制备方法制备得到的芯片级二氧化硅填料的纯度高、球形度高、杂质离子含量低，并且粒径分布满足倒装芯片封装的要求。并且，通过助溶剂、催化剂以及硅源化合物配比的调控，制备得到的二氧化硅的平均粒径和切断点可以得到控制，无需后续的分级、筛分和级配工艺操作。

Description

芯片级底部填充胶用二氧化硅填料及其制备方法与应用 技术领域
本申请涉及半导体技术领域，例如一种二氧化硅，尤其涉及一种芯片级底部填充胶用二氧化硅填料及其制备方法与应用。
背景技术
二氧化硅(SiO 2)作为无机填料被广泛应用于芯片级底部填充胶中，对芯片封装后的应力匹配、力学保护和可靠性等至关重要。随着电子设备逐渐向薄型化、高集成度和多功能化方向发展，集成电路(IC)的封装形式已经开始由2D封装向2.1D、2.5D与3D封装过渡，在高密度互联发展趋势下，芯片之间、微凸点之间以及芯片和基板之间的间距越来越窄，对SiO 2的粒径、杂质元素以及放射性元素含量提出了新的要求。目前，制备SiO 2的方法包括熔融法、燃爆法和化学合成法，虽然均能制备出不同粒径的SiO 2，但仍然存在一定的弊端。
熔融法生产SiO 2是以结晶二氧化硅为原料，在制备SiO 2之前，需要对结晶二氧化硅进行破碎、超细粉碎、筛分和提纯处理，然后将提纯后的粉末送入可燃气-氧气产生的高温场中，经高温熔融之后，通过控制条件使其在冷却过程中的表面张力得到调控，最终冷却固化成球形SiO 2。
但熔融法得到的SiO 2的平均粒径较大，球形度不高，并且由于结晶二氧化硅来源于天然石英矿，放射性元素U含量较高。
燃爆法是以超细硅粉为原料，在制备球形SiO 2之前，需要对硅粉进行超细粉碎和筛分处理，燃爆法将甲烷、丙烷、氢气或乙炔等可燃气体通过喷烧器在含氧气氛中燃烧形成火焰，同时将超细硅粉送入火焰中形成粉尘云，引发燃爆得到球状SiO 2超微粒子。燃爆法得到的SiO 2的球形度较高、表面光滑，但是超细硅粉容易引发粉尘爆炸，对空间及设备的安全性要求极高。而且，若要得到指定粒度分布的球形SiO 2，还需要对SiO 2产品进行再分级、筛分和级配，生产工序较为繁琐。
化学合成法则是以硅化合物为原料，在分散剂、控制剂和催化剂等的作用下，经过成核和生长过程得到高纯球形SiO 2。化学合成法通过控制反应温度、原料配比和添加次序等因素，可以对SiO 2的形貌、粒径等进行调控，同时SiO 2 中的杂质离子和放射性元素含量等均可以通过原料的提纯实现进一步的降低。
本申请在化学合成法的基础上提供了一种SiO 2的制备方法，该制备方法得到的SiO 2的纯度高、球形度高、杂质离子含量低，并且粒径分布满足倒装芯片封装的场景要求。而且，本申请提供的制备方法能够灵活控制SiO 2的平均粒径以及切断点，无需后续的分级、筛分和级配的工艺处理。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请实施例提供一种芯片级底部填充胶用二氧化硅填料及其制备方法与应用，所述制备方法得到的芯片级二氧化硅填料的纯度高、球形度好，且制备条件易于调控，便于对最终所得芯片级二氧化硅填料的平均粒径进行调控。
第一方面，本申请实施例提供了一种芯片级底部填充胶用二氧化硅填料的制备方法，所述制备方法包括如下步骤：
(1)混合助溶剂溶液与硅源化合物，得到溶液A；
(2)混合催化剂水溶液与步骤(1)所得溶液A，得到悬浊液；
(3)固液分离步骤(2)所得悬浊液，干燥后，得到粉体A；
(4)煅烧步骤(3)所得粉体A，得到所述芯片级二氧化硅填料。
本申请提供的制备方法首先混合硅源化合物与助溶剂，在催化剂水溶液的催化作用下，硅源化合物逐渐水解、缩合，得到稳定溶胶体系；而溶胶聚合形成的凝胶经过固液分离、干燥以及烧结后，形成的芯片级二氧化硅的纯度高、球形度好，且粒径分布满足倒装芯片的封装要求。
优选地，步骤(1)所述助溶剂溶液包括质量比(10-50):(10-100)的助溶剂与水，例如可以是50:10、50:25、50:30、50:40、10:10、10:20、10:30、10:40、10:50、10:60、10:70、10:80、10:90或10:100，但不限于所列举的数值，数值范围内其它未列举的数值同样适用。
优选地，所述助溶剂包括甲醇、乙醇、异丙醇或环己烷中的任意一种或至少两种的组合，典型但非限制性的组合包括甲醇与乙醇的组合，乙醇与异丙醇的组合，异丙醇与环己烷的组合，甲醇、乙醇与异丙醇的组合，乙醇、异丙醇与环己烷的组合，或甲醇、乙醇、异丙醇与环己烷的组合。
优选地，步骤(1)所述助溶剂溶液与硅源化合物的质量比为(1-50):1，例如可以是1:1、5:1、10:1、20:1、30:1、40:1或50:1，但不限于所列举的数值，数值范围内其它未列举的数值同样适用。
优选地，步骤(1)所述硅源化合物包括有机硅、硅氧烷或硅酸盐中的任意一种或至少两种的组合，例如可以是有机硅与硅氧烷的组合，硅氧烷与硅酸盐的组合，有机硅与硅酸盐的组合，或有机硅、硅氧烷与硅酸盐的组合。
优选地，所述有机硅包括乙烯基三甲氧基硅烷、乙烯基三乙氧基硅烷、(3-巯基丙基)三甲氧基硅烷、烯丙基三甲氧基硅烷、3-缩水甘油基氧基丙基三甲氧基硅烷或十二烷基三甲氧基硅烷中的任意一种或至少两种的组合，典型但非限制性的组合包括乙烯基三甲氧基硅烷与乙烯基三乙氧基硅烷的组合，(3-巯基丙基)三甲氧基硅烷与烯丙基三甲氧基硅烷的组合，3-缩水甘油基氧基丙基三甲氧基硅烷与十二烷基三甲氧基硅烷的组合，乙烯基三甲氧基硅烷、乙烯基三乙氧基硅烷与(3-巯基丙基)三甲氧基硅烷的组合，烯丙基三甲氧基硅烷、3-缩水甘油基氧基丙基三甲氧基硅烷与十二烷基三甲氧基硅烷的组合，或，乙烯基三甲氧基硅烷、乙烯基三乙氧基硅烷、(3-巯基丙基)三甲氧基硅烷、烯丙基三甲氧基硅烷、3-缩水甘油基氧基丙基三甲氧基硅烷与十二烷基三甲氧基硅烷的组合。
优选地，所述硅氧烷包括四甲氧基硅烷、四乙氧基硅烷或四丙氧基硅烷中的任意一种或至少两种的组合，典型但非限制性的组合包括四甲氧基硅烷与四乙氧基硅烷的组合，四乙氧基硅烷与四丙氧基硅烷的组合，四甲氧基硅烷与四丙氧基硅烷的组合，或四甲氧基硅烷、四乙氧基硅烷以及四丙氧基硅烷的组合。
优选地，所述硅酸盐包括硅酸钠。
优选地，步骤(2)所述混合的温度为30-60℃，例如可以是30℃、35℃、40℃、45℃、50℃、55℃或60℃，但不限于所列举的数值，数值范围内其它未列举的数值同样适用。
优选地，步骤(2)所述催化剂水溶液与硅源化合物的质量比为(1-20):1，例如可以是1:1、3:1、5:1、8:1、10:1、12:1、15:1、18:1或20:1，但不限于所列举的数值，数值范围内其它未列举的数值同样适用。
优选地，步骤(2)所述催化剂水溶液的浓度为0.1-20wt％，例如可以是0.1wt％、1wt％、3wt％、5wt％、8wt％、10wt％、12wt％、15wt％、16wt％、18wt％或20wt％，但不限于所列举的数值，数值范围内其它未列举的数值同样适用。
优选地，步骤(2)所述催化剂水溶液包括无机酸水溶液、无机碱水溶液或有机酸水溶液中的任意一种或至少两种的组合。
优选地，步骤(2)所述混合包括搅拌混合至得到悬浊液，然后继续搅拌10-300min，例如可以是10min、30min、50min、60min、80min、100min、120min、150min、160min、180min、200min、210min、240min、250min、270min、280min或300min，但不限于所列举的数值，数值范围内其它未列举的数值同样适用。
优选地，所述搅拌混合的转速为150-250rpm，例如可以是150rpm、160rpm、180rpm、200rpm、210rpm、240rpm或250rpm，但不限于所列举的数值，数值范围内其它未列举的数值同样适用。
优选地，步骤(2)所得悬浊液为白色悬浊液。
优选地，步骤(3)所述固液分离的方法包括压滤、离心或沉降中的任意一种或至少两种的组合，典型但非限制性的组合包括压滤与离心的组合，离心与沉降的组合，压滤与沉降的组合，或压滤、离心与沉降的组合。
优选地，步骤(3)所述干燥的温度为30-220℃，例如可以是30℃、50℃、60℃、80℃、100℃、120℃、150℃、160℃、180℃、200℃或220℃，但不限于所列举的数值，数值范围内其它未列举的数值同样适用。
优选地，步骤(3)所述干燥的时间为1-24h，例如可以是1h、2h、3h、5h、6h、8h、10h、12h、15h、16h、18h、20h、21h或24h，但不限于所列举的数值，数值范围内其它未列举的数值同样适用。
本申请通过固液分离后进行干燥，实现了物理吸附水的去除，从而得到粉体A。
进一步优选地，所述制备方法包括固液分离后对所得固体进行洗涤，以去除硅源化合物中存在的杂质，因而可以降低对硅源化合物的纯度要求，还能够保证最终所得芯片级二氧化硅填料的纯度。
优选地，步骤(4)所述煅烧处理的温度为500-1300℃，例如可以是500℃、600℃、700℃、800℃、900℃、1000℃、1100℃、1200℃或1300℃，但不限于所列举的数值，数值范围内其它未列举的数值同样适用。
优选地，步骤(4)所述煅烧处理的时间为10-300min，例如可以是10min、30min、50min、60min、80min、100min、120min、150min、160min、180min、200min、210min、240min、250min、270min、280min或300min，但不限于所列 举的数值，数值范围内其它未列举的数值同样适用。
优选地，步骤(4)所述煅烧所用煅烧装置包括管式炉、箱式炉、隧道炉、推板炉或轨道炉中的任意一种或至少两种的组合。
本申请通过对粉体A进行煅烧，将粉体A中的有机物去除，并对粉体A进行致密化，从而得到致密的球形二氧化硅，即为本申请所述芯片级二氧化硅填料。
作为本申请第一方面所述制备方法的优选技术方案，所述制备方法包括如下步骤：
(1)混合质量比为(1-50):1的助溶剂溶液与硅源化合物，得到溶液A；所述助溶剂溶液包括质量比(10-50):(10-100)的助溶剂与水；
(2)30-60℃的条件下，以150-250rpm的转速搅拌混合催化剂水溶液与步骤(1)所得溶液A至得到白色悬浊液，然后继续搅拌10-300min；所述催化剂水溶液与硅源化合物的质量比为(1-20):1；
(3)固液分离步骤(2)所得悬浊液，30-220℃干燥1-24h后，得到粉体A；
(4)500-1300℃煅烧步骤(3)所得粉体A，得到所述芯片级二氧化硅填料，煅烧时间为10-300min。
第二方面，本申请实施例提供了一种芯片级底部填充胶用二氧化硅填料，所述芯片级二氧化硅填料由第一方面所述制备方法得到。
本申请提供的芯片级底部填充胶用二氧化硅填料的纯度≥99.9wt％且球形度≥98％；其粒径分布D50为0.3-8μm，D100为1-20μm，满足倒装芯片封装的要求。
第三方面，本申请实施例提供了一种芯片级底部填充胶用二氧化硅填料的应用，所述芯片级底部填充胶用二氧化硅填料用于芯片封装。
相对于相关技术，本申请实施例具有以下有益效果：
本申请实施例所述制备方法制备得到的芯片级底部填充胶用二氧化硅填料的纯度≥99.9％、球形度98≥％，杂质离子含量低；并且粒径分布D50为0.3-8μm，D100为1-20μm，满足倒装芯片封装的要求。并且，通过助溶剂、催化剂以及硅源化合物配比的调控，制备得到的二氧化硅的平均粒径和切断点可以得到控制，无需后续的分级、筛分和级配工艺操作。
在阅读并理解了附图和详细描述后，可以明白其它方面。
附图说明
附图用来提供对本文技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本文的技术方案，并不构成对本文技术方案的限制。
图1为本申请实施例1所得芯片级二氧化硅填料的扫描电镜图；
图2为本申请实施例1所得芯片级二氧化硅填料的粒度分布图；
图3为本申请实施例2所得芯片级二氧化硅填料的扫描电镜图；
图4为本申请实施例2所得芯片级二氧化硅填料的粒度分布图。
具体实施方式
下面通过具体实施方式来进一步说明本申请的技术方案。本领域技术人员应该明了，所述实施例仅仅是帮助理解本申请，不应视为对本申请的具体限制。
实施例1
本实施例提供了一种芯片级二氧化硅填料的制备方法，所述制备方法包括如下步骤：
(1)按照质量比30:1混合助溶剂溶液与硅源化合物，得到溶液A；所述助溶剂溶液由质量比2:5的助溶剂与去离子水组成；所述助溶剂为环己烷；所述硅源化合物为(3-巯基丙基)三甲氧基硅烷；
(2)40℃的条件下，200rpm搅拌混合10wt％的催化剂水溶液与步骤(1)所得溶液A至得到白色悬浊液，然后继续搅拌120min；所述催化剂水溶液为氨水；所述催化剂水溶液与硅源化合物的质量比为10:1；
(3)离心步骤(2)所得白色悬浊液得到白色泥状物，60℃干燥14h，除去物理吸附水得到粉体A；
(4)步骤(3)所得粉体A在隧道炉内进行煅烧，隧道炉内温度在100min上升至1000℃，粉体A在其中停留120min，在此过程中，粉体A中的有机物被除去，且实现了粉体A的致密化，得到所述芯片级二氧化硅填料。
本实施例所得芯片级二氧化硅填料的SEM图如图1所示，其粒度分布图如图2所示。
实施例2
本实施例提供了一种芯片级二氧化硅填料的制备方法，所述制备方法包括 如下步骤：
(1)按照质量比15:1混合助溶剂溶液与硅源化合物，得到溶液A；所述助溶剂溶液由质量比1:5的助溶剂与去离子水组成；所述助溶剂为环己烷；所述硅源化合物为(3-巯基丙基)三甲氧基硅烷；
(2)35℃的条件下，180rpm搅拌混合浓度为5wt％的催化剂水溶液与步骤(1)所得溶液A至得到白色悬浊液，然后继续搅拌200min；所述催化剂水溶液为氨水；所述催化剂水溶液与硅源化合物的质量比为15:1；
(3)压滤步骤(2)所得白色悬浊液得到白色块状物，120℃干燥12h，除去物理吸附水得到粉体A；
(4)步骤(3)所得粉体A在箱式炉内进行煅烧，隧道炉内温度在120min上升至1100℃，粉体A在其中停留90min，在此过程中，粉体A中的有机物被除去，且实现了粉体A的致密化，得到所述芯片级二氧化硅填料。
本实施例所得芯片级二氧化硅填料的SEM图如图3所示，其粒度分布图如图4所示。
实施例3
本实施例提供了一种芯片级二氧化硅填料的制备方法，所述制备方法包括如下步骤：
(1)按质量比40:1混合助溶剂溶液与硅源化合物，得到溶液A；所述助溶剂溶液由质量比1:8的助溶剂与去离子水组成；所述助溶剂为环己烷；所述硅源化合物为(3-巯基丙基)三甲氧基硅烷；
(2)50℃的条件下，210rpm搅拌混合浓度为15wt％的催化剂水溶液与步骤(1)所得溶液A至得到白色悬浊液，然后继续搅拌300min；所述催化剂水溶液为氨水；所述催化剂水溶液与硅源化合物的质量比为5:1；
(3)压滤步骤(2)所得白色悬浊液得到白色块状物，180℃干燥9h，除去物理吸附水得到粉体A；
(4)步骤(3)所得粉体A在推板炉内进行煅烧，隧道炉内温度在240min上升至1000℃，粉体A在其中停留300min，在此过程中，粉体A中的有机物被除去，且实现了粉体A的致密化，得到所述芯片级二氧化硅填料。
实施例4
本实施例提供了一种芯片级二氧化硅填料的制备方法，所述制备方法包括 如下步骤：
(1)按照质量比1:1混合助溶剂溶液与硅源化合物，得到溶液A；所述助溶剂溶液由质量比1:10的助溶剂与去离子水组成；所述助溶剂为环己烷；所述硅源化合物为(3-巯基丙基)三甲氧基硅烷；
(2)60℃的条件下，150rpm搅拌混合浓度为0.1wt％的催化剂水溶液与步骤(1)所得溶液A至得到白色悬浊液，然后继续搅拌60min；所述催化剂水溶液为氨水；所述催化剂水溶液与硅源化合物的质量比为20:1；
(3)压滤步骤(2)所得白色悬浊液得到白色块状物，200℃干燥16h，除去物理吸附水得到粉体A；
(4)步骤(3)所得粉体A在推板炉内进行煅烧，隧道炉内温度在160min上升至900℃，粉体A在其中停留240min，在此过程中，粉体A中的有机物被除去，且实现了粉体A的致密化，得到所述芯片级二氧化硅填料。
实施例5
本实施例提供了一种芯片级二氧化硅填料的制备方法，所述制备方法包括如下步骤：
(1)按照质量比50:1混合助溶剂溶液与硅源化合物，得到溶液A；所述助溶剂溶液由质量比1:1的助溶剂与去离子水组成；所述助溶剂为环己烷；所述硅源化合物为(3-巯基丙基)三甲氧基硅烷；
(2)30℃的条件下，250rpm搅拌混合浓度为20wt％的催化剂水溶液与步骤(1)所得溶液A至得到白色悬浊液，然后继续搅拌100min；所述催化剂水溶液为氨水；所述催化剂水溶液与硅源化合物的质量比为1:1；
(3)压滤步骤(2)所得白色悬浊液得到白色块状物，120℃干燥20h，除去物理吸附水得到粉体A；
(4)步骤(3)所得粉体A在箱式炉内进行煅烧，隧道炉内温度在200min上升至1200℃，粉体A在其中停留180min，在此过程中，粉体A中的有机物被除去，且实现了粉体A的致密化，得到所述芯片级二氧化硅填料。
实施例6
本实施例提供了一种芯片级二氧化硅填料的制备方法，除了将助溶剂等质量替换为异丙醇外，其余均与实施例1相同。
实施例7
本实施例提供了一种芯片级二氧化硅填料的制备方法，除了将助溶剂等质量替换为甲醇外，其余均与实施例1相同。
实施例8
本实施例提供了一种芯片级二氧化硅填料的制备方法，除了将助溶剂等质量替换为乙醇外，其余均与实施例1相同。
实施例9
本实施例提供了一种芯片级二氧化硅填料的制备方法，除了将硅源化合物等质量替换为乙烯基三甲氧基硅烷外，其余均与实施例1相同。
实施例10
本实施例提供了一种芯片级二氧化硅填料的制备方法，除了将硅源化合物等质量替换为四甲氧基硅烷外，其余均与实施例1相同。
实施例11
本实施例提供了一种芯片级二氧化硅填料的制备方法，除了将硅源化合物等质量替换为四丙氧基硅烷外，其余均与实施例1相同。
实施例12
本实施例提供了一种芯片级二氧化硅填料的制备方法，除了将硅源化合物等质量替换为硅酸钠外，其余均与实施例1相同。
对比例1
本对比例提供了一种二氧化硅填料的制备方法，除了不使用助溶剂溶液，而是直接将硅源化合物与催化剂水溶液混合外，其余均与实施例1相同。
性能测试
对上述实施例以及对比例所得二氧化硅填料的纯度、球形度以及粒径分布进行测试，纯度按照SJ/T 3228.4-2016进行测试，球形度按照GB/T 32661-2016进行测试，粒径分布按照GB/T 19077-2016进行测试。
所得结果如表1所示。
表1
Figure PCTCN2022139185-appb-000001
Figure PCTCN2022139185-appb-000002
综上所述，本申请所述制备方法制备得到的芯片级底部填充胶用二氧化硅填料的纯度≥99.9％、球形度98≥％，杂质离子含量低；并且粒径分布D50为0.3-8μm，D100为1-20μm，满足倒装芯片封装的要求。并且，通过助溶剂、催化剂以及硅源化合物配比的调控，制备得到的二氧化硅的平均粒径和切断点可以得到控制，无需后续的分级、筛分和级配工艺操作。
以上所述仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，所属技术领域的技术人员应该明了，任何属于本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，均落在本申请的保护范围和公开范围之内。

Claims (12)

  1. 一种芯片级底部填充胶用二氧化硅填料的制备方法，其包括如下步骤：
    (1)混合助溶剂溶液与硅源化合物，得到溶液A；
    (2)混合催化剂水溶液与步骤(1)所得溶液A，得到悬浊液；
    (3)固液分离步骤(2)所得悬浊液，干燥后，得到粉体A；
    (4)煅烧步骤(3)所得粉体A，得到所述芯片级二氧化硅填料。
  2. 根据权利要求1所述的制备方法，其中，步骤(1)所述助溶剂溶液包括质量比(10-50):(10-100)的助溶剂与水。
  3. 根据权利要求1或2所述的制备方法，其中所述助溶剂包括甲醇、乙醇、异丙醇或环己烷中的任意一种或至少两种的组合。
  4. 根据权利要求1-3任一项所述的制备方法，其中，步骤(1)所述助溶剂溶液与硅源化合物的质量比为(1-50):1。
  5. 根据权利要求1-4任一项所述的制备方法，其中，步骤(1)所述硅源化合物包括有机硅、硅氧烷或硅酸盐中的任意一种或至少两种的组合；
    优选地，所述有机硅包括乙烯基三甲氧基硅烷、乙烯基三乙氧基硅烷、(3-巯基丙基)三甲氧基硅烷、烯丙基三甲氧基硅烷、3-缩水甘油基氧基丙基三甲氧基硅烷或十二烷基三甲氧基硅烷中的任意一种或至少两种的组合；
    优选地，所述硅氧烷包括四甲氧基硅烷、四乙氧基硅烷或四丙氧基硅烷中的任意一种或至少两种的组合；
    优选地，所述硅酸盐包括硅酸钠。
  6. 根据权利要求1-5任一项所述的制备方法，其中，步骤(2)所述混合的温度为30-60℃；
    优选地，步骤(2)所述催化剂水溶液与硅源化合物的质量比为(1-20):1；
    优选地，步骤(2)所述催化剂水溶液的浓度为0.1-20wt％；
    优选地，步骤(2)所述催化剂水溶液包括无机酸水溶液、无机碱水溶液或有机酸水溶液中的任意一种或至少两种的组合。
  7. 根据权利要求1-6任一项所述的制备方法，其中，步骤(2)所述混合包括搅拌混合至得到悬浊液，然后继续搅拌10-300min；
    优选地，所述搅拌混合的转速为150-250rpm；
    优选地，步骤(2)所得悬浊液为白色悬浊液。
  8. 根据权利要求1-7任一项所述的制备方法，其中，步骤(3)所述固液分 离的方法包括压滤、离心或沉降中的任意一种或至少两种的组合；
    优选地，步骤(3)所述干燥的温度为30-220℃；
    优选地，步骤(3)所述干燥的时间为1-24h。
  9. 根据权利要求1-8任一项所述的制备方法，其中，步骤(4)所述煅烧处理的温度为500-1300℃；
    优选地，步骤(4)所述煅烧处理的时间为10-300min；
    优选地，步骤(4)所述煅烧所用煅烧装置包括管式炉、箱式炉、隧道炉、推板炉或轨道炉中的任意一种或至少两种的组合。
  10. 根据权利要求1-9任一项所述的制备方法，其中，所述制备方法包括如下步骤：
    (1)混合质量比为(1-50):1的助溶剂溶液与硅源化合物，得到溶液A；所述助溶剂溶液包括质量比(10-50):(10-100)的助溶剂与水；
    (2)30-60℃的条件下，以150-250rpm的转速搅拌混合催化剂水溶液与步骤(1)所得溶液A至得到白色悬浊液，然后继续搅拌10-300min；所述催化剂水溶液与硅源化合物的质量比为(1-20):1；
    (3)固液分离步骤(2)所得悬浊液，30-220℃干燥1-24h后，得到粉体A；
    (4)500-1300℃煅烧步骤(3)所得粉体A，得到所述芯片级二氧化硅填料，煅烧时间为10-300min。
  11. 一种芯片级底部填充胶用二氧化硅填料，其中，所述芯片级二氧化硅填料由权利要求1-10任一项所述制备方法得到。
  12. 一种如权利要求11所述的芯片级底部填充胶用二氧化硅填料的应用，其中，所述芯片级二氧化硅填料用于芯片封装。
PCT/CN2022/139185 2022-11-23 2022-12-15 芯片级底部填充胶用二氧化硅填料及其制备方法与应用 WO2024108695A1 (zh)

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