WO2024093022A1 - 一种基于半加成工艺的精细线路板及其制备方法、表面处理方法和应用 - Google Patents
一种基于半加成工艺的精细线路板及其制备方法、表面处理方法和应用 Download PDFInfo
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- WO2024093022A1 WO2024093022A1 PCT/CN2023/070727 CN2023070727W WO2024093022A1 WO 2024093022 A1 WO2024093022 A1 WO 2024093022A1 CN 2023070727 W CN2023070727 W CN 2023070727W WO 2024093022 A1 WO2024093022 A1 WO 2024093022A1
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- substrate
- fine circuit
- fine
- circuit board
- surface treatment
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 238000004381 surface treatment Methods 0.000 title claims abstract description 32
- 239000000654 additive Substances 0.000 title claims abstract description 26
- 238000002360 preparation method Methods 0.000 title claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 103
- 125000003396 thiol group Chemical group [H]S* 0.000 claims abstract description 21
- TXDNPSYEJHXKMK-UHFFFAOYSA-N sulfanylsilane Chemical compound S[SiH3] TXDNPSYEJHXKMK-UHFFFAOYSA-N 0.000 claims abstract description 17
- 230000004048 modification Effects 0.000 claims abstract description 16
- 238000012986 modification Methods 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 17
- 239000010949 copper Substances 0.000 claims description 17
- 238000005234 chemical deposition Methods 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 5
- UUEWCQRISZBELL-UHFFFAOYSA-N 3-trimethoxysilylpropane-1-thiol Chemical compound CO[Si](OC)(OC)CCCS UUEWCQRISZBELL-UHFFFAOYSA-N 0.000 claims description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000009832 plasma treatment Methods 0.000 claims description 4
- IKYAJDOSWUATPI-UHFFFAOYSA-N 3-[dimethoxy(methyl)silyl]propane-1-thiol Chemical compound CO[Si](C)(OC)CCCS IKYAJDOSWUATPI-UHFFFAOYSA-N 0.000 claims description 3
- DCQBZYNUSLHVJC-UHFFFAOYSA-N 3-triethoxysilylpropane-1-thiol Chemical compound CCO[Si](OCC)(OCC)CCCS DCQBZYNUSLHVJC-UHFFFAOYSA-N 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910021645 metal ion Inorganic materials 0.000 abstract description 5
- 230000009920 chelation Effects 0.000 abstract description 4
- 125000002887 hydroxy group Chemical group [H]O* 0.000 abstract description 2
- 238000004806 packaging method and process Methods 0.000 abstract description 2
- 238000006177 thiolation reaction Methods 0.000 abstract 1
- 230000007797 corrosion Effects 0.000 description 7
- 238000005260 corrosion Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 3
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 2
- 229910001431 copper ion Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
Definitions
- the present invention belongs to the technical field of chip packaging, and in particular relates to a fine circuit board based on a semi-additive process, a preparation method thereof, a surface treatment method and an application thereof.
- the semi-additive process is a mature production method for high-density IC substrates when producing fine circuits.
- the main steps of this method are to first apply a copper seed layer on the base dielectric material, then pattern the fine circuits and finally remove unnecessary copper and seed layers.
- fine circuits prepared by the semi-additive process have been widely used in high-density interconnect circuit boards with a line width and line spacing of less than 50 microns.
- Circuit boards produced by the semi-additive process have advantages such as ultra-fine line width and line spacing and low metal line roughness.
- advantages such as ultra-fine line width and line spacing and low metal line roughness.
- there are still problems such as poor adhesion between the seed layer and the substrate and the resulting sidewall corrosion. If the adhesion of the seed layer under the fine line can be improved by patterning, the problem of sidewall corrosion and line corrosion and shedding can be effectively reduced, effectively improving the yield and production efficiency of the system.
- one of the purposes of the present invention is to provide a surface treatment method for a fine circuit substrate, which can effectively improve the metal ion adsorption performance of the substrate and improve the adhesion between the substrate and the fine circuit.
- a second object of the present invention is to provide an application of a surface treatment method for a fine circuit substrate.
- the third object of the present invention is to provide a method for preparing a fine circuit board based on a semi-additive process, thereby improving the interface bonding strength between the fine circuit and the substrate, making the thickness of the fine circuit controllable, and improving the problems of side wall corrosion and circuit shedding of the fine circuit board.
- a fourth object of the present invention is to provide a fine circuit board based on a semi-additive process, with a small line width and line spacing, and the fine circuit is not easy to fall off.
- a surface treatment method for a fine circuit substrate comprises the following steps:
- the photoresist dry film is removed to obtain a substrate with a surface modified in a fine circuit area.
- the hydrophilic modification treatment method is at least one of plasma treatment, ultraviolet treatment and ozone treatment.
- the material of the substrate is any one of glass, ceramic, silicon wafer, epoxy resin, BT resin, and PI resin, or a combination of two or more thereof.
- step 3 the operation of the mercapto treatment is: selectively depositing gaseous mercaptosilane in the fine circuit pattern area of the substrate.
- the mercaptosilane is at least one of 3-mercaptopropyltrimethoxysilane, 3-mercaptopropyltriethoxysilane and mercaptopropylmethyldimethoxysilane.
- the invention discloses an application of a surface treatment method for a fine circuit substrate, and an application of the surface treatment method for a fine circuit substrate in the production of fine circuit boards.
- a method for preparing a fine circuit board based on a semi-additive process comprises the following steps:
- step S3 applying a second photoresist dry film to the seed layer in step S2, exposing and developing, and electroplating to form fine circuits;
- step S4 after removing the photoresist dry film from the substrate containing the fine circuit in step S3, etching to remove the seed layer, to obtain a fine circuit board.
- the metal material of the fine circuit is any one of copper, gold and silver, or a combination of two or more thereof.
- step S4 the line width of the fine circuit in the fine circuit board is 1-200 ⁇ m, and the line spacing is 1-200 ⁇ m.
- a fine circuit board based on a semi-additive process is prepared by adopting the preparation method of the fine circuit board based on a semi-additive process.
- the present invention has the following beneficial effects:
- the present invention discloses a surface treatment method for a fine circuit substrate, which firstly performs a hydrophilic modification treatment on the surface of the substrate to expose hydroxyl groups, and then selectively deposits mercaptosilane in the area required for the corresponding fine circuit, so that the substrate is covered with mercapto groups; the strong chelation between mercapto groups and metal ions can be used to effectively adsorb metal ions, and after reduction, a seed layer with strong interface bonding force with the substrate material is formed, thereby greatly improving the bonding force between the seed layer and the substrate.
- the present invention discloses a method for preparing a fine circuit board based on a semi-additive process.
- a copper seed layer is chemically deposited, so that the exposure area corresponding to the fine circuit has extremely high interface bonding force under the strong chelation effect of mercapto groups and copper ions; at the same time, the copper seed layer in the non-exposed area has weak bonding force with the substrate, and the copper seed layer is easy to be etched and removed.
- the fine circuit is further electroplated on the seed layer by the semi-additive process, the ultra-fine line width and line spacing processing effect of the fine circuit is achieved, and the problems of side wall corrosion and circuit shedding of the fine circuit are improved.
- the fine circuit board based on the semi-additive process of the present invention has small line width and line spacing, controllable thickness, low metal line roughness, and the fine line is not easy to fall off.
- FIG. 1 is a process flow chart of a surface treatment method for a fine circuit substrate of the present invention.
- FIG. 2 is a schematic diagram of the structure of a chemical deposition seed layer in a method for preparing a fine circuit board based on a semi-additive process of the present invention.
- FIG. 3 is a process flow chart of a method for preparing a fine circuit board based on a semi-additive process according to the present invention.
- FIG. 4 is a physical picture of a fine circuit board obtained in Example 4 of the present invention.
- a surface treatment method for a fine circuit substrate comprises the following steps:
- the surface of the substrate is subjected to hydrophilic modification treatment to form a hydroxylated surface to obtain a hydrophilic substrate;
- the material of the substrate is epoxy resin;
- the method of the hydrophilic modification treatment includes but is not limited to plasma treatment, ultraviolet treatment and ozone treatment.
- the method of the hydrophilic modification treatment in this embodiment is plasma treatment, the treatment power is 10-100W, and the treatment time is 10s-10min.
- the photoresist dry film is removed to obtain a substrate with a surface of a fine circuit area modified by mercapto grouping.
- the mercaptosilane is 3-mercaptopropyltrimethoxysilane; the specific operation of the mercapto treatment in this embodiment is: placing the substrate to be treated into a vacuum chamber, the volume of the chamber is 1-100L; then dripping 1-100ml of 3-mercaptopropyltrimethoxysilane liquid into the cavity, and then evacuating the cavity to maintain a vacuum degree of less than 0.1 atmospheres; leaving the vacuum for 30 minutes to complete the mercapto surface modification.
- a surface treatment method for a fine circuit substrate comprises the following steps:
- the surface of the substrate is subjected to hydrophilic modification treatment to form a hydroxylated surface, thereby obtaining a hydrophilic substrate;
- the material of the substrate is BT resin; and the method of the hydrophilic modification treatment is ultraviolet treatment.
- the photoresist dry film is removed to obtain a substrate with a surface of a fine circuit area modified by mercapto grouping.
- the operation of the mercapto treatment is: selectively depositing gaseous mercaptosilane in the fine circuit pattern area of the substrate; the mercaptosilane is 3-mercaptopropyltriethoxysilane.
- a surface treatment method for a fine circuit substrate comprises the following steps:
- the surface of the substrate is subjected to hydrophilic modification treatment to form a hydroxylated surface, thereby obtaining a hydrophilic substrate;
- the material of the substrate is PI resin; and the method of the hydrophilic modification treatment is ozone treatment.
- the photoresist dry film is removed to obtain a substrate with a surface of a fine circuit area modified by mercapto grouping.
- the operation of the mercapto treatment is: selectively depositing gaseous mercaptosilane in the fine circuit pattern area of the substrate; the mercaptosilane is mercaptopropylmethyldimethoxysilane.
- a method for preparing a fine circuit board based on a semi-additive process comprises the following steps:
- step S2 applying a second photoresist dry film 3 to the seed layer 2 in step S1, exposing and developing, and determining the area of the fine circuit;
- step S3 electroplating the substrate obtained in step S2, wherein the electroplated metal is copper, to form fine circuits 4;
- step S4 removing the photoresist dry film 3 from the blank containing fine circuits obtained in step S3 to expose the seed layer 2;
- step S5 etching the blank obtained in step S4 to remove the exposed seed layer 2, so as to obtain a fine circuit board; the fine circuits in the fine circuit board have a line width of 1-10 ⁇ m and a line spacing of 1-50 ⁇ m.
- the method for preparing a fine circuit board of this embodiment can form fine circuits with a line width and a line spacing within 10 ⁇ m, and the structure of the high-density circuits is complete without obvious sidewall corrosion and circuit shedding problems.
- a method for preparing a fine circuit board based on a semi-additive process comprises the following steps:
- step S2 applying a second photoresist dry film 3 to the seed layer 2 in step S1, exposing and developing, and determining the area of the fine circuit;
- step S3 electroplating the substrate obtained in step S2, wherein the electroplated metal is gold, to form fine circuits 4;
- step S4 removing the photoresist dry film 3 from the blank containing fine circuits obtained in step S3 to expose the seed layer 2;
- step S5 etching the blank obtained in step S4 to remove the exposed seed layer 2, so as to obtain a fine circuit board;
- the fine circuit in the fine circuit board has a line width of 10-30 ⁇ m and a line spacing of 10-100 ⁇ m.
- a method for preparing a fine circuit board based on a semi-additive process comprises the following steps:
- step S2 applying a second photoresist dry film 3 to the seed layer 2 in step S1, exposing and developing, and determining the area of the fine circuit;
- step S3 electroplating the substrate obtained in step S2, wherein the electroplated metal is silver, to form fine circuits 4;
- step S4 removing the photoresist dry film 3 from the blank containing fine circuits obtained in step S3 to expose the seed layer 2;
- step S5 etching the blank obtained in step S4 to remove the exposed seed layer 2, so as to obtain a fine circuit board; the fine circuits in the fine circuit board have a line width of 100-200 ⁇ m and a line spacing of 50-200 ⁇ m.
- the invention discloses a method for preparing a fine circuit board based on a semi-additive process.
- a substrate is selectively covered with a mercapto group by a surface treatment method, a copper seed layer is chemically deposited, so that an exposed area corresponding to the fine circuit has an extremely high interface bonding force under the strong chelation of the mercapto group and the copper ion; at the same time, the copper seed layer in the non-exposed area has a weak bonding force with the substrate, and the copper seed layer is easily etched and removed.
- the ultra-fine line width and line spacing processing effect of the fine circuit is achieved, and the problems of side wall corrosion and circuit shedding of the fine circuit are improved.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
一种基于半加成工艺的精细线路板及其制备方法、表面处理方法和应用；涉及芯片封装技术领域；包括以下步骤：1)将基板的表面进行亲水改性处理，形成羟基化的表面，得到亲水基板；2)在所述亲水基板上覆压光阻干膜，曝光显影，形成精细线路图案，得到含图案的基板；3)将所述含图案的基板通过巯基硅烷进行巯基化处理后，去除光阻干膜，得到精细线路区域表面改性的基板。本发明将基板的表面进行亲水改性处理，暴露出羟基，然后在对应的精细线路所需的区域中选择性沉积巯基硅烷，从而使基板覆有巯基；利用巯基与金属离子之间的强螯合作用，可有效吸附金属离子，还原后形成与基板材料具有强界面结合力的种子层，从而大幅提升种子层与基板的结合力。
Description
本发明属于芯片封装技术领域，具体涉及一种基于半加成工艺的精细线路板及其制备方法、表面处理方法和应用。
半加成法工艺是在生产精细线路时用于高密度IC载板的成熟生产方法。该方法的主要步骤为，首先在基底介质材料上施加铜种子层，接着图案化电镀精细线路，最后去除不必要的铜与种子层。目前，半加成工艺制备的精细线路已广泛应用于线宽线距小于50微米的高密度互连电路板。
半加成法工艺生产的电路板具有超细的线宽和线距以及金属线路粗糙度低等优势。但是，化学沉铜制作种子层时，依旧面临着种子层与基板附着力差及其衍生的侧壁腐蚀等问题。如果能图案化局部提高精细线路下方的种子层粘附力，则能有效减少侧壁腐蚀，线路腐蚀脱落的难题，有效提高系统的良率和生产效率。
发明内容
为了克服现有技术的不足，本发明的目的之一在于提供一种精细线路基板的表面处理方法，可有效提高基板的吸附金属离子性能，提高基板与精细线路的粘附力。
本发明的目的之二在于提供一种精细线路基板的表面处理方法的应用。
本发明的目的之三在于提供一种基于半加成工艺的精细线路板的制备方法，提高精细线路与基板之间的界面结合力，精细线路的厚度可控，改善精细线路板 的侧壁腐蚀和线路脱落的问题。
本发明的目的之四在于提供一种基于半加成工艺的精细线路板，线宽线距小，精细线路不易脱落。
本发明的目的之一采用如下技术方案实现：
一种精细线路基板的表面处理方法，包括以下步骤：
1)将基板的表面进行亲水改性处理，形成羟基化的表面，得到亲水基板；
2)在所述亲水基板上覆压光阻干膜，曝光显影，形成精细线路图案，得到含图案的基板；
3)将所述含图案的基板通过巯基硅烷进行巯基化处理后，去除光阻干膜，得到精细线路区域表面改性的基板。
进一步地，步骤1)中，所述亲水改性处理的方法为等离子体处理、紫外线处理和臭氧处理中的至少一种。
进一步地，所述基板的材料为玻璃、陶瓷、硅片、环氧树脂、BT树脂、PI树脂中的任一种或两种以上的组合。
进一步地，步骤3)中，巯基化处理的操作为：将气相的巯基硅烷选择性沉积在基板的精细线路图案区域。
进一步地，所述巯基硅烷为3-巯基丙基三甲氧基硅烷、3-巯丙基三乙氧基硅烷和巯丙基甲基二甲氧基硅烷中的至少一种。
本发明的目的之二采用如下技术方案实现：
一种精细线路基板的表面处理方法的应用，所述的精细线路基板的表面处理方法在生产精细线路板中的应用。
本发明的目的之三采用如下技术方案实现：
一种基于半加成工艺的精细线路板的制备方法，包括以下步骤：
S1，采用所述的精细线路基板的表面处理方法对基板进行表面处理，得到表面处理的基板；
S2，将所述表面处理的基板表面进行铜的化学沉积，形成种子层；
S3，向步骤S2中的种子层进行第二次的覆压光阻干膜，曝光显影，电镀形成精细线路；
S4，将步骤S3中含精细线路的基板去除光阻干膜后，刻蚀去除种子层，得到精细线路板。
进一步地，步骤S3中，所述精细线路的金属材料为铜、金和银中的任一种或两种以上的组合物。
进一步地，步骤S4中，所述精细线路板中精细线路的线宽为1-200μm，线距为1-200μm。
本发明的目的之四采用如下技术方案实现：
一种基于半加成工艺的精细线路板，采用所述的基于半加成工艺的精细线路板的制备方法制得。
相比现有技术，本发明的有益效果在于：
本发明的一种精细线路基板的表面处理方法，先将基板的表面进行亲水改性处理，暴露出羟基，然后在对应的精细线路所需的区域中选择性沉积巯基硅烷，从而使基板覆有巯基；利用巯基与金属离子之间的强螯合作用，可有效吸附金属离子，还原后形成与基板材料具有强界面结合力的种子层，从而大幅提升种子层与基板的结合力。
本发明的一种基于半加成工艺的精细线路板的制备方法，利用上述表面处理 方法使基板选择性覆有巯基后，化学沉积铜的种子层，使精细线路对应的曝光区域在巯基与铜离子的强螯合作用下，具有极高的界面结合力；同时非曝光区域的铜种子层与基板的结合力弱，易于刻蚀去除铜种子层，利用半加成工艺在种子层上进一步电镀形成精细线路后，即实现精细线路的超细线宽和线距加工的效果，同时改善精细线路的侧壁腐蚀和线路脱落的问题。
本发明的一种基于半加成工艺的精细线路板，其线宽和线距小，厚度可控，金属线路粗糙度低，且精细线路不易脱落。
图1是本发明的一种精细线路基板的表面处理方法的工艺流程图。
图2是本发明的一种基于半加成工艺的精细线路板的制备方法中化学沉积种子层的结构示意图。
图3是本发明的一种基于半加成工艺的精细线路板的制备方法的工艺流程图。
图4是本发明的实施例4制得的精细线路板的实物图。
其中，1、基板；2、种子层；3、光阻干膜；4、精细线路。
下面，结合具体实施方式，对本发明做进一步描述，需要说明的是，在不相冲突的前提下，以下描述的各实施例之间或各技术特征之间可以任意组合形成新的实施例。
实施例1
一种精细线路基板的表面处理方法，参照图1，包括以下步骤：
1)将基板的表面进行亲水改性处理，形成羟基化的表面，得到亲水基板；所述基板的材料为环氧树脂；所述亲水改性处理的方法包括但不限于等离子体处理、紫外线处理和臭氧处理，优选地，本实施例所述亲水改性处理的方法为等离子体处理，处理功率为10-100W，处理时间为10s-10min。
2)在所述亲水基板上覆压光阻干膜，曝光显影，形成精细线路图案，得到含图案的基板；
3)将所述含图案的基板通过巯基硅烷进行巯基化处理后，去除光阻干膜，得到精细线路区域表面巯基化改性的基板。
进一步地，所述巯基硅烷为3-巯基丙基三甲氧基硅烷；本实施例的巯基化处理的具体操作为：将待处理的基板放入真空腔体中，腔体的体积为1-100L；然后在腔体内部滴入1-100ml的3-巯基丙基三甲氧基硅烷液体，之后抽真空，保持真空度小于0.1个大气压即可；真空静置30分钟，即可完成巯基化表面改性。
实施例2
一种精细线路基板的表面处理方法，参照图1，包括以下步骤：
1)将基板的表面进行亲水改性处理，形成羟基化的表面，得到亲水基板；所述基板的材料为BT树脂；所述亲水改性处理的方法为紫外线处理。
2)在所述亲水基板上覆压光阻干膜，曝光显影，形成精细线路图案，得到含图案的基板；
3)将所述含图案的基板通过巯基硅烷进行巯基化处理后，去除光阻干膜，得到精细线路区域表面巯基化改性的基板。
进一步地，巯基化处理的操作为：将气相的巯基硅烷选择性沉积在基板的精细线路图案区域；所述巯基硅烷为3-巯丙基三乙氧基硅烷。
实施例3
一种精细线路基板的表面处理方法，参照图1，包括以下步骤：
1)将基板的表面进行亲水改性处理，形成羟基化的表面，得到亲水基板；所述基板的材料为PI树脂；所述亲水改性处理的方法为臭氧处理。
2)在所述亲水基板上覆压光阻干膜，曝光显影，形成精细线路图案，得到含图案的基板；
3)将所述含图案的基板通过巯基硅烷进行巯基化处理后，去除光阻干膜，得到精细线路区域表面巯基化改性的基板。
进一步地，巯基化处理的操作为：将气相的巯基硅烷选择性沉积在基板的精细线路图案区域；所述巯基硅烷为巯丙基甲基二甲氧基硅烷。
实施例4
一种基于半加成工艺的精细线路板的制备方法，参照图2-3，包括以下步骤：
S1，采用实施例1所述的精细线路基板的表面处理方法对基板1进行表面处理，然后将所述表面处理的基板1表面进行铜的化学沉积，形成种子层2；
S2，向步骤S1中的种子层2进行第二次的覆压光阻干膜3，曝光显影，确定精细线路的区域；
S3，将步骤S2得到的基板进行电镀，电镀的金属为铜，形成精细线路4；
S4，将步骤S3得到的含精细线路的坯板进行去除光阻干膜3处理，暴露出种子层2；
S5，将步骤S4得到的坯板刻蚀去除暴露的种子层2，得到精细线路板；所述精细线路板中精细线路的线宽为1-10μm，线距为1-50μm。
参照图4，本实施例的精细线路板的制备方法可形成线宽和线距均在10μm 以内的精细线路，且高密度的线路的结构完整，无明显的侧壁腐蚀和线路脱落脱落问题。
实施例5
一种基于半加成工艺的精细线路板的制备方法，参照图2-3，包括以下步骤：
S1，采用实施例2所述的精细线路基板的表面处理方法对基板1进行表面处理，然后将所述表面处理的基板1表面进行铜的化学沉积，形成种子层2；
S2，向步骤S1中的种子层2进行第二次的覆压光阻干膜3，曝光显影，确定精细线路的区域；
S3，将步骤S2得到的基板进行电镀，电镀的金属为金，形成精细线路4；
S4，将步骤S3得到的含精细线路的坯板进行去除光阻干膜3处理，暴露出种子层2；
S5，将步骤S4得到的坯板刻蚀去除暴露的种子层2，得到精细线路板；所述精细线路板中精细线路的线宽为10-30μm，线距为10-100μm。
实施例6
一种基于半加成工艺的精细线路板的制备方法，参照图2-3，包括以下步骤：
S1，采用实施例3所述的精细线路基板的表面处理方法对基板1进行表面处理，然后将所述表面处理的基板1表面进行铜的化学沉积，形成种子层2；
S2，向步骤S1中的种子层2进行第二次的覆压光阻干膜3，曝光显影，确定精细线路的区域；
S3，将步骤S2得到的基板进行电镀，电镀的金属为银，形成精细线路4；
S4，将步骤S3得到的含精细线路的坯板进行去除光阻干膜3处理，暴露出种子层2；
S5，将步骤S4得到的坯板刻蚀去除暴露的种子层2，得到精细线路板；所述精细线路板中精细线路的线宽为100-200μm，线距为50-200μm。
本发明的一种基于半加成工艺的精细线路板的制备方法，利用表面处理方法使基板选择性覆有巯基后，化学沉积铜的种子层，使精细线路对应的曝光区域在巯基与铜离子的强螯合作用下，具有极高的界面结合力；同时非曝光区域的铜种子层与基板的结合力弱，易于刻蚀去除铜种子层，利用半加成工艺在种子层上进一步电镀形成精细线路后，即实现精细线路的超细线宽和线距加工的效果，同时改善精细线路的侧壁腐蚀和线路脱落的问题。
上述实施方式仅为本发明的优选实施方式，不能以此来限定本发明保护的范围，本领域的技术人员在本发明的基础上所做的任何非实质性的变化及替换均属于本发明所要求保护的范围。
Claims (10)
- 一种精细线路基板的表面处理方法，其特征在于，包括以下步骤：1)将基板的表面进行亲水改性处理，形成羟基化的表面，得到亲水基板；2)在所述亲水基板上覆压光阻干膜，曝光显影，形成精细线路图案，得到含图案的基板；3)将所述含图案的基板通过巯基硅烷进行巯基化处理后，去除光阻干膜，得到精细线路区域表面改性的基板。
- 如权利要求1所述的精细线路基板的表面处理方法，其特征在于：步骤1)中，所述亲水改性处理的方法为等离子体处理、紫外线处理和臭氧处理中的至少一种。
- 如权利要求1所述的精细线路基板的表面处理方法，其特征在于：所述基板的材料为玻璃、陶瓷、硅片、环氧树脂、BT树脂、PI树脂中的任一种或两种以上的组合。
- 如权利要求1所述的精细线路基板的表面处理方法，其特征在于：步骤3)中，巯基化处理的操作为：将气相的巯基硅烷选择性沉积在基板的精细线路图案区域。
- 如权利要求1或4所述的精细线路基板的表面处理方法，其特征在于：所述巯基硅烷为3-巯基丙基三甲氧基硅烷、3-巯丙基三乙氧基硅烷和巯丙基甲基二甲氧基硅烷中的至少一种。
- 一种精细线路基板的表面处理方法的应用，其特征在于，权利要求1-5任一项所述的精细线路基板的表面处理方法在生产精细线路板中的应用。
- 一种基于半加成工艺的精细线路板的制备方法，其特征在于，包括以下步骤：S1，采用权利要求1-5任一项所述的精细线路基板的表面处理方法对基板进行表面处理，得到表面处理的基板；S2，将所述表面处理的基板表面进行铜的化学沉积，形成种子层；S3，向步骤S2中的种子层进行第二次的覆压光阻干膜，曝光显影，电镀形成精细线路；S4，将步骤S3中含精细线路的基板去除光阻干膜后，刻蚀去除种子层，得到精细线路板。
- 如权利要求7所述的基于半加成工艺的精细线路板的制备方法，其特征在于：步骤S3中，所述精细线路的金属材料为铜、金和银中的任一种或两种以上的组合物。
- 如权利要求7所述的基于半加成工艺的精细线路板的制备方法，其特征在于：步骤S4中，所述精细线路板中精细线路的线宽为1-200μm，线距为1-200μm。
- 一种基于半加成工艺的精细线路板，其特征在于：采用权利要求7-9任一项所述的基于半加成工艺的精细线路板的制备方法制得。
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| CN108697002A (zh) * | 2018-04-24 | 2018-10-23 | 深圳市斯普莱特激光科技有限公司 | 一种激光加工式高精度电路板制作工艺 |
| CN111200912A (zh) * | 2020-03-02 | 2020-05-26 | 厦门弘信电子科技集团股份有限公司 | 一种改善精度的精细线路制作方法 |
| CN113873771A (zh) * | 2021-10-25 | 2021-12-31 | 恒赫鼎富(苏州)电子有限公司 | 一种适用于超精细fpc线路的制作工艺 |
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| US20160095215A1 (en) * | 2014-09-25 | 2016-03-31 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
| CN108337812A (zh) * | 2018-03-27 | 2018-07-27 | 北京大学东莞光电研究院 | 一种在基板上制备金属化线路的方法 |
| CN108697002A (zh) * | 2018-04-24 | 2018-10-23 | 深圳市斯普莱特激光科技有限公司 | 一种激光加工式高精度电路板制作工艺 |
| CN111200912A (zh) * | 2020-03-02 | 2020-05-26 | 厦门弘信电子科技集团股份有限公司 | 一种改善精度的精细线路制作方法 |
| CN113873771A (zh) * | 2021-10-25 | 2021-12-31 | 恒赫鼎富(苏州)电子有限公司 | 一种适用于超精细fpc线路的制作工艺 |
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