WO2024087334A1 - 中介层结构及其制作方法 - Google Patents

中介层结构及其制作方法 Download PDF

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WO2024087334A1
WO2024087334A1 PCT/CN2022/137498 CN2022137498W WO2024087334A1 WO 2024087334 A1 WO2024087334 A1 WO 2024087334A1 CN 2022137498 W CN2022137498 W CN 2022137498W WO 2024087334 A1 WO2024087334 A1 WO 2024087334A1
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substrate
opening
dielectric layer
layer
bonding structure
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PCT/CN2022/137498
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English (en)
French (fr)
Inventor
叶国梁
胡胜
占琼
周俊
孙鹏
杨道虹
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武汉新芯集成电路制造有限公司
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Publication of WO2024087334A1 publication Critical patent/WO2024087334A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure

Definitions

  • the present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to an intermediate layer structure and a manufacturing method thereof.
  • Packaging technology came into being with the invention of integrated circuits. Its main functions are to complete power distribution, signal distribution, heat dissipation and protection. With the development of chip technology, packaging technology has been continuously innovated, the packaging interconnection density has been continuously improved, the packaging thickness has been continuously reduced, and the three-dimensional packaging and system packaging methods have been continuously evolved. With the diversification of integrated circuit applications, emerging fields such as smart phones, the Internet of Things, automotive electronics, high-performance computing, 5G, and artificial intelligence have put forward higher requirements for advanced packaging. Packaging technology has developed rapidly and innovative technologies have continued to emerge. In order to solve the problem of insufficient wiring density of conventional interposers, silicon interposers (Interposers) with through-silicon vias (TSVs) and high-density metal wiring have come into being.
  • Interposers silicon interposers
  • TSVs through-silicon vias
  • the existing silicon interposer has a redistribution metal layer (RDL) formed on only one side.
  • the formation method is to form a blind hole on the front side of the substrate and fill it with conductive material to form TSV, and then form a redistribution metal layer on the front side to electrically lead out the TSV.
  • the TSV does not completely penetrate the substrate, and it is necessary to subsequently thin the back side to expose the bottom of the TSV and then connect it to the IC substrate through a metal solder ball (bump). It is used together with the IC substrate to improve the strength.
  • the number of redistribution metal layers cannot meet the design requirements and high-density interconnection cannot be achieved.
  • the silicon thickness of the silicon interposer after thinning is thin due to the TSV depth limitation. At high temperatures, the silicon thermal expansion coefficient (CTE) is more sensitive and prone to deformation and even fragmentation abnormalities.
  • CTE silicon thermal expansion coefficient
  • the purpose of the present invention is to provide an interposer structure and a method for manufacturing the same, in which a redistributed metal layer is formed on both sides of the substrate thickness direction for wiring, so as to meet the needs of high-density interconnection.
  • the first opening and the second opening are formed from both sides of the substrate thickness direction and connected to form a TSV hole, so that a thicker interposer can be manufactured; the limitation of the aspect ratio process limit in the process of electroplating the filling metal layer in the TSV hole is overcome, the deformation effect of the interposer at high temperature is reduced, and even the use of the integrated circuit substrate alone can be omitted, saving cost and power consumption.
  • the present invention provides a method for manufacturing an interposer structure, comprising:
  • a substrate is provided, wherein the substrate has a first surface and a second surface opposite to each other, a first opening is provided on the first surface, the first opening extends from the first surface to the substrate, and a first conductive layer is filled in the first opening; a first dielectric layer is formed on the first surface of the substrate, a first redistribution metal layer is formed in the first dielectric layer, and the first redistribution metal layer is electrically connected to the first conductive layer;
  • first bonding structure on a side of the second dielectric layer away from the substrate, wherein the first bonding structure is electrically connected to the second redistribution metal layer;
  • the first bonding structure is bonded to a second carrier, and after removing the first carrier, a second bonding structure is formed on a side of the first dielectric layer away from the substrate, the second bonding structure is electrically connected to the first redistribution metal layer, and the second carrier is removed.
  • a minimum cross-sectional width of the first opening is ⁇ 10 ⁇ m, and a depth of the first opening is ⁇ 100 ⁇ m.
  • the substrate is thinned from the second surface of the substrate, and the thickness of the substrate after thinning is ⁇ 150 ⁇ m.
  • a minimum cross-sectional width of the second opening is ⁇ 5 ⁇ m, and a depth of the second opening is ⁇ 50 ⁇ m.
  • first bonding structure and/or the second bonding structure is a metal solder ball and/or a hybrid bonding structure.
  • the pitch of the second bonding structure is smaller than the pitch of the first bonding structure
  • the second bonding structure is used for bonding chips
  • the first bonding structure is used for bonding printed circuit boards.
  • the substrate is a silicon substrate.
  • the present invention also provides an intermediate layer structure, comprising:
  • a substrate having a first surface and a second surface opposite to each other;
  • first opening extending from the first surface into the substrate, the first opening being filled with a first conductive layer
  • first dielectric layer located on a first surface of the substrate, a first redistribution metal layer being formed in the first dielectric layer, and the first redistribution metal layer being electrically connected to the first conductive layer;
  • the second opening extending from the second surface into the substrate and communicating with the first opening, the second opening being filled with a second conductive layer, the second conductive layer being electrically connected to the first conductive layer;
  • the second dielectric layer being located on a second surface of the substrate, a second redistribution metal layer being formed in the second dielectric layer, and the second redistribution metal layer being electrically connected to the second conductive layer;
  • a first bonding structure and a second bonding structure wherein the first bonding structure is located on a side of the second dielectric layer away from the substrate and electrically connected to the second redistribution metal layer, and the second bonding structure is located on a side of the first dielectric layer away from the substrate and electrically connected to the first redistribution metal layer.
  • the pitch of the second bonding structure is smaller than the pitch of the first bonding structure
  • the second bonding structure is used for bonding chips
  • the first bonding structure is used for bonding printed circuit boards.
  • the thickness of the substrate is ⁇ 150 ⁇ m.
  • the present invention has the following beneficial effects:
  • the present invention provides an interposer structure and a manufacturing method thereof, comprising: providing a substrate; forming a first opening, filling a first conductive layer in the first opening; forming a first dielectric layer on the first surface of the substrate, forming a first redistributed metal layer in the first dielectric layer, and the first redistributed metal layer is electrically connected to the first conductive layer; forming a second opening, filling a second conductive layer in the second opening, and the second conductive layer is electrically connected to the first conductive layer; forming a second dielectric layer on the second surface of the substrate, forming a second redistributed metal layer in the second dielectric layer, and the second redistributed metal layer is electrically connected to the second conductive layer.
  • Redistributed metal layers are formed on both sides of the thickness direction of the substrate for wiring, which increases the number of RDL layers and meets the requirements of high-density interconnection.
  • the first opening and the second opening are respectively formed by etching from both sides of the thickness direction of the substrate, and the first opening and the second opening are connected to form a TSV hole.
  • the depth of the TSV hole is doubled, and a thicker interposer can be manufactured; the limitation of the aspect ratio process limit in the process of electroplating the filling metal layer in the TSV hole is overcome, and the thickness of the interposer is increased.
  • the increased thickness of the interposer makes it less likely to deform, which reduces the impact of deformation of the interposer at high temperatures. It can even be used alone without the integrated circuit substrate, saving the cost and power consumption of the integrated circuit substrate.
  • FIG. 1 is a schematic flow chart of a method for manufacturing an interposer structure according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a method for manufacturing an interposer structure according to an embodiment of the present invention after forming a first redistribution metal layer;
  • FIG. 3 is a schematic diagram of a method for manufacturing an interposer structure according to an embodiment of the present invention after a first dielectric layer is bonded to a first carrier;
  • FIG. 4 is a schematic diagram of a method for manufacturing an interposer structure according to an embodiment of the present invention after forming a second redistribution metal layer;
  • FIG. 5 is a schematic diagram of a method for manufacturing an interposer structure according to an embodiment of the present invention after a first bonding structure is formed;
  • FIG. 6 is a schematic diagram of a method for manufacturing an interposer structure according to an embodiment of the present invention after the second dielectric layer is bonded to the second carrier;
  • FIG. 7 is a schematic diagram of a method for manufacturing an interposer structure according to an embodiment of the present invention after removing the first carrier board;
  • FIG. 8 is a schematic diagram of an interposer structure and a chip electrically connected according to an embodiment of the present invention.
  • the thickness of the current silicon-made interposer is relatively thin, and it needs to be used together with an IC substrate to improve strength.
  • the thin interposer is prone to deformation at high temperatures.
  • only forming an RDL (redistributed metal) layer on the front of the interposer still cannot meet the needs of high-density interconnection.
  • the interposer is made of silicon, which has a high coefficient of thermal expansion (CTE). Silicon is more sensitive and prone to deformation at high temperatures. The thinner the silicon thickness, the more susceptible it is to deformation and abnormalities such as cracks.
  • the current TSV structure manufacturing process limits the thickness of the interposer.
  • the TSV structure in the interposer is to form a TSV hole on the silicon material through reactive ion etching technology, and then make an insulating layer on the side wall of the TSV hole, and fill the metal layer in the TSV hole through electroplating to complete the production of the TSV structure.
  • TSV trench-semiconductor
  • some process steps can only complete the processing of TSV with an aspect ratio of less than 10:1, such as depositing an insulating layer, electroplating and filling a metal layer. If a TSV structure with an aspect ratio greater than 10:1 is produced, it is currently difficult to achieve from a process point of view. Therefore, the depth of TSV greatly limits the thickness of the interposer made of silicon.
  • an embodiment of the present invention provides a method for manufacturing an interposer structure.
  • the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
  • some embodiments of the present application may use spatially relative terms such as “above”, “below”, “top”, “below”, etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments.
  • the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being “below” or “below” other elements or components will subsequently be positioned as being “above” or “above” other elements or components.
  • the terms “first”, “second”, etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.
  • An embodiment of the present invention provides a method for manufacturing an interposer structure, as shown in FIG1 , comprising:
  • Step S1 providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other, a first opening is formed on the first surface, the first opening extends from the first surface into the substrate, and a first conductive layer is filled in the first opening;
  • Step S2 forming a first dielectric layer on the first surface of the substrate, forming a first redistribution metal layer in the first dielectric layer, and the first redistribution metal layer is electrically connected to the first conductive layer;
  • Step S3 bonding the first dielectric layer to a first carrier on a side away from the substrate, opening a second opening on the second surface of the substrate, the second opening extending from the second surface into the substrate and communicating with the first opening, the second opening being filled with a second conductive layer, the second conductive layer being electrically connected to the first conductive layer;
  • Step S4 forming a second dielectric layer on the second surface of the substrate, forming a second redistribution metal layer in the second dielectric layer, and the second redistribution metal layer is electrically connected to the second conductive layer;
  • Step S5 forming a first bonding structure on a side of the second dielectric layer away from the substrate, wherein the first bonding structure is electrically connected to the second redistribution metal layer;
  • Step S6 bonding the first bonding structure to a second carrier, removing the first carrier to form a second bonding structure on a side of the first dielectric layer away from the substrate, the second bonding structure being electrically connected to the first redistributed metal layer, and removing the second carrier.
  • a substrate 10 is provided, and the substrate 10 has a first surface f1 and a second surface f2 opposite to each other.
  • the substrate 10 may be a silicon substrate, a germanium substrate, or a silicon germanium substrate.
  • the substrate 10 may also be made of other materials, using a silicon substrate as the substrate 10 may reduce stress because the mismatch between the coefficient of thermal expansion (CTE) between the silicon substrate and the silicon of the chip to be connected is lower than that of a substrate made of other materials.
  • the substrate 10 may be other suitable materials such as organic or inorganic materials, such as III-V group material compound semiconductors such as silicon carbide, gallium arsenide, and indium arsenide.
  • the substrate 10 may include but is not limited to a thickness of about several hundred microns, for example, in the range of 500 ⁇ m-1200 ⁇ m.
  • a first opening V 1 is formed, and the first opening V 1 extends from the first surface f 1 to the substrate 10, and the first conductive layer 21 is filled in the first opening V 1.
  • the aspect ratio of the first opening V 1 may be ⁇ 10:1 or ⁇ 10:1, and preferably, the aspect ratio of the first opening V 1 is ⁇ 10:1; on a cross section perpendicular to the first surface f 1 , the minimum cross-sectional width of the first opening V 1 is ⁇ 10 ⁇ m, and the depth of the first opening V 1 is ⁇ 100 ⁇ m.
  • the first opening V 1 may be formed by reactive ion etching; the first opening V 1 may also be formed by etching using other methods, such as plasma etching, ion beam spraying, X-ray and electron beam irradiation.
  • Several first openings V 1 may be formed in the substrate 10 along a direction parallel to the first surface f 1.
  • the cross-sectional figure of the first opening V 1 may be circular or polygonal such as a quadrilateral or a hexagon.
  • the first conductive layer 21 is made of a conductive material, which may include but is not limited to copper, nickel, aluminum, tungsten, titanium and a combination thereof; the material of the first conductive layer 21 is copper, and the first conductive layer 21 may be formed by an electroplating process.
  • a barrier layer may also be formed between the sidewall of the first opening V1 and the first conductive layer 21, and the material of the barrier layer may include but is not limited to at least one of TaN, Ta, TiN, Ti and CoW.
  • An insulating layer of a certain thickness may be provided between the peripheral sidewall of the first opening V1 and the first conductive layer 21 to insulate the substrate 10 from the first conductive layer 21. In the example with a barrier layer, the insulating layer is provided between the peripheral sidewall of the first opening V1 and the barrier layer.
  • a first dielectric layer 40 is formed on the first surface f1 of the substrate 10, and a first redistribution metal layer 41 is formed in the first dielectric layer 40, and the first redistribution metal layer 41 is electrically connected to the first conductive layer 21.
  • the first dielectric layer 40 may be an organic or inorganic dielectric material, and may include but is not limited to an oxide dielectric layer, such as silicon nitride, etc.
  • the first redistribution metal layer 41 is made of a conductive material, and may include but is not limited to copper, nickel, aluminum, tungsten, titanium, and combinations thereof.
  • the substrate 10 and the first dielectric layer 40 are turned upside down by 180° so that the second surface f2 of the substrate 10 faces upward.
  • the side of the first dielectric layer 40 away from the substrate 10 is bonded to the first carrier 60. Since the bonding strength of the melt bonding or hybrid bonding is greater than the bonding strength of the temporary bonding, and the subsequent formation of the second opening and the second redistribution metal layer will experience a higher temperature, the first dielectric layer 40 and the first carrier 60 can be melt bonded or hybrid bonded through the first bonding layer 61.
  • the first bonding layer 61 can be a material well known in the art, including but not limited to an oxide layer or a nitride layer and a combination thereof.
  • the side of the substrate 10 away from the first dielectric layer 40 is ground to thin the substrate from the second surface f2 of the substrate.
  • the thickness of the thinned substrate 10 is ⁇ 150 ⁇ m.
  • the specific thinning process is to perform a series of thinning, grinding, and polishing processes on the substrate 10 by physical and chemical methods so that the surface of the substrate 10 reaches the required thickness, flatness, and roughness.
  • a second opening V 2 is formed, and the second opening V 2 extends from the second surface f 2 into the substrate 10 and is connected to the first opening V 1.
  • the second opening V 2 may extend from the thinned second surface into the substrate 10 and be connected to the first opening V 1.
  • the second conductive layer 31 is filled in the second opening V 2 , and the second conductive layer 31 is electrically connected to the first conductive layer 21.
  • the second opening V 2 may be formed by reactive ion etching; the second opening V 2 may also be formed by etching using other methods, such as plasma etching, ion beam spraying, X-ray and electron beam irradiation.
  • the aspect ratio of the second opening V 2 may be ⁇ 10:1 or ⁇ 10:1. Preferably, the aspect ratio of the second opening V 2 is ⁇ 10:1.
  • the minimum cross-sectional width of the second opening V 2 is ⁇ 5 ⁇ m, and the depth of the second opening V 2 is ⁇ 50 ⁇ m.
  • a second dielectric layer 50 is formed on the second surface f2 of the substrate 10, and a second redistributed metal layer 51 is formed in the second dielectric layer 50. The second redistributed metal layer 51 is electrically connected to the second conductive layer 31.
  • the second dielectric layer 50 may be an organic or inorganic dielectric material, and may include but is not limited to an oxide dielectric layer, such as silicon nitride.
  • the second conductive layer 31 is made of a conductive material, and may include but is not limited to copper, nickel, aluminum, tungsten, titanium, and combinations thereof; the material of the second conductive layer 31 is copper, and the second conductive layer 31 may be formed by an electroplating process.
  • the second redistributed metal layer 51 is made of a conductive material, and may include but is not limited to copper, nickel, aluminum, tungsten, titanium, and combinations thereof.
  • the present invention changes the architecture of the existing interposer, forms a redistributed metal (RDL) layer on both opposite sides of the substrate 10 for wiring, increases the number of interposer RDL layers, enhances integration, and meets the needs of high-density interconnection.
  • RDL redistributed metal
  • the first opening V1 and the second opening V2 are formed from the opposite sides of the substrate 10 and connected to form a TSV hole.
  • the aspect ratio is the ratio of the depth of the entire TSV hole to the minimum cross-sectional width in the TSV hole
  • the process limit of the aspect ratio less than 10:1 can be broken through to produce a TSV structure with an aspect ratio greater than 10:1, and a thicker interposer can be produced; the limitation of the aspect ratio process limit in the processes of depositing an insulating layer, electroplating a filling metal layer, etc. in TSV is overcome.
  • the thickness of the interposer increases, and it is not easy to deform. By increasing the thickness of the interposer, the influence of high temperature on deformation is reduced, and even the IC carrier can be omitted for use alone, saving cost and power consumption.
  • the present invention realizes the production of ultra-high aspect ratio TSV structure under existing process conditions, while reducing the working difficulty of high aspect ratio TSV structure. At the same time, it has the advantages of simple process, high reliability and compatibility with semiconductor process, and effectively solves the etching problem of TSV through hole in three-dimensional structure.
  • the devices to be connected on the opposite sides of the substrate 10 are connected to different functional chips (such as CPU, DRAM, etc.) on the same interposer through the second conductive layer 31 and the first conductive layer 21 in the TSV hole of the interposer layer to realize vertical interconnection, reduce the interconnection length, reduce signal delay, and realize low power consumption and high-speed communication between chips.
  • a first bonding structure 52 is formed on the side of the second dielectric layer 50 away from the substrate 10.
  • the first bonding structure 52 is electrically connected to the second redistribution metal layer 31.
  • the first bonding structure 52 may be a metal solder ball and/or a hybrid bonding structure.
  • the first bonding structure 52 is a solder ball and/or a solder block, or a metal microcolumn with a solder ball at the top.
  • the second redistribution metal layer 51 may be a single layer or multiple layers to meet the needs of multiple information input/output.
  • the outermost layer of the second redistribution metal layer 51 is provided with an input/output terminal, and the input/output terminal is provided with the first bonding structure 52.
  • the second adhesive 71 is made of a relatively soft material.
  • the first bonding structure 52 is a metal solder ball
  • the first bonding structure 52 can be wrapped to enhance the bonding strength.
  • the second adhesive 71 is a temporary bonding adhesive; in other examples, the second adhesive 71 is a blue film.
  • the first carrier 60 and/or the first bonding layer 61 are removed by a grinding process.
  • a second bonding structure 53 is formed on a side of the first dielectric layer 40 away from the substrate 10, and the second bonding structure 53 is electrically connected to the first redistribution metal layer 41.
  • the second bonding structure 53 may be a metal solder ball and/or a hybrid bonding structure.
  • the second bonding structure 53 is a solder ball or a solder block, or a metal microcolumn with a solder ball at the top.
  • the spacing of the second bonding structure 53 is smaller than the spacing of the first bonding structure 52, the second bonding structure 53 is used to bond the chip, and the first bonding structure 52 is used to bond the printed circuit board, and there is no need to use an IC carrier.
  • the first chip C1 and the second chip C2 are electrically connected to the interposer through the second bonding structure 53 to realize the architecture of the ultra-thick interposer.
  • the completed interposer structure can be cut and split along the cutting line using the wafer-level packaging process to form a single body.
  • the embodiment of the present invention further provides an interposer structure, as shown in FIG8 , including:
  • a substrate 10 wherein the substrate 10 has a first surface and a second surface opposite to each other;
  • a first opening wherein the first opening extends from the first surface into the substrate 10, and a first conductive layer 21 is filled in the first opening;
  • a first dielectric layer 40 wherein the first dielectric layer 40 is located on the first surface of the substrate 10, wherein a first redistribution metal layer 41 is formed in the first dielectric layer 40, and wherein the first redistribution metal layer 41 is electrically connected to the first conductive layer 21;
  • a second opening wherein the second opening extends from the second surface into the substrate 10 and is connected to the first opening, the second opening is filled with a second conductive layer 31, and the second conductive layer 31 is electrically connected to the first conductive layer 21;
  • a second dielectric layer 50 wherein the second dielectric layer 50 is located on the second surface of the substrate 10, a second redistribution metal layer 51 is formed in the second dielectric layer 50, and the second redistribution metal layer 51 is electrically connected to the second conductive layer 31;
  • a first bonding structure 52 and a second bonding structure 53 wherein the first bonding structure 52 is located on a side of the second dielectric layer 50 away from the substrate 10 and is electrically connected to the second redistribution metal layer 51, and the second bonding structure 53 is located on a side of the first dielectric layer 40 away from the substrate 10 and is electrically connected to the first redistribution metal layer 41.
  • the pitch of the second bonding structure 53 is smaller than the pitch of the first bonding structure 52
  • the second bonding structure 53 is used for bonding chips
  • the first bonding structure 52 is used for bonding printed circuit boards (PCB boards).
  • the first bonding structure 52 and/or the second bonding structure 53 are metal solder balls and/or hybrid bonding structures.
  • the substrate 10 can be a silicon substrate, a germanium substrate, or a silicon germanium substrate.
  • the substrate 10 can be other suitable materials such as organic or inorganic materials, such as III-V group material compound semiconductors such as silicon carbide, gallium arsenide, and indium arsenide; the thickness of the substrate 10 is ⁇ 150 ⁇ m.
  • the present invention provides an interposer structure and a manufacturing method thereof, including: providing a substrate; forming a first opening, filling a first conductive layer in the first opening; forming a first dielectric layer on the first surface of the substrate, forming a first redistributed metal layer in the first dielectric layer, and the first redistributed metal layer is electrically connected to the first conductive layer; forming a second opening, filling a second conductive layer in the second opening, and the second conductive layer is electrically connected to the first conductive layer; forming a second dielectric layer on the second surface of the substrate, forming a second redistributed metal layer in the second dielectric layer, and the second redistributed metal layer is electrically connected to the second conductive layer.
  • Redistributed metal layers are formed on both sides of the thickness direction of the substrate for wiring, which increases the number of RDL layers and meets the requirements of high-density interconnection.
  • the first opening and the second opening are respectively etched from both sides of the thickness direction of the substrate, and the first opening and the second opening are connected to form a TSV hole.
  • the depth of the TSV hole is doubled, and a thicker interposer can be made; the limitation of the aspect ratio process limit in the process of electroplating the filling metal layer in the TSV hole is overcome, and the thickness of the interposer is increased.
  • the increased thickness of the interposer makes it less likely to deform, which reduces the impact of deformation of the interposer at high temperatures.
  • the interposer can even be used alone without the integrated circuit substrate, saving the cost and power consumption of the integrated circuit substrate.
  • each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments.
  • the same or similar parts between the embodiments can be referred to each other.
  • the description is relatively simple, and the relevant parts can be referred to the method part description.

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Abstract

本发明提供一种中介层结构及其制作方法，包括：提供一基板；形成第一开孔，在第一开孔中填充第一导电层；在基板的第一表面形成第一介质层，在第一介质层中形成第一再分布金属层；形成第二开孔，在第二开孔中填充第二导电层；在基板的第二表面形成第二介质层，在第二介质层中形成第二再分布金属层。在基板厚度方向的两侧均形成再分布金属层用于布线，满足高密度互联的需求。第一开孔和第二开孔分别从基板厚度方向的两侧形成且连通构成TSV孔，从而可制作较厚的中介层；克服TSV孔中电镀填充金属层等工艺中深宽比工艺极限的限制，降低了中介层高温下形变影响，甚至可以省去集成电路衬底单独使用，节约了成本与功耗。

Description

中介层结构及其制作方法 技术领域
本发明属于集成电路制造技术领域，具体涉及一种中介层结构及其制作方法。
背景技术
封装技术伴随集成电路发明应运而生，主要功能是完成电源分配、信号分配、散热和保护，伴随着芯片技术的发展，封装技术不断革新，封装互连密度不断提高，封装厚度不断减小，三维封装、系统封装手段不断演进，随着集成电路应用多元化，智能手机、物联网、汽车电子、高性能计算、5G、人工智能等新兴领域对先进封装提出更高要求，封装技术发展迅速，创新技术不断出现，为解决常规中介层布线密度不足的问题，带有硅通孔(TSV)和高密度金属布线的硅中介层(Interposer)应运而生。
现有硅中介层(Interposer)只有一侧形成再分布金属层(RDL)，其形成方法是在基板正面形成盲孔并填充导电材料形成TSV，并在正面形成再分布金属层将TSV电引出，其中，TSV并未完全贯穿基板，需要后续通过背面减薄暴露出TSV底部后通过金属焊球(bump)连接至IC载板(IC substrate)，与IC载板搭配在一起使用以提高强度，一方面，再分布金属层层数不能满足设计需求无法实现高密度互联，另一方面，硅中介层因TSV深度限制导致减薄后的硅厚度较薄，高温下硅热膨胀系数(CTE)较为敏感容易产生形变甚至造成破片异常。
发明内容
本发明的目的在于提供一种中介层结构及其制作方法，在基板厚度方向的两侧均形成再分布金属层用于布线，满足高密度互联的需求。第一开孔和第二开孔分别从基板厚度方向的两侧形成且连通构成TSV孔，从而可制作较厚的中介层；克服TSV孔中电镀填充金属层等工艺中深宽比工艺极限的限制， 降低了中介层高温下形变影响，甚至可以省去集成电路衬底单独使用，节约了成本与功耗。
本发明提供一种中介层结构的制作方法，包括：
提供一基板，所述基板具有相背的第一表面和第二表面，所述第一表面开设第一开孔，所述第一开孔从所述第一表面延伸至所述基板中，所述第一开孔中填充第一导电层；在所述基板第一表面形成第一介质层，所述第一介质层中形成第一再分布金属层，所述第一再分布金属层与所述第一导电层电连接；
将所述第一介质层远离所述基板的一侧与第一载板键合，在所述基板第二表面开设第二开孔，所述第二开孔从所述第二表面延伸至所述基板中与所述第一开孔连通，所述第二开孔中填充第二导电层，所述第二导电层与所述第一导电层电连接；
在所述基板第二表面形成第二介质层，所述第二介质层中形成第二再分布金属层，所述第二再分布金属层与所述第二导电层电连接；
在所述第二介质层远离所述基板的一侧形成第一键合结构，所述第一键合结构与所述第二再分布金属层电连接；
将所述第一键合结构键合至第二载板，去除所述第一载板后在所述第一介质层远离所述基板的一侧形成第二键合结构，所述第二键合结构与所述第一再分布金属层电连接，去除所述第二载板。
进一步的，在垂直于所述第一表面的截面上，所述第一开孔的最小截面宽度≥10μm，所述第一开孔的深度≥100μm。
进一步的，在所述基板第二表面开设所述第二开孔之前从所述基板第二表面减薄所述基板，减薄后的所述基板的厚度≥150μm。
进一步的，在垂直于所述第一表面的截面上，所述第二开孔的最小截面宽度≥5μm，所述第二开孔的深度≥50μm。
进一步的，所述第一键合结构和/或所述第二键合结构为金属焊球和/或混合键合结构。
进一步的，所述第二键合结构的间距小于所述第一键合结构的间距，所 述第二键合结构用于键合芯片，所述第一键合结构用于键合印刷电路板。
进一步的，所述基板为硅基底。
本发明还提供一种中介层结构，包括：
基板，所述基板具有相背的第一表面和第二表面；
第一开孔，所述第一开孔从所述第一表面延伸至所述基板中，所述第一开孔中填充第一导电层；
第一介质层，所述第一介质层位于所述基板的第一表面，所述第一介质层中形成有第一再分布金属层，所述第一再分布金属层与所述第一导电层电连接；
第二开孔，所述第二开孔从所述第二表面延伸至所述基板中且与所述第一开孔连通，所述第二开孔中填充第二导电层，所述第二导电层与所述第一导电层电连接；
第二介质层，所述第二介质层位于所述基板的第二表面，所述第二介质层中形成第二再分布金属层，所述第二再分布金属层与所述第二导电层电连接；
第一键合结构和第二键合结构，所述第一键合结构位于所述第二介质层远离所述基板的一侧且与所述第二再分布金属层电连接，所述第二键合结构位于所述第一介质层远离所述基板的一侧且与所述第一再分布金属层电连接。
进一步的，所述第二键合结构的间距小于所述第一键合结构的间距，所述第二键合结构用于键合芯片，所述第一键合结合用于键合印刷电路板。
进一步的，所述基板的厚度≥150μm。
与现有技术相比，本发明具有如下有益效果：
本发明提供一种中介层结构及其制作方法，包括：提供一基板；形成第一开孔，在第一开孔中填充第一导电层；在基板的第一表面形成第一介质层，在第一介质层中形成第一再分布金属层，第一再分布金属层与第一导电层电连接；形成第二开孔，在第二开孔中填充第二导电层，第二导电层与第一导 电层电连接；在基板的第二表面形成第二介质层，在第二介质层中形成第二再分布金属层，第二再分布金属层与第二导电层电连接。在基板的厚度方向的两侧均形成再分布金属层用于布线，提升了RDL层数，满足高密度互联的需求。第一开孔和第二开孔分别从基板的厚度方向的两侧刻蚀形成，第一开孔和第二开孔连通构成TSV孔，TSV孔的深度翻倍，可制作较厚的中介层；克服TSV孔中电镀填充金属层等工艺中深宽比工艺极限的限制，增加了中介层厚度。中介层厚度增加不易发生形变，降低了中介层高温下形变影响，甚至可以省去集成电路衬底而单独使用，节约了集成电路衬底的成本与功耗。
附图说明
图1为本发明实施例的一种中介层结构的制作方法流程示意图。
图2为本发明实施例的中介层结构的制作方法中形成第一再分布金属层后的示意图；
图3为本发明实施例的中介层结构的制作方法中第一介质层与第一载板键合后的示意图；
图4为本发明实施例的中介层结构的制作方法中形成第二再分布金属层后的示意图；
图5为本发明实施例的中介层结构的制作方法中形成第一键合结构后的示意图；
图6为本发明实施例的中介层结构的制作方法中第二介质层与第二载板键合后的示意图；
图7为本发明实施例的中介层结构的制作方法中移除第一载板后的示意图；
图8为本发明实施例的中介层结构与芯片电连接后的示意图。
其中，附图标记如下：
10-基板；f 1-第一表面；f 2-第二表面；21-第一导电层；31-第二导电层；40-第一介质层；50-第二介质层；41-第一再分布金属层；51-第二再分布金属层；52-第一键合结构；53-第二键合结构；60-第一载板；61-第一键合层；70- 第二载板；71-第二粘合胶；C 1-第一芯片；C 2-第二芯片。
具体实施方式
如背景技术所述，当前硅制作的中介层(Interposer)厚度较薄，需要和IC载板搭配在一起使用以提高强度，中介层较薄在高温下易产生形变。而且仅在中介层(Interposer)正面形成RDL(再分布金属)层，仍然无法满足高密度互联的需求。
具体的，中介层(Interposer)由硅制作而成，硅热膨胀系数(CTE)较高，硅在高温下较为敏感容易产生形变，硅厚度越薄越容易受形变影响造成破裂等异常。当前的TSV结构制作工艺限制了中介层(Interposer)的厚度。中介层中的TSV结构是通过反应离子刻蚀技术在硅材料上形成TSV孔，然后在TSV孔的侧壁制作绝缘层、电镀工艺填充金属层在TSV孔中完成TSV结构的制作。由于工艺的限制，目前一些工艺步骤只能完成深宽比小于10:1的TSV的加工，如沉积绝缘层、电镀填充金属层等。如果制作深宽比大于10:1的TSV结构，那么从工艺上目前就难以实现了，因此TSV的深度极大的限制了硅制作的中介层(Interposer)的厚度。
基于上述研究，本发明实施例提供了一种中介层结构的制作方法。以下结合附图和具体实施例对本发明进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需要说明的是，附图均采用非常简化的形式且使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
为了便于描述，本申请一些实施例可以使用诸如“在…上方”、“在…之下”、“顶部”、“下方”等空间相对术语，以描述如实施例各附图所示的一个元件或部件与另一个(或另一些)元件或部件之间的关系。应当理解的是， 除了附图中描述的方位之外，空间相对术语还旨在包括装置在使用或操作中的不同方位。例如若附图中的装置被翻转，则被描述为在其它元件或部件“下方”或“之下”的元件或部件，随后将被定位为在其它元件或部件“上方”或“之上”。下文中的术语“第一”、“第二”、等用于在类似要素之间进行区分，且未必是用于描述特定次序或时间顺序。要理解，在适当情况下，如此使用的这些术语可替换。
本发明实施例提供了一种中介层结构的制作方法，如图1所示，包括：
步骤S1、提供一基板，所述基板具有相背的第一表面和第二表面，所述第一表面开设第一开孔，所述第一开孔从所述第一表面延伸至所述基板中，所述第一开孔中填充第一导电层；
步骤S2、在所述基板第一表面形成第一介质层，所述第一介质层中形成第一再分布金属层，所述第一再分布金属层与所述第一导电层电连接；
步骤S3、将所述第一介质层远离所述基板的一侧与第一载板键合，在所述基板第二表面开设第二开孔，所述第二开孔从所述第二表面延伸至所述基板中与所述第一开孔连通，所述第二开孔中填充第二导电层，所述第二导电层与所述第一导电层电连接；
步骤S4、在所述基板第二表面形成第二介质层，所述第二介质层中形成第二再分布金属层，所述第二再分布金属层与所述第二导电层电连接；
步骤S5、在所述第二介质层远离所述基板的一侧形成第一键合结构，所述第一键合结构与所述第二再分布金属层电连接；
步骤S6、将所述第一键合结构键合至第二载板，去除所述第一载板后在所述第一介质层远离所述基板的一侧形成第二键合结构，所述第二键合结构与所述第一再分布金属层电连接，去除所述第二载板。
下面结合图2至图8介绍本发明实施例的中介层结构的制作方法的各步骤。
如图2所示，提供一基板10，基板10具有相背的第一表面f 1和第二表面 f 2。基板10可采用硅基底、锗基底、或者硅锗基底，虽然基板10也可由其他材料所构成，但是使用硅基底作为基板10可降低应力，因为硅基底与待连接芯片的硅之间热膨胀系数(CTE)不匹配程度低于由其他材料所构成的基底。在其他实施例中，基板10可以是有机物或无机物等其他合适的材料，例如碳化硅、砷化镓、砷化铟等Ⅲ-Ⅴ族材料化合物半导体。示例性的，基板10可以包括但不限于约几百微米的厚度，例如可以在500μm-1200μm的厚度范围内。
形成第一开孔V 1，第一开孔V 1从第一表面f 1延伸至基板10中，在第一开孔V 1中填充第一导电层21。第一开孔V 1深宽比可以≥10:1或者＜10:1，优选的，第一开孔V 1深宽比＜10:1；在垂直于第一表面f 1的截面上，第一开孔V 1的最小截面宽度≥10μm，第一开孔V 1的深度≥100μm。第一开孔V 1可通过反应离子刻蚀法形成；第一开孔V 1也可采用其他方法刻蚀形成，如等离子体刻蚀、离子束喷射、X射线和电子束照射等方法。基板10中可沿平行于第一表面f 1方向上形成若干个第一开孔V 1。平行于第一表面f 1的截面上，第一开孔V 1的截面图形可以呈圆形或四边形、六边形等多边形。
第一导电层21由导电材料构成，可以包括但不限于铜、镍、铝、钨、钛及其组合；第一导电层21的材质为铜，可通过电镀工艺形成第一导电层21。第一开孔V 1的侧壁和第一导电层21之间还可形成阻挡层，阻挡层的材质可以包括但不限于为TaN、Ta、TiN、Ti和CoW中的至少一种。第一开孔V 1的周圈侧壁与第一导电层21之间可设置有一定厚度的绝缘层，以使基板10与第一导电层21绝缘。在有阻挡层的示例中，绝缘层设置在第一开孔V 1的周圈侧壁与阻挡层之间。
在基板10的第一表面f 1形成第一介质层40，在第一介质层40中形成第一再分布金属层41，第一再分布金属层41与第一导电层21电连接。第一介质层40可为有机或无机介电材料，可以包括但不限于氧化介电层，例如氮化硅等。第一再分布金属层41由导电材料构成，可以包括但不限于铜、镍、铝、钨、钛及其组合等。
如图3所示，将基板10和第一介质层40整体上下翻转180°，使基板10的第二表面f 2朝上。将第一介质层40远离基板10的一侧与第一载板60 键合，由于熔融键合或混合键合键合强度大于临时键合键合强度，且后续形成第二开孔与第二再分布金属层会经历较高的温度，可通过第一键合层61将第一介质层40与第一载板60熔融键合或混合键合，第一键合层61可以为本领域所熟知的材料，包括但不限于氧化层或氮化层及其组合等。在基板第二表面开设第二开孔之前，研磨基板10远离第一介质层40的一侧以从基板第二表面f 2减薄基板，减薄后的基板10的厚度≥150μm。具体的减薄过程是通过物理和化学的方法对基板10进行一系列减薄、研磨、抛光工艺，使基板10表面达到所需要的厚度、平整度以及粗糙度。
如图4所示，形成第二开孔V 2，第二开孔V 2从第二表面f 2延伸至基板10中且与第一开孔V 1连通，具体的，第二开孔V 2可以是从减薄后的第二表面延伸至基板10中且与第一开孔V 1连通，在第二开孔V 2中填充第二导电层31，第二导电层31与第一导电层21电连接。第二开孔V 2可通过反应离子刻蚀法形成；第二开孔V 2也可采用其他方法刻蚀形成，如等离子体刻蚀、离子束喷射、X射线和电子束照射等方法。第二开孔V 2深宽比可以≥10:1或者＜10:1，优选的，第二开孔V 2深宽比＜10:1；在垂直于第一表面f 1的截面上，第二开孔V 2的最小截面宽度≥5μm，第二开孔V 2的深度≥50μm。在基板10的第二表面f 2形成第二介质层50，在第二介质层50中形成第二再分布金属层51，第二再分布金属层51与第二导电层31电连接。上述实施例中示出了，先形成第一开孔V 1后形成第二开孔V 2；在其他示例中，也可先形成第二开孔V 2后形成第一开孔V 1；第一开孔V 1的最小截面宽度可小于、等于或大于第二开孔V 2的最小截面宽度，根据实际需要配置。第二介质层50可为有机或无机介电材料，可以包括但不限于氧化介电层，例如氮化硅等。第二导电层31由导电材料构成，可以包括但不限于铜、镍、铝、钨、钛及其组合；第二导电层31的材质为铜，可通过电镀工艺形成第二导电层31。第二再分布金属层51由导电材料构成，可以包括但不限于铜、镍、铝、钨、钛及其组合等。
本发明改变已有的中介层的架构，在基板10相背两侧均形成再分布金属(RDL)层用于布线，提升了中介层RDL层数，增强集成度，满足高密度互联的需求。在垂直基板10第一表面f 1方向上，第一开孔V 1和第二开孔V 2从基板10相背两侧形成并连通构成TSV孔，由于深宽比是整个TSV孔深度与TSV孔中最小截面宽度的比值，第一开孔V 1、第二开孔V 2深宽比均小于10:1时能够突破深宽比小于10:1的工艺极限从而制作深宽比大于10:1的TSV结构，可制作较厚的中介层；克服TSV中沉积绝缘层、电镀填充金属层等工艺中深宽比工艺极限的限制。中介层厚度增加，不易发生形变，通过增加中介层厚度降低了高温对形变的影响，甚至可以省去IC载板单独使用，节省成本与功耗。
本发明在现有工艺条件下实现了超高深宽比TSV结构的制作，同时降低了高深宽比TSV结构的工作难度。与此同时，具有工艺简单，可靠性高以及兼容半导体工艺的优点，有效解决了三维结构中TSV通孔的刻蚀问题。基板10相背两侧的待连接的器件，通过中介层TSV孔中的第二导电层31、第一导电层21将连到同一中介层上的不同功能芯片(例如CPU、DRAM等)实现垂直互连，减小互联长度，减小信号延迟，实现芯片间的低功耗，高速通讯。
如图5所示，在第二介质层50远离基板10的一侧形成第一键合结构52，第一键合结构52与第二再分布金属层31电连接，第一键合结构52可为金属焊球和/或混合键合结构。示例性的，第一键合结构52为焊球和/或焊块，也可以是顶端为焊球的金属微柱。第二再分布金属层51可以是单层，也可以是复数层，以满足多重信息输入/输出的需要，第二再分布金属层51的最外层设有输入/输出端，输入/输出端设置有第一键合结构52。
如图6所示，将中介层结构的第一键合结构52一侧键合到第二载板70上，可通过第二粘合胶71将第二介质层50与第二载板70临时键合，第二粘合胶71材质较软，第一键合结构52为金属焊球时可将第一键合结构52包裹 以增强键合强度，一实施例中，第二粘合胶71为临时键合胶；其他示例中，第二粘合胶71为蓝膜。
如图6和图7所示，通过研磨工艺去除第一载板60和/或第一键合层61。
如图7和图8所示，在第一介质层40远离基板10的一侧形成第二键合结构53，第二键合结构53与第一再分布金属层41对应电连接。第二键合结构53可为金属焊球和/或混合键合结构。示例性的，第二键合结构53为焊球或焊块，也可以是顶端为焊球的金属微柱。使用时，若干相同或不同的芯片与中介层键合实现电连接。在一示例中，第二键合结构53的间距小于第一键合结构52的间距，第二键合结构53用于键合芯片，第一键合结构52用于键合印刷电路板，可以无需使用IC载板。
示例性的，第一芯片C 1与第二芯片C 2通过第二键合结构53与中介层实现电连接，实现超厚中介层的架构。可将采用晶圆级封装工艺将完成的中介层结构沿切割线切割、裂片，形成单体。
本发明实施例还提供一种中介层结构，如图8包括：
基板10，所述基板10具有相背的第一表面和第二表面；
第一开孔，所述第一开孔从所述第一表面延伸至所述基板10中，在所述第一开孔中填充有第一导电层21；
第一介质层40，所述第一介质层40位于所述基板10第一表面，所述第一介质层40中形成有第一再分布金属层41，所述第一再分布金属层41与所述第一导电层21电连接；
第二开孔，所述第二开孔从所述第二表面延伸至所述基板10中且与所述第一开孔连通，所述第二开孔中填充第二导电层31，所述第二导电层31与所述第一导电层21电连接；
第二介质层50，所述第二介质层50位于所述基板10的所述第二表面，在所述第二介质层50中形成有第二再分布金属层51，所述第二再分布金属层51与所述第二导电层31电连接；
第一键合结构52和第二键合结构53，所述第一键合结构52位于所述第二介质层50远离所述基板10的一侧且与所述第二再分布金属层51电连接， 所述第二键合结构53位于所述第一介质层40远离所述基板10的一侧且与所述第一再分布金属层41电连接。
示例性的，第二键合结构53的间距小于第一键合结构52的间距，第二键合结构53用于键合芯片，第一键合结构52用于键合印刷电路板(PCB板)。
第一键合结构52和/或第二键合结构53为金属焊球和/或混合键合结构。基板10可采用硅基底、锗基底、或者硅锗基底，基板10可以是有机物或无机物等其他合适的材料，例如碳化硅、砷化镓、砷化铟等Ⅲ-Ⅴ族材料化合物半导体；基板10的厚度≥150μm。
综上所述，本发明提供一种中介层结构及其制作方法，包括：提供一基板；形成第一开孔，在第一开孔中填充第一导电层；在基板的第一表面形成第一介质层，在第一介质层中形成第一再分布金属层，第一再分布金属层与第一导电层电连接；形成第二开孔，在第二开孔中填充第二导电层，第二导电层与第一导电层电连接；在基板的第二表面形成第二介质层，在第二介质层中形成第二再分布金属层，第二再分布金属层与第二导电层电连接。在基板的厚度方向的两侧均形成再分布金属层用于布线，提升了RDL层数，满足高密度互联的需求。第一开孔和第二开孔分别从基板的厚度方向的两侧刻蚀形成，第一开孔和第二开孔连通构成TSV孔，TSV孔的深度翻倍，可制作较厚的中介层；克服TSV孔中电镀填充金属层等工艺中深宽比工艺极限的限制，增加了中介层厚度。中介层厚度增加不易发生形变，降低了中介层高温下形变影响，甚至可以省去集成电路衬底而单独使用，节约了集成电路衬底的成本与功耗。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的方法而言，由于与实施例公开的器件相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
上述描述仅是对本发明较佳实施例的描述，并非对本发明权利要求范围 的任何限定，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。

Claims (10)

  1. 一种中介层结构的制作方法，其特征在于，包括：
    提供一基板，所述基板具有相背的第一表面和第二表面，所述第一表面开设第一开孔，所述第一开孔从所述第一表面延伸至所述基板中，所述第一开孔中填充第一导电层；在所述基板第一表面形成第一介质层，所述第一介质层中形成第一再分布金属层，所述第一再分布金属层与所述第一导电层电连接；
    将所述第一介质层远离所述基板的一侧与第一载板键合，在所述基板第二表面开设第二开孔，所述第二开孔从所述第二表面延伸至所述基板中与所述第一开孔连通，所述第二开孔中填充第二导电层，所述第二导电层与所述第一导电层电连接；
    在所述基板第二表面形成第二介质层，所述第二介质层中形成第二再分布金属层，所述第二再分布金属层与所述第二导电层电连接；
    在所述第二介质层远离所述基板的一侧形成第一键合结构，所述第一键合结构与所述第二再分布金属层电连接；
    将所述第一键合结构键合至第二载板，去除所述第一载板后在所述第一介质层远离所述基板的一侧形成第二键合结构，所述第二键合结构与所述第一再分布金属层电连接，去除所述第二载板。
  2. 如权利要求1所述的中介层结构的制作方法，其特征在于，在垂直于所述第一表面的截面上，所述第一开孔的最小截面宽度≥10μm，所述第一开孔的深度≥100μm。
  3. 如权利要求1所述的中介层结构的制作方法，其特征在于，在所述基板第二表面开设所述第二开孔之前从所述基板第二表面减薄所述基板，减薄后的所述基板的厚度≥150μm。
  4. 如权利要求1所述的中介层结构的制作方法，其特征在于，在垂直于所述第一表面的截面上，所述第二开孔的最小截面宽度≥5μm，所述第二开孔的深度≥50μm。
  5. 如权利要求1所述的中介层结构的制作方法，其特征在于，所述第一 键合结构和/或所述第二键合结构为金属焊球和/或混合键合结构。
  6. 如权利要求1所述的中介层结构的制作方法，其特征在于，所述第二键合结构的间距小于所述第一键合结构的间距，所述第二键合结构用于键合芯片，所述第一键合结构用于键合印刷电路板。
  7. 如权利要求1至6任意一项所述的中介层结构的制作方法，其特征在于，所述基板为硅基底。
  8. 一种中介层结构，其特征在于，包括：
    基板，所述基板具有相背的第一表面和第二表面；
    第一开孔，所述第一开孔从所述第一表面延伸至所述基板中，所述第一开孔中填充第一导电层；
    第一介质层，所述第一介质层位于所述基板的第一表面，所述第一介质层中形成有第一再分布金属层，所述第一再分布金属层与所述第一导电层电连接；
    第二开孔，所述第二开孔从所述第二表面延伸至所述基板中且与所述第一开孔连通，所述第二开孔中填充第二导电层，所述第二导电层与所述第一导电层电连接；
    第二介质层，所述第二介质层位于所述基板的第二表面，所述第二介质层中形成第二再分布金属层，所述第二再分布金属层与所述第二导电层电连接；
    第一键合结构和第二键合结构，所述第一键合结构位于所述第二介质层远离所述基板的一侧且与所述第二再分布金属层电连接，所述第二键合结构位于所述第一介质层远离所述基板的一侧且与所述第一再分布金属层电连接。
  9. 如权利要求8所述的中介层结构，其特征在于，所述第二键合结构的间距小于所述第一键合结构的间距，所述第二键合结构用于键合芯片，所述第一键合结合用于键合印刷电路板。
  10. 如权利要求8所述的中介层结构，其特征在于，所述基板的厚度≥150μm。
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CN111341754A (zh) * 2020-02-29 2020-06-26 浙江集迈科微电子有限公司 一种超厚转接板的制作方法

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