WO2024078125A1 - 一种复合沟槽型肖特基二极管器件及其制作方法 - Google Patents

一种复合沟槽型肖特基二极管器件及其制作方法 Download PDF

Info

Publication number
WO2024078125A1
WO2024078125A1 PCT/CN2023/113289 CN2023113289W WO2024078125A1 WO 2024078125 A1 WO2024078125 A1 WO 2024078125A1 CN 2023113289 W CN2023113289 W CN 2023113289W WO 2024078125 A1 WO2024078125 A1 WO 2024078125A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
epitaxial layer
trench
schottky diode
diode device
Prior art date
Application number
PCT/CN2023/113289
Other languages
English (en)
French (fr)
Inventor
张小辛
李秋梅
艾治州
Original Assignee
华润微电子（重庆）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华润微电子（重庆）有限公司 filed Critical 华润微电子（重庆）有限公司
Publication of WO2024078125A1 publication Critical patent/WO2024078125A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the invention belongs to the technical field of semiconductor integrated circuits and relates to a composite trench type Schottky diode device and a manufacturing method thereof.
  • Schottky diodes are semiconductor devices made with noble metals (silver Ag, platinum pt, etc.) as positive electrodes and semiconductors as negative electrodes, and using the potential barrier formed on the contact surface of the noble metal and the semiconductor to have the rectifying property.
  • Trench Schottky diodes are made based on planar Schottky diodes by using the MOS effect of metal-semiconductor-silicon. Trench Schottky diodes have higher withstand voltage, lower reverse leakage, lower forward voltage, wider safe operating range, and lower switching loss than planar Schottky diodes, so they are widely used in solar cells, switching power supplies and other fields.
  • a wafer is composed of multiple grains (chip dies).
  • Figure 1 shows a groove arrangement diagram in a grain, in which multiple grooves 101 extend in the same direction, are parallel to each other and are spaced apart.
  • this design of wafer can only reduce stress concentration in a single direction, and the wafer warping problem cannot be effectively solved, and it will also cause defects such as dislocations.
  • the object of the present invention is to provide a composite trench Schottky diode device and a method for manufacturing the same, so as to solve the problem in the prior art that as the trench spacing becomes smaller and smaller, the problem of wafer warping becomes more and more serious, and it is also easy to cause defects such as dislocations.
  • the present invention provides a composite trench Schottky diode device, comprising:
  • a substrate comprising a front surface and a back surface arranged opposite to each other;
  • An epitaxial layer located on the front side of the substrate
  • a groove structure array is located in the epitaxial layer and extends from the front side of the epitaxial layer to the back side of the epitaxial layer, wherein the groove structure array includes a plurality of groove structure array units arranged in at least two rows and at least two columns, wherein the groove structure array unit includes a plurality of linear groove structures that are parallel to each other and spaced apart, and the linear groove structures in two adjacent groove structure array units extend in directions perpendicular to each other;
  • a Schottky metal layer located on the front side of the epitaxial layer and covering the linear groove structure;
  • a front metal electrode layer located on the Schottky metal layer
  • the back metal electrode layer is located on the back side of the substrate.
  • the composite trench Schottky diode device further includes one or more annular trench structures located in the epitaxial layer and extending from the front side of the epitaxial layer toward the back side of the epitaxial layer, and the annular trench structures are arranged around the periphery of the trench structure array.
  • the annular groove structure is a rounded square ring.
  • the linear trench structure and the annular trench structure both include a conductive material layer and a dielectric layer covering the sidewall and bottom surface of the conductive material layer.
  • the conductive material includes doped polysilicon
  • the dielectric layer includes silicon dioxide
  • a plurality of the linear groove structures have the same length and are arranged at equal intervals.
  • the present invention also provides a method for manufacturing a composite trench Schottky diode device, comprising the following steps:
  • the substrate comprising a front side and a back side arranged opposite to each other;
  • a trench array extending from the front side of the epitaxial layer to the back side of the epitaxial layer is formed in the epitaxial layer.
  • the groove array comprises a plurality of groove array units arranged in at least two rows and at least two columns, wherein the groove array unit comprises a plurality of linear grooves which are parallel to each other and spaced apart, and the linear grooves in two adjacent groove array units extend in directions perpendicular to each other;
  • a back metal electrode layer is formed on the back side of the substrate.
  • the method further comprises the following steps:
  • annular grooves Forming one or more annular grooves in the epitaxial layer, wherein the annular grooves extend from the front side of the epitaxial layer toward the back side of the epitaxial layer, and the annular grooves are arranged around the periphery of the groove array;
  • a dielectric layer and a conductive material layer are sequentially formed in the annular groove to obtain an annular groove structure.
  • the annular groove is in the shape of a rounded square ring.
  • the plurality of linear grooves have the same length and are arranged at equal intervals.
  • the composite trench Schottky diode device of the present invention and its manufacturing method form a trench array in the crystal grain
  • the trench array includes a plurality of trench array units arranged in at least two rows and at least two columns
  • each trench array unit includes a plurality of linear trenches that are parallel to each other and spaced apart, and the extension directions of the number of linear trenches in two adjacent trench array units are perpendicular to each other.
  • one or more annular trenches can be designed around the trench array.
  • the criss-crossed trench array units can offset the stresses in different directions on the wafer; the multiple annular trenches formed at the edge of the chip active area can also reduce wafer warping, and can also improve the problem of concentrated electric field distribution of weak devices; this composite trench device design effectively improves the problem of wafer warping, reduces defects such as device dislocation, and further improves the electric field distribution, which helps to improve device stability.
  • FIG. 1 shows a diagram of the groove arrangement in a die in the prior art.
  • FIG. 2 shows a trench plan layout diagram of the composite trench Schottky diode device of the present invention.
  • FIG. 3 is a schematic diagram showing a cross-sectional structure of a composite trench Schottky diode device of the present invention.
  • FIG. 4 is a process flow chart showing a method for manufacturing a composite trench Schottky diode device according to the present invention.
  • FIG. 5 is a schematic diagram showing a cross-sectional structure of a substrate provided for the method for manufacturing a composite trench Schottky diode device of the present invention.
  • FIG6 shows a method for manufacturing a composite trench Schottky diode device of the present invention, wherein an epitaxial layer is formed on the positive side of the substrate. Schematic diagram of the cross-sectional structure of the obtained structure.
  • FIG. 7 is a schematic cross-sectional view of a structure obtained after a silicon dioxide layer is grown on an epitaxial layer in the method for manufacturing a composite trench Schottky diode device of the present invention.
  • FIG8 is a schematic cross-sectional view of a structure obtained after a planar pattern of a trench is formed in a silicon dioxide layer according to the method for manufacturing a composite trench Schottky diode device of the present invention.
  • FIG9 is a schematic diagram showing a cross-sectional structure of a structure obtained after etching the epitaxial layer using a patterned silicon dioxide layer as a mask to obtain a trench array in the epitaxial layer according to a method for manufacturing a composite trench Schottky diode device of the present invention.
  • FIG. 10 is a schematic diagram showing a cross-sectional structure of a structure obtained after removing silicon dioxide in the method for manufacturing a composite trench Schottky diode device of the present invention.
  • FIG. 11 is a schematic cross-sectional view of a structure obtained after a dielectric layer is formed on the sidewall and bottom of a linear trench in the method for manufacturing a composite trench Schottky diode device of the present invention.
  • FIG. 12 is a schematic diagram showing the cross-sectional structure of the structure obtained after filling highly doped polysilicon material on the dielectric layer and removing excess polysilicon material outside the trench according to the method for manufacturing the composite trench Schottky diode device of the present invention.
  • FIG. 13 is a schematic cross-sectional view of a structure obtained after forming a Schottky metal layer on the front side of the epitaxial layer according to the method for manufacturing a composite trench Schottky diode device of the present invention.
  • FIG. 14 is a schematic cross-sectional view of a structure obtained after a front metal electrode layer is formed on a Schottky metal layer in the method for manufacturing a composite trench Schottky diode device of the present invention.
  • FIG. 15 is a schematic cross-sectional view of a structure obtained after forming a back metal electrode layer on the back side of a substrate in the method for manufacturing a composite trench Schottky diode device of the present invention.
  • Component number description 101 Groove 201 Substrate 202 epitaxial layer 203 Groove Structure Array 204 Schottky metal layer 205 front metal electrode layer 206 back metal electrode layer 207 Linear groove structure 208a Groove structure array unit 208b Groove structure array unit 208c Groove structure array unit 209 conductive material layer 210 Dielectric layer 211 Annular groove structure 212 Linear groove 213 Silicon dioxide layer
  • a composite trench Schottky diode device is provided in the present embodiment, please refer to Figures 2 and 3, wherein Figure 2 shows a trench plan layout diagram of the composite trench Schottky diode device of the present embodiment, and Figure 3 shows a cross-sectional structure schematic diagram of the composite trench Schottky diode device of the present embodiment.
  • the composite trench Schottky diode device includes a substrate 201, an epitaxial layer 202, a trench structure array 203, a Schottky metal layer 204, a front metal electrode layer 205 and a back metal electrode layer 206, wherein the substrate 201 includes a front side and a back side that are relatively arranged; the epitaxial layer 202 includes a front side and a back side that are relatively arranged, and the back side of the epitaxial layer 202 is in contact with the front side of the substrate 201; the trench structure array 203 is located in the epitaxial layer 202 and extends from the front side of the epitaxial layer 202 to the back side of the epitaxial layer 202, the Schottky metal layer 204 is located on the front side of the epitaxial layer 202 and covers the trench structure array 203; the front metal electrode layer is located on the Schottky metal layer; the back metal electrode layer is located on the back side of the substrate 201.
  • the substrate 201 may be a silicon substrate, a germanium silicon substrate, a III-V group element compound substrate or other semiconductor material substrates known to those skilled in the art.
  • the substrate 201 is an N-type silicon substrate
  • the epitaxial layer 202 is an N-type silicon epitaxial layer.
  • the groove structure array 203 includes a plurality of grooves arranged in at least two rows and at least two columns.
  • a groove structure array unit wherein the groove structure array unit includes a plurality of linear groove structures 207 that are parallel to each other and spaced apart, and the number extension directions of the linear groove structures 207 in two adjacent groove structure array units (for example, the groove structure array unit 208a and the groove structure array unit 208b, or the groove structure array unit 208a and the groove structure array unit 208c shown in FIG. 2) are perpendicular to each other.
  • the present invention forms these criss-cross groove structure array units in a single crystal grain, which can offset the stresses in different directions on the wafer, effectively improve the wafer warping problem, and reduce defects such as device dislocation.
  • the lengths of the plurality of linear groove structures 207 are consistent and are arranged at equal intervals, wherein the number of the linear groove structures 207 in each of the groove structure array units can be adjusted as needed.
  • the linear groove structure 207 includes a conductive material layer 209 and a dielectric layer 210 coated on the sidewalls and bottom of the conductive material layer 209, wherein the material of the conductive material layer 209 may include doped polysilicon or other suitable conductive materials, and the material of the dielectric layer 210 may include silicon dioxide or other suitable dielectric materials.
  • the composite trench Schottky diode device further includes one or more annular groove structures 211 located in the epitaxial layer 202 and extending from the front side of the epitaxial layer 202 to the back side of the epitaxial layer 202, and the annular groove structures 211 are arranged around the periphery of the groove structure array 203.
  • the present invention can further reduce wafer warpage by forming the annular groove structures 211 in the grain edge region.
  • the annular groove structure 211 is a rounded square ring, that is, a circular groove is made at the corner of the annular groove.
  • the circular groove can effectively improve the problem of concentrated electric field distribution of the device.
  • the trench structure array includes a plurality of trench structure array units arranged in at least two rows and at least two columns, each trench structure array unit includes a plurality of linear trench structures that are parallel to each other and spaced apart, the number of linear trench structures in two adjacent trench structure array units extending in directions perpendicular to each other, and the criss-crossed trench structure array units can offset the stresses in different directions on the wafer.
  • the composite trench Schottky diode device of the present embodiment may include one or more annular trench structures arranged around the trench structure array, which can further reduce the wafer warpage, and can also improve the problem of concentrated electric field distribution of weak devices.
  • this composite trench design of the composite trench Schottky diode device of the present embodiment can effectively improve the problem of wafer warpage, reduce defects such as device dislocation, and can further improve the electric field distribution, which helps to improve the stability of the device.
  • This embodiment provides a method for manufacturing a composite trench Schottky diode device, which can be used to manufacture the composite trench Schottky diode device described in the first embodiment. Please refer to FIG. 4, which shows a process flow chart of the manufacturing method, including The following steps are included:
  • S1 providing a substrate, wherein the substrate comprises a front side and a back side arranged opposite to each other;
  • S2 forming an epitaxial layer on the front side of the substrate, wherein the epitaxial layer comprises a front side and a back side which are arranged opposite to each other, and the back side of the epitaxial layer contacts the front side of the substrate;
  • the groove array comprises a plurality of groove array units arranged in at least two rows and at least two columns, wherein the groove array unit comprises a plurality of linear grooves parallel to each other and spaced apart, and the linear grooves in two adjacent groove array units extend in directions perpendicular to each other;
  • step S1 providing a substrate 201 , wherein the substrate 201 includes a front side and a back side that are oppositely disposed.
  • the substrate 201 may be a silicon substrate, a germanium silicon substrate, a III-V group element compound substrate, or other semiconductor material substrates known to those skilled in the art.
  • the substrate 201 is an N-type silicon substrate.
  • the step S2 forming an epitaxial layer 202 on the front surface of the substrate 201.
  • the epitaxial layer 202 is an N-type silicon epitaxial layer.
  • step S3 form a groove array extending from the front side of the epitaxial layer 202 toward the back side of the epitaxial layer 202 in the epitaxial layer 202, the groove array includes a plurality of groove array units arranged in at least two rows and at least two columns, the groove array unit includes a plurality of linear grooves 212 parallel to each other and spaced apart, and the number of linear grooves 212 in two adjacent groove array units extends in directions perpendicular to each other.
  • a silicon dioxide layer 213 is first grown on the epitaxial layer 202 by chemical vapor deposition, physical vapor deposition or other suitable methods as a mask layer.
  • a planar pattern of grooves is formed in the silicon dioxide layer 213 by semiconductor patterning processes such as photolithography and etching.
  • the epitaxial layer 202 is etched using the patterned silicon dioxide layer 213 as a mask to obtain the trench array in the epitaxial layer 202 .
  • the silicon dioxide layer 213 is removed by wet etching or other suitable semiconductor processes.
  • the present invention forms these crisscross groove array units in a single crystal grain, which can offset the crystal grains.
  • the stresses in different directions on the wafer can effectively improve the wafer warpage problem and reduce defects such as device dislocation.
  • the lengths of the plurality of linear grooves 212 are consistent and are arranged at equal intervals, wherein the number of linear grooves 212 in each groove array unit can be adjusted as needed.
  • one or more annular grooves are also formed in the epitaxial layer 202, the annular grooves extending from the front side of the epitaxial layer 202 to the back side of the epitaxial layer 202, and the annular grooves are arranged around the periphery of the groove array.
  • the present invention can further reduce wafer warpage by forming annular grooves in the edge region of the grain.
  • the annular groove is in the form of a rounded square ring, that is, a circular groove is made at the corner of the annular groove.
  • the circular groove can effectively improve the problem of concentrated electric field distribution of the device.
  • the step S4 is performed: a dielectric layer 210 and a conductive material layer 209 are sequentially formed in the linear trench 212 to obtain a linear trench structure 207 .
  • the dielectric layer 210 made of silicon dioxide is first formed on the sidewall and bottom of the linear trench 212 by thermal oxidation.
  • highly doped polysilicon material is then filled on the dielectric layer 210 , and chemical mechanical polishing or other suitable planarization processes are used to remove excess polysilicon material outside the trenches, and the remaining polysilicon material in the trenches serves as the conductive material layer 209 .
  • the dielectric layer 210 and the conductive material layer 209 are sequentially formed in the annular groove to obtain an annular groove structure 211 .
  • step S5 forming a Schottky metal layer 204 on the front surface of the epitaxial layer 202 by metal sputtering or other suitable methods, wherein the Schottky metal layer 204 also covers the linear trench structure 207, and annealing is performed to form a Schottky barrier junction.
  • step S6 forming a front metal electrode layer 205 on the Schottky metal layer 204 by chemical vapor deposition, physical vapor deposition or other suitable methods.
  • the front metal electrode layer 205 serves as the anode of the Schottky diode.
  • the material of the front metal electrode layer 205 can be selected from one or more of tungsten (W), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), copper (Cu) and aluminum copper (AlCu), or other suitable metal materials.
  • step S7 forming a back metal electrode layer 206 on the back side of the substrate 201 by chemical vapor deposition, physical vapor deposition or other suitable methods, and the back metal electrode layer 206 serves as the cathode of the Schottky diode.
  • the material of the back metal electrode layer 206 can be selected from one or more of tungsten (W), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), copper (Cu) and aluminum copper (AlCu), or other suitable metal materials.
  • the method for manufacturing the composite trench Schottky diode device of this embodiment can effectively improve the problem of wafer warpage, reduce defects such as device dislocation, and further improve the electric field distribution and device stability without changing the existing process and increasing the manufacturing cost.
  • the composite trench Schottky diode device and its manufacturing method of the present invention form a trench array in the crystal grain
  • the trench array includes a plurality of trench array units arranged in at least two rows and at least two columns, and each trench array unit includes a plurality of linear trenches that are parallel to each other and spaced apart, and the number of linear trenches in two adjacent trench array units extends in directions perpendicular to each other.
  • one or more annular trenches can be designed around the trench array.
  • the criss-crossed trench array units can offset the stresses in different directions on the wafer; the multiple annular trenches formed at the edge of the chip active area can also reduce the wafer warping, and can also improve the problem of concentrated electric field distribution of weak devices; this composite trench device design effectively improves the problem of wafer warping, reduces defects such as device dislocation, and further improves the electric field distribution, which helps to improve the stability of the device. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种复合沟槽型肖特基二极管器件及其制作方法，该器件包括衬底（201）、外延层（202）、沟槽结构阵列（203）、肖特基金属层（204）、正面金属电极层（205）及背面金属电极层（206），其中，外延层（202）位于衬底（201）的正面；沟槽结构阵列（203）位于外延层（202）中并包括多个排列成至少两行及至少两列的沟槽结构阵列单元（208a、208b、208c），每个沟槽结构阵列单元（208a、208b、208c）包括多个相互平行且间隔设置的线型沟槽结构（207），相邻两个沟槽结构阵列单元（208a、208b、208c）中的线型沟槽结构（207）的延伸方向互相垂直；肖特基金属层（204）位于外延层（202）的正面并覆盖线型沟槽结构（207）；正面金属电极层（205）位于肖特基金属层（204）上；背面金属电极层（206）位于衬底（201）的背面。该复合沟槽型肖特基二极管器件的设计可以有效改善晶圆翘曲问题，降低器件位错等缺陷，同时可进一步改善电场分布，有助于提高器件稳定性。

Description

一种复合沟槽型肖特基二极管器件及其制作方法
相关申请的交叉引用
本申请要求于2022年10月11日提交中国专利局、申请号为202211241466.1、发明名称为“一种复合沟槽型肖特基二极管器件及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于半导体集成电路技术领域，涉及一种复合沟槽型肖特基二极管器件及其制作方法。
背景技术
肖特基二极管是以贵金属(银Ag，铂pt等)为正极，半导体为负极，利用贵金属和半导体接触面上形成的势垒具有整流特性而制作的半导体器件，沟槽型肖特基二极管是在平面型肖特基二极管基础上利用了金属-半导体-硅的MOS效应而制作出来的。沟槽型肖特基二极管比平面型肖特基二极管具有更高的耐压，更低的反向漏电，更低的正向电压，更宽的安全工作范围，开关损耗更小等优点，因此广泛运用于太阳能电池、开关电源等多种领域。
沟槽型肖特基二极管器件在工艺制造过程中，进行沟槽刻蚀以及沟槽填充时，晶圆受到不均匀应力，这会产生严重的晶圆翘曲问题，还会导致芯片发生位错等硅缺陷，影响器件性能。因此如何降低芯片翘曲度是沟槽型肖特基二极管芯片设计中考虑的关键因素之一。
现有的沟槽型肖特基二极管主要是通过在芯片中形成单个方向、平行、等距的沟槽来抵御芯片翘曲问题。具体而言，一片晶圆由多个晶粒(芯片die)组成，请参阅图1，显示为一个晶粒中的沟槽排布图，其中，多个沟槽101均往同一方向延伸，相互平行且间隔设置。但是随着沟槽间距的不断缩小，这种设计的晶圆仅能减弱单一方向的应力集中，晶圆翘曲问题并不能有效解决，还会导致位错等缺陷。
因此，如何改进沟槽型肖特基二极管器件的沟槽布局设计，使得器件能够在不改变现有工艺和不增加制作成本的基础上有效改善晶圆翘曲问题，降低器件位错等缺陷，同时进一步改善电场分布，提高器件稳定性，成为本领域技术人员亟待解决的一个重要技术问题。
应该注意，上面对技术背景的介绍只是为了方便对本申请的技术方案进行清楚、完整的说明，并方便本领域技术人员的理解而阐述的。不能仅仅因为这些方案在本申请的背景技术部分进行了阐述而认为上述技术方案为本领域技术人员所公知。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种复合沟槽型肖特基二极管器件及其制作方法，用于解决现有技术中随着沟槽间距尺寸的越来越小，晶圆发生翘曲的问题越来越严重，还容易导致位错等缺陷的问题。
为实现上述目的及其他相关目的，本发明提供一种复合沟槽型肖特基二极管器件，包括：
衬底，包括相对设置的正面与背面；
外延层，位于所述衬底的正面；
沟槽结构阵列，位于所述外延层中并自所述外延层的正面往所述外延层的背面方向延伸，所述沟槽结构阵列包括多个排列成至少两行及至少两列的沟槽结构阵列单元，所述沟槽结构阵列单元包括多个相互平行且间隔设置的线型沟槽结构，相邻两个沟槽结构阵列单元中的线型沟槽结构的数量延伸方向互相垂直；
肖特基金属层，位于所述外延层的正面并覆盖所述线型沟槽结构；
正面金属电极层，位于所述肖特基金属层上；
背面金属电极层，位于所述衬底的背面。
可选地，所述复合沟槽型肖特基二极管器件还包括位于所述外延层中并自所述外延层的正面往所述外延层的背面方向延伸的一个或多个环形沟槽结构，所述环形沟槽结构环设于所述沟槽结构阵列的外围。
可选地，所述环形沟槽结构呈圆角正方形环。
可选地，所述线型沟槽结构及所述环形沟槽结构均包括导电材料层及包覆于所述导电材料层的侧壁与底面的介质层。
可选地，所述导电材料的材质包括掺杂多晶硅，所述介质层的材质包括二氧化硅。
可选地，所述沟槽结构阵列单元中，多个所述线型沟槽结构的长度一致且等间距排列。
本发明还提供一种复合沟槽型肖特基二极管器件的制作方法，包括以下步骤：
提供一衬底，所述衬底包括相对设置的正面与背面；
形成外延层于所述衬底的正面；
形成自所述外延层的正面往所述外延层的背面方向延伸的沟槽阵列于所述外延层中， 所述沟槽阵列包括多个排列成至少两行及至少两列的沟槽阵列单元，所述沟槽阵列单元包括多个相互平行且间隔设置的线型沟槽，相邻两个沟槽阵列单元中的线型沟槽的数量延伸方向互相垂直；
依次形成介质层及导电材料层于所述线型沟槽中以得到线型沟槽结构；
形成肖特基金属层于所述外延层的正面，所述肖特基金属层还覆盖所述线型沟槽结构；
形成正面金属电极层于所述肖特基金属层上；
形成背面金属电极层于所述衬底的背面。
可选地，还包括以下步骤：
形成一个或多个环形沟槽于所述外延层中，所述环形沟槽自所述外延层的正面往所述外延层的背面方向延伸，所述环形沟槽环设于所述沟槽阵列的外围；
依次形成介质层及导电材料层于所述环形沟槽中以得到环形沟槽结构。
可选地，所述环形沟槽呈圆角正方形环。
可选地，所述沟槽阵列单元中，多个所述线型沟槽的长度一致且等间距排列。
如上所述，本发明的复合沟槽型肖特基二极管器件及其制作方法在晶粒内形成沟槽阵列，该沟槽阵列包括多个排列成至少两行及至少两列的沟槽阵列单元，每个沟槽阵列单元包括多个相互平行且间隔设置的线型沟槽，相邻两个沟槽阵列单元中的线型沟槽数量的延伸方向互相垂直。进一步地，可在沟槽阵列周围设计一条或多条环形沟槽。本发明中，纵横交错的沟槽阵列单元可互相抵消晶圆受到的不同方向的应力；芯片有源区边缘形成的多个环形沟槽同样可以降低晶圆翘曲，而且还可以改善弱器件电场分布集中的问题；这种复合型沟槽器件设计有效改善了晶圆翘曲问题，降低器件位错等缺陷，同时进一步改善电场分布，有助于提高器件稳定性。
附图说明
图1显示为现有技术中一个晶粒中的沟槽排布图。
图2显示为本发明的复合沟槽型肖特基二极管器件的沟槽平面布局图。
图3显示为本发明的复合沟槽型肖特基二极管器件的剖面结构示意图。
图4显示为本发明的复合沟槽型肖特基二极管器件的制作方法的工艺流程图。
图5显示为本发明的复合沟槽型肖特基二极管器件的制作方法提供的衬底的剖面结构示意图。
图6显示为本发明的复合沟槽型肖特基二极管器件的制作方法形成外延层于衬底的正 面后所得结构的剖面结构示意图。
图7显示为本发明的复合沟槽型肖特基二极管器件的制作方法在外延层上生长一层二氧化硅层后所得结构的剖面结构示意图。
图8显示为本发明的复合沟槽型肖特基二极管器件的制作方法在二氧化硅层中形成沟槽的平面图案后所得结构的剖面结构示意图。
图9显示为本发明的复合沟槽型肖特基二极管器件的制作方法以图形化后的二氧化硅层为掩膜对外延层进行刻蚀，在外延层中得到沟槽阵列后所得结构的剖面结构示意图。
图10显示为本发明的复合沟槽型肖特基二极管器件的制作方法去除二氧化硅后所得结构的剖面结构示意图。
图11显示为本发明的复合沟槽型肖特基二极管器件的制作方法在线型沟槽的侧壁和底部形成介质层后所得结构的剖面结构示意图。
图12显示为本发明的复合沟槽型肖特基二极管器件的制作方法在介质层上填充高掺杂多晶硅材料并去除沟槽外多余的多晶硅材料后所得结构的剖面结构示意图。
图13显示为本发明的复合沟槽型肖特基二极管器件的制作方法形成肖特基金属层于外延层的正面后所得结构的剖面结构示意图。
图14显示为本发明的复合沟槽型肖特基二极管器件的制作方法形成正面金属电极层于肖特基金属层上后所得结构的剖面结构示意图。
图15显示为本发明的复合沟槽型肖特基二极管器件的制作方法形成背面金属电极层于衬底的背面后所得结构的剖面结构示意图。
元件标号说明
101                    沟槽
201                    衬底
202                    外延层
203                    沟槽结构阵列
204                    肖特基金属层
205                    正面金属电极层
206                    背面金属电极层
207                    线型沟槽结构
208a                   沟槽结构阵列单元
208b                   沟槽结构阵列单元
208c                   沟槽结构阵列单元
209                    导电材料层
210                    介质层
211                    环形沟槽结构
212                    线型沟槽
213                    二氧化硅层
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图15。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
本实施例中提供一种复合沟槽型肖特基二极管器件，请参阅图2及图3，其中，图2显示为本实施例的复合沟槽型肖特基二极管器件的沟槽平面布局图，图3显示为本实施例的复合沟槽型肖特基二极管器件的剖面结构示意图。
具体的，如图3所示，所述复合沟槽型肖特基二极管器件包括衬底201、外延层202、沟槽结构阵列203、肖特基金属层204、正面金属电极层205及背面金属电极层206，其中，所述衬底201包括相对设置的正面与背面；所述外延层202包括相对设置的正面与背面，所述外延层202的背面与所述衬底201的正面相接触；所述沟槽结构阵列203位于所述外延层202中并自所述外延层202的正面往所述外延层202的背面方向延伸，所述肖特基金属层204位于所述外延层202的正面并覆盖所述沟槽结构阵列203；所述正面金属电极层位于所述肖特基金属层上；所述背面金属电极层位于所述衬底201的背面。
作为示例，所述衬底201可以是硅衬底、锗硅衬底、III-V族元素化合物衬底或本领域技术人员公知的其他半导体材料衬底。本实施例中，所述衬底201选用N型硅衬底，所述外延层202选用N型硅外延层。
特别的，如图2所示，所述沟槽结构阵列203包括多个排列成至少两行及至少两列的 沟槽结构阵列单元，所述沟槽结构阵列单元包括多个相互平行且间隔设置的线型沟槽结构207，相邻两个沟槽结构阵列单元(例如图2中所示沟槽结构阵列单元208a与沟槽结构阵列单元208b，或者沟槽结构阵列单元208a与沟槽结构阵列单元208c)中的线型沟槽结构207的数量延伸方向互相垂直。
具体的，本发明通过在单个晶粒内形成这些纵横交错的沟槽结构阵列单元，可互相抵消晶圆受到的不同方向的应力，有效改善晶圆翘曲问题，并降低器件位错等缺陷。
作为示例，所述沟槽结构阵列单元中，多个所述线型沟槽结构207的长度一致且等间距排列，其中，每一所述沟槽结构阵列单元中的线型沟槽结构207的数量可以根据需要进行调整。
作为示例，如图3所示，所述线型沟槽结构207包括导电材料层209及包覆于所述导电材料层209的侧壁与底面的介质层210，其中，所述导电材料层209的材质可包括掺杂多晶硅或其它合适的导电材料，所述介质层210的材质可包括二氧化硅或其它合适的介电材料。
作为示例，请回头参见图2，在另一可选实施例中，所述复合沟槽型肖特基二极管器件还包括位于所述外延层202中并自所述外延层202的正面往所述外延层202的背面方向延伸的一个或多个环形沟槽结构211，所述环形沟槽结构211环设于所述沟槽结构阵列203的外围。本发明通过在晶粒边缘区形成环形沟槽结构211，可进一步降低晶圆翘曲。
作为示例，所述环形沟槽结构211呈圆角正方形环，也就是说，在环形沟槽转角处做了圆环形沟槽处理，圆环形沟槽可以有效地改善器件电场分布集中的问题。
本实施例的复合沟槽型肖特基二极管器件中，沟槽结构阵列包括多个排列成至少两行及至少两列的沟槽结构阵列单元，每个沟槽结构阵列单元包括多个相互平行且间隔设置的线型沟槽结构，相邻两个沟槽结构阵列单元中的线型沟槽结构的数量延伸方向互相垂直，纵横交错的沟槽结构阵列单元可互相抵消晶圆受到的不同方向的应力。进一步地，本实施例的复合沟槽型肖特基二极管器件可包括设置在沟槽结构阵列周围的一条或多条环形沟槽结构，可以进一步降低晶圆翘曲，而且还可以改善弱器件电场分布集中的问题。总而言之，本实施例的复合沟槽型肖特基二极管器件的这种复合型沟槽设计可有效改善晶圆翘曲问题、降低器件位错等缺陷，同时可进一步改善电场分布，有助于提高器件稳定性。
实施例二
本实施例提供一种复合沟槽型肖特基二极管器件的制作方法，可用于制作实施例一中所述的复合沟槽型肖特基二极管器件，请参阅图4，显示为该制作方法的工艺流程图，包 括以下步骤：
S1：提供一衬底，所述衬底包括相对设置的正面与背面；
S2：形成外延层于所述衬底的正面，所述外延层包括相对设置的正面与背面，所述外延层的背面与所述衬底的正面接触；
S3：形成自所述外延层的正面往所述外延层的背面方向延伸的沟槽阵列于所述外延层中，所述沟槽阵列包括多个排列成至少两行及至少两列的沟槽阵列单元，所述沟槽阵列单元包括多个相互平行且间隔设置的线型沟槽，相邻两个沟槽阵列单元中的线型沟槽的数量延伸方向互相垂直；
S4：依次形成介质层及导电材料层于所述线型沟槽中以得到线型沟槽结构；
S5：形成肖特基金属层于所述外延层的正面，所述肖特基金属层还覆盖所述线型沟槽结构；
S6：形成正面金属电极层于所述肖特基金属层上；
S7：形成背面金属电极层于所述衬底的背面。
首先请参阅图5，执行所述步骤S1：提供一衬底201，所述衬底201包括相对设置的正面与背面。
作为示例，所述衬底201可以是硅衬底、锗硅衬底、III-V族元素化合物衬底或本领域技术人员公知的其他半导体材料衬底。本实施例中，所述衬底201选用N型硅衬底。
再请参阅图6，执行所述步骤S2：形成外延层202于所述衬底201的正面，本实施例中，所述外延层202选用N型硅外延层
再请参阅图7至图10，执行所述步骤S3：形成自所述外延层202的正面往所述外延层202的背面方向延伸的沟槽阵列于所述外延层202中，所述沟槽阵列包括多个排列成至少两行及至少两列的沟槽阵列单元，所述沟槽阵列单元包括多个相互平行且间隔设置的线型沟槽212，相邻两个沟槽阵列单元中的线型沟槽212的数量延伸方向互相垂直。
作为示例，如图7所示，先采用化学气相沉积、物理气相沉积或其它合适的方法在所述外延层202上生长一层二氧化硅层213作为掩膜层。
如图8所示，通过光刻、刻蚀等半导体图形化工艺在所述二氧化硅层213中形成沟槽的平面图案。
如图9所示，以图形化后的所述二氧化硅层213为掩膜对所述外延层202进行刻蚀，在所述外延层202中得到所述沟槽阵列。
如图10所示，采用湿法刻蚀或其它合适的半导体工艺去除所述二氧化硅层213。
具体的，本发明通过在单个晶粒内形成这些纵横交错的沟槽阵列单元，可互相抵消晶 圆受到的不同方向的应力，有效改善晶圆翘曲问题，并降低器件位错等缺陷。
作为示例，所述沟槽阵列单元中，多个所述线型沟槽212的长度一致且等间距排列，其中，每一所述沟槽阵列单元中的线型沟槽212的数量可以根据需要进行调整。
作为示例，在形成所述线型沟槽212的同时，还形成一个或多个环形沟槽于所述外延层202中，所述环形沟槽自所述外延层202的正面往所述外延层202的背面方向延伸，所述环形沟槽环设于所述沟槽阵列的外围。本发明通过在晶粒边缘区形成环形沟槽，可进一步降低晶圆翘曲。
作为示例，所述环形沟槽呈圆角正方形环，也就是说，在环形沟槽的转角处做了圆环形沟槽处理，圆环形沟槽可以有效地改善器件电场分布集中的问题。
再请参阅图11至图12，执行所述步骤S4：依次形成介质层210及导电材料层209于所述线型沟槽212中以得到线型沟槽结构207。
作为示例，如图11所示，先在所述线型沟槽212的侧壁和底部通过热氧化形成二氧化硅材质的所述介质层210。
如图12所示，再在所述介质层210上填充高掺杂多晶硅材料，并采用化学机械抛光或其它合适的平坦化工艺去除沟槽外多余的多晶硅材料，沟槽内剩余的多晶硅材料作为所述导电材料层209。
作为示例，还依次形成所述介质层210及所述导电材料层209于所述环形沟槽中以得到环形沟槽结构211。
再请参阅图13，执行所述步骤S5：采用金属溅射方式或其它合适的方式形成肖特基金属层204于所述外延层202的正面，所述肖特基金属层204还覆盖所述线型沟槽结构207，并进行退火以形成肖特基势垒结。
再请参阅图14，执行所述步骤S6：采用化学气相沉积、物理气相沉积或其它合适的方法形成正面金属电极层205于所述肖特基金属层204上，所述正面金属电极层205作为肖特基二极管的阳极。
作为示例，所述正面金属电极层205的材质可选用钨(W)、钛(Ti)、氮化钽(TaN)、氮化钛(TiN)、铜(Cu)及铝铜(AlCu)中的一种或多种，也可选用其它合适的金属材质。
再请参阅图15，执行所述步骤S7：采用化学气相沉积、物理气相沉积或其它合适的方法形成背面金属电极层206于所述衬底201的背面，所述背面金属电极层206作为肖特基二极管的阴极。
作为示例，所述背面金属电极层206的材质可选用钨(W)、钛(Ti)、氮化钽(TaN)、氮化钛(TiN)、铜(Cu)及铝铜(AlCu)中的一种或多种，也可选用其它合适的金属材质。
至此，制作得到一种复合沟槽型肖特基二极管器件。本实施例的复合沟槽型肖特基二极管器件的制作方法可以在不改变现有工艺和不增加制作成本的基础上有效改善晶圆翘曲的问题，降低器件位错等缺陷，同时进一步改善电场分布，提高器件稳定性。
综上所述，本发明的复合沟槽型肖特基二极管器件及其制作方法在晶粒内形成沟槽阵列，该沟槽阵列包括多个排列成至少两行及至少两列的沟槽阵列单元，每个沟槽阵列单元包括多个相互平行且间隔设置的线型沟槽，相邻两个沟槽阵列单元中的线型沟槽的数量延伸方向互相垂直。进一步地，可在沟槽阵列周围设计一条或多条环形沟槽。本发明中，纵横交错的沟槽阵列单元可互相抵消晶圆受到的不同方向的应力；芯片有源区边缘形成的多个环形沟槽同样可以降低晶圆翘曲，而且还可以改善弱器件电场分布集中的问题；这种复合型沟槽器件设计有效改善了晶圆翘曲问题，降低器件位错等缺陷，同时进一步改善电场分布，有助于提高器件稳定性。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (15)

  1. 一种复合沟槽型肖特基二极管器件，其特征在于，包括：
    衬底，包括相对设置的正面与背面；
    外延层，包括相对设置的正面与背面，其背面与所述衬底的正面接触；
    沟槽结构阵列，位于所述外延层中并自所述外延层的正面往所述外延层的背面方向延伸，所述沟槽结构阵列包括多个排列成至少两行及至少两列的沟槽结构阵列单元，所述沟槽结构阵列单元包括多个相互平行且间隔设置的线型沟槽结构，相邻两个沟槽结构阵列单元中的线型沟槽结构的数量延伸方向互相垂直；
    肖特基金属层，位于所述外延层的正面并覆盖所述线型沟槽结构；
    正面金属电极层，位于所述肖特基金属层上；
    背面金属电极层，位于所述衬底的背面。
  2. 根据权利要求1所述的复合沟槽型肖特基二极管器件，其特征在于：所述复合沟槽型肖特基二极管器件还包括位于所述外延层中并自所述外延层的正面往所述外延层的背面方向延伸的一个或多个环形沟槽结构，所述环形沟槽结构环设于所述沟槽结构阵列的外围。
  3. 根据权利要求2所述的复合沟槽型肖特基二极管器件，其特征在于：所述环形沟槽结构呈圆角正方形环。
  4. 根据权利要求2所述的复合沟槽型肖特基二极管器件，其特征在于：所述线型沟槽结构及所述环形沟槽结构均包括导电材料层及包覆于所述导电材料层的侧壁与底面的介质层。
  5. 根据权利要求4所述的复合沟槽型肖特基二极管器件，其特征在于：所述导电材料的材质包括掺杂多晶硅，所述介质层的材质包括二氧化硅。
  6. 根据权利要求1所述的复合沟槽型肖特基二极管器件，其特征在于：所述沟槽结构阵列单元中，多个所述线型沟槽结构的长度一致且等间距排列。
  7. 根据权利要求1所述的复合沟槽型肖特基二极管器件，其特征在于：所述衬底为硅衬底、锗硅衬底、或III-V族元素化合物，所述外延层选用N型硅外延层。
  8. 根据权利要求1所述的复合沟槽型肖特基二极管器件，其特征在于：所述正面金属电极层和所述背面金属电极层的材质均选用钨、钛、氮化钽、氮化钛、铜及铝铜中的一种或多种。
  9. 一种复合沟槽型肖特基二极管器件的制作方法，其特征在于，包括以下步骤：
    提供一衬底，所述衬底包括相对设置的正面与背面；
    形成外延层于所述衬底的正面，所述外延层包括相对设置的正面与背面，所述外延层的背面与所述衬底的正面接触；
    形成自所述外延层的正面往所述外延层的背面方向延伸的沟槽阵列于所述外延层中，所述沟槽阵列包括多个排列成至少两行及至少两列的沟槽阵列单元，所述沟槽阵列单元包括多个相互平行且间隔设置的线型沟槽，相邻两个沟槽阵列单元中的线型沟槽的数量延伸方向互相垂直；
    依次形成介质层及导电材料层于所述线型沟槽中以得到线型沟槽结构；
    形成肖特基金属层于所述外延层的正面，所述肖特基金属层还覆盖所述线型沟槽结构；形成正面金属电极层于所述肖特基金属层上；
    形成背面金属电极层于所述衬底的背面。
  10. 根据权利要求9所述的复合沟槽型肖特基二极管器件的制作方法，其特征在于，还包括以下步骤：
    形成一个或多个环形沟槽于所述外延层中，所述环形沟槽自所述外延层的正面往所述外延层的背面方向延伸，所述环形沟槽环设于所述沟槽阵列的外围；
    依次形成介质层及导电材料层于所述环形沟槽中以得到环形沟槽结构。
  11. 根据权利要求10所述的复合沟槽型肖特基二极管器件的制作方法，其特征在于：所述环形沟槽呈圆角正方形环。
  12. 根据权利要求9所述的复合沟槽型肖特基二极管器件的制作方法，其特征在于：所述沟槽阵列单元中，多个所述线型沟槽的长度一致且等间距排列。
  13. 根据权利要求9所述的复合沟槽型肖特基二极管器件的制作方法，其特征在于： 在形成自所述外延层的正面往所述外延层的背面方向延伸的沟槽阵列之前，采用化学气相沉积或物理气相沉积在所述外延层上生长一层二氧化硅层作为掩膜层，通过光刻或刻蚀半导体图形化工艺在所述二氧化硅层中形成沟槽的平面图案，以图形化后的所述二氧化硅层为掩膜对所述外延层进行刻蚀，在所述外延层中得到所述沟槽阵列。
  14. 根据权利要求13所述的复合沟槽型肖特基二极管器件的制作方法，其特征在于：在所述外延层中得到所述沟槽阵列之后，采用湿法刻蚀的半导体工艺去除所述二氧化硅层。
  15. 根据权利要求9所述的复合沟槽型肖特基二极管器件的制作方法，其特征在于：形成所述肖特基金属层的方法包括金属溅射方式，形成所述正面金属电极层的方法包括化学气相沉积或物理气相沉积。
PCT/CN2023/113289 2022-10-11 2023-08-16 一种复合沟槽型肖特基二极管器件及其制作方法 WO2024078125A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211241466.1 2022-10-11
CN202211241466.1A CN117913147A (zh) 2022-10-11 2022-10-11 一种复合沟槽型肖特基二极管器件及其制作方法

Publications (1)

Publication Number Publication Date
WO2024078125A1 true WO2024078125A1 (zh) 2024-04-18

Family

ID=90668717

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/113289 WO2024078125A1 (zh) 2022-10-11 2023-08-16 一种复合沟槽型肖特基二极管器件及其制作方法

Country Status (2)

Country Link
CN (1) CN117913147A (zh)
WO (1) WO2024078125A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101901808A (zh) * 2010-06-23 2010-12-01 苏州硅能半导体科技股份有限公司 一种沟槽式肖特基势垒二极管整流器件及制造方法
CN103715130A (zh) * 2012-09-29 2014-04-09 上海华虹宏力半导体制造有限公司 一种改善硅片翘曲度的深沟槽制造方法
CN104701161A (zh) * 2013-12-06 2015-06-10 上海华虹宏力半导体制造有限公司 一种沟槽型肖特基二极管的制备工艺方法
CN105355554A (zh) * 2015-12-10 2016-02-24 天水天光半导体有限责任公司 一种100v肖特基二极管台面制作方法
CN111883527A (zh) * 2020-07-10 2020-11-03 安徽安芯电子科技股份有限公司 一种用于大尺寸晶圆制造的沟槽型肖特基势垒芯片
CN218632054U (zh) * 2022-10-11 2023-03-14 华润微电子（重庆）有限公司 一种复合沟槽型肖特基二极管器件

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101901808A (zh) * 2010-06-23 2010-12-01 苏州硅能半导体科技股份有限公司 一种沟槽式肖特基势垒二极管整流器件及制造方法
CN103715130A (zh) * 2012-09-29 2014-04-09 上海华虹宏力半导体制造有限公司 一种改善硅片翘曲度的深沟槽制造方法
CN104701161A (zh) * 2013-12-06 2015-06-10 上海华虹宏力半导体制造有限公司 一种沟槽型肖特基二极管的制备工艺方法
CN105355554A (zh) * 2015-12-10 2016-02-24 天水天光半导体有限责任公司 一种100v肖特基二极管台面制作方法
CN111883527A (zh) * 2020-07-10 2020-11-03 安徽安芯电子科技股份有限公司 一种用于大尺寸晶圆制造的沟槽型肖特基势垒芯片
CN218632054U (zh) * 2022-10-11 2023-03-14 华润微电子（重庆）有限公司 一种复合沟槽型肖特基二极管器件

Also Published As

Publication number Publication date
CN117913147A (zh) 2024-04-19

Similar Documents

Publication Publication Date Title
US7078780B2 (en) Schottky barrier diode and method of making the same
JP5031985B2 (ja) 多数のボディコンタクト領域を形成できる金属酸化膜半導体電界効果トランジスタデバイス
TWI469351B (zh) 具有超級介面之功率電晶體元件及其製作方法
CN111106135B (zh) 集成芯片以及形成集成芯片的方法
US11088040B2 (en) Cell-like floating-gate test structure
US8993427B2 (en) Method for manufacturing rectifier with vertical MOS structure
JP5687128B2 (ja) 半導体装置およびその製造方法
TW201413797A (zh) Ｍｏｓ電晶體及其形成方法
TWI470699B (zh) 具有超級介面之溝槽型功率電晶體元件及其製作方法
CN218632054U (zh) 一种复合沟槽型肖特基二极管器件
US10388656B2 (en) Semiconductor device having thyristor and metal-oxide semiconductor transistor
WO2024078125A1 (zh) 一种复合沟槽型肖特基二极管器件及其制作方法
WO2020238587A1 (zh) 一种结型势垒肖特基二极管
WO2022142371A1 (zh) 一种半导体器件及其制造方法
WO2013011548A1 (ja) 半導体装置の製造方法
CN111370473A (zh) 一种沟槽型器件及其制备方法
TW202013454A (zh) 半導體裝置
TWI578403B (zh) 溝渠式蕭基二極體及其製作方法
CN216435912U (zh) 肖特基势垒器件
CN219371037U (zh) 一种宽沟槽终止区的肖特基芯片
CN110676220B (zh) 沟槽型mosfet的制作方法、沟槽型mosfet和电子产品
TWI834348B (zh) 半導體裝置
US11545447B2 (en) Method of forming semiconductor device
US20210399105A1 (en) Semiconductor device and fabrication method thereof
US20230301066A1 (en) Semiconductor structure and manufacturing method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23876330

Country of ref document: EP

Kind code of ref document: A1