WO2024060765A1 - 显示面板和电子装置 - Google Patents

显示面板和电子装置 Download PDF

Info

Publication number
WO2024060765A1
WO2024060765A1 PCT/CN2023/103882 CN2023103882W WO2024060765A1 WO 2024060765 A1 WO2024060765 A1 WO 2024060765A1 CN 2023103882 W CN2023103882 W CN 2023103882W WO 2024060765 A1 WO2024060765 A1 WO 2024060765A1
Authority
WO
WIPO (PCT)
Prior art keywords
lead
gate
group
lead group
display area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/103882
Other languages
English (en)
French (fr)
Inventor
李悦
刘波
龚强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US18/558,177 priority Critical patent/US20250089366A1/en
Publication of WO2024060765A1 publication Critical patent/WO2024060765A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136263—Line defects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and an electronic device.
  • a detection circuit that can detect defective phenomena such as signal line short circuit is usually designed on the array substrate.
  • a gate detection circuit is used to detect the gate scan line, and two detection signals are usually used to improve the detection efficiency.
  • the metal traces used to transmit the two detection signals are arranged on two metal layers, and the metal traces on each metal layer transmit a detection signal.
  • the present application provides a display panel and an electronic device to alleviate the technical problem of missed detection in existing display panels during the lighting test process.
  • An embodiment of the present application provides a display panel, which includes a display area and a first non-display area located on one side of the display area.
  • the display panel further includes:
  • a plurality of gate scan lines are provided on the base substrate and located in the display area. Each of the gate scan lines extends along a first direction, and the plurality of gate scan lines extend along a second direction. directionally spaced arrangement;
  • a plurality of first lead groups are provided on the base substrate and located in the first non-display area, each of the first lead groups including at least two gate leads extending along the first direction. , each gate lead is electrically connected to a corresponding gate scan line, and there is a voltage difference between each two adjacent gate leads;
  • a plurality of second lead groups are arranged on the base substrate and located in the first non-display area, each of the second lead groups includes at least two gate leads extending along the first direction, each gate lead is electrically connected to a corresponding gate scanning line, and there is a voltage difference between each two adjacent gate leads;
  • first lead group and the second lead group are located on different layers, and the orthographic projection of the gate leads in the second lead group on the base substrate is different from the orthographic projection of the gate leads in the first lead group.
  • Orthographic projections of the gate leads on the base substrate are alternately arranged.
  • each of the first lead groups further includes a plurality of connecting wires.
  • each connecting wire is electrically connected to a corresponding gate wire, and there is a voltage difference between each two adjacent connecting wires.
  • Each of the second lead wire groups also includes a plurality of connecting wires.
  • each connecting wire is electrically connected to a corresponding gate wire, and each two adjacent connecting wires are electrically connected to each other. There is a voltage difference between the traces;
  • the orthographic projection of the connection traces in the first lead group on the base substrate at least partially overlaps the orthographic projection of the connection traces in the second lead group on the base substrate.
  • the number of gate leads in the first lead group is equal to the number of gate leads in the second lead group, and the number of gate leads in the first lead group is The voltage on the lead is the same as the voltage on the corresponding gate lead in the second lead set.
  • the first wire group includes adjacent first gate wires and second gate wires
  • the second wire group includes adjacent third gate wires and third gate wires.
  • Four gate leads the voltage on the first gate lead is the same as the voltage on the third gate lead
  • the voltage on the second gate lead is the same as the voltage on the fourth gate lead .
  • the display panel further includes a plurality of third lead groups and a plurality of fourth lead groups arranged on the same layer as the first lead group, and each two adjacent One third lead group and one said fourth lead group are disposed between the first lead group, each of the third lead group and the fourth lead group includes at least two gate leads, and the third lead group There is a voltage difference between every two adjacent gate leads in the three-lead group, and there is a voltage difference between every two adjacent gate leads in the fourth lead group;
  • the voltage on at least one gate lead in the third lead set is different from the voltage on the gate lead in the first lead set, and the voltage on the adjacent first lead set and the third lead is In the group, there is a voltage difference between the gate lead in the third lead group close to the first lead group and the gate lead in the first lead group close to the third lead group;
  • the voltage on at least one gate lead in the fourth lead set is different from the voltage on the gate lead in the first lead set, and the voltage on the adjacent first lead set and the fourth lead is In the group, there is a voltage difference between the gate lead in the fourth lead group close to the first lead group and the gate lead in the first lead group close to the fourth lead group; and between adjacent In the third lead group and the fourth lead group, the gate lead in the third lead group close to the fourth lead group and the gate lead in the fourth lead group close to the third lead group There is a voltage difference between the pole leads.
  • the first lead group includes adjacent first gate leads and second gate leads;
  • the third lead group includes adjacent fifth gate leads and the The first gate lead, the fifth gate lead and the second gate lead have a voltage difference, and in the adjacent first lead group and the third lead group, the third The five gate leads are close to the first lead group;
  • the fourth lead group includes an adjacent sixth gate lead and the second gate lead. There is a voltage difference between the sixth gate lead and the first gate lead, and the adjacent sixth gate lead has a voltage difference between the sixth gate lead and the first gate lead. In the first lead group and the fourth lead group, the sixth gate lead is close to the first lead group.
  • the voltage on the fifth gate lead is the same as the voltage on the sixth gate lead.
  • the display panel further includes a second non-display area located on the other side of the display area, and the second non-display area is arranged opposite to the first non-display area.
  • the first lead group and the second lead group are provided in the second non-display area, wherein the first lead group and the second lead group of the first non-display area are connected to odd-numbered rows.
  • the gate scanning lines of the second non-display area are electrically connected to the gate scanning lines of the even-numbered rows.
  • the display panel further includes a second non-display area located on the other side of the display area, and the second non-display area is arranged opposite to the first non-display area.
  • the first lead set and the second lead set are disposed in the second non-display area, wherein the first lead set of the first non-display area and all of the second non-display area
  • the first lead group is symmetrically arranged
  • the second lead group in the first non-display area is symmetrically arranged with the second lead group in the second non-display area.
  • the first lead group or the second lead group and the gate scanning line are arranged in the same layer.
  • An embodiment of the present application also provides an electronic device, which includes the display panel of one of the foregoing embodiments.
  • the display panel includes a plurality of first lead groups and a plurality of second lead groups provided on a substrate.
  • the first lead group and the second lead group are located on different layers.
  • the first Both the lead group and the second lead group include at least two gate leads, each gate lead is electrically connected to a corresponding gate scan line, and there is a gap between each two adjacent gate leads in the first lead group. There is a voltage difference between each two adjacent gate leads in the second lead group. In this way, adjacent gate leads on the same layer transmit different signals. When a short circuit occurs between adjacent gate leads on the same layer, At this time, due to the short circuit between different signals, the voltage on the gate lead after the short circuit will change significantly, which can be detected through a lighting test, effectively reducing missed detections.
  • FIG. 1 is a schematic structural diagram of a top view of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a detailed structural diagram of the first non-display area in FIG. 1 .
  • Figure 3 is a schematic cross-sectional structural diagram along the M-M’ direction in Figure 2.
  • Figure 4 is a schematic cross-sectional structural diagram along the N-N’ direction in Figure 2.
  • FIG. 5 is another top structural schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 6 is a detailed structural diagram of the first non-display area in FIG. 5 .
  • FIG. 7 is another top structural schematic diagram of a display panel provided by an embodiment of the present application.
  • Figure 1 is a schematic top structural view of a display panel provided by an embodiment of the present application.
  • Figure 2 is a detailed structural schematic view of the first non-display area in Figure 1.
  • Figure 3 is a schematic view of the edge M in Figure 2.
  • -M' direction sectional structural schematic diagram Figure 4 is a sectional structural schematic diagram along the N-N' direction in Figure 2.
  • the display panel 100 includes a display area AA and a non-display area surrounding the display area AA.
  • the non-display area includes a first non-display area NA1, a second non-display area NA2 and a third non-display area NA3.
  • the first The non-display area NA1 is located on one side of the display area AA, and the second non-display area NA2 is located on the other side of the display area AA. That is, the second non-display area NA2 is located far away from the display area AA.
  • the first non-display area NA1 and the second non-display area NA2 are arranged opposite to each other.
  • the third non-display area NA3 is located between the first non-display area NA1 and the second non-display area NA2.
  • the display panel 100 includes a liquid crystal display panel, an OLED display panel, etc.
  • the display panel 100 further includes a base substrate 10 and a plurality of gate scanning lines GL, a plurality of data lines DL, a plurality of first lead groups R1 and a plurality of second lead groups provided on the base substrate 10 R2.
  • the substrate substrate 10 is a rigid substrate or a flexible substrate; when the substrate substrate 10 is a rigid substrate, it may include a rigid substrate such as a glass substrate; when the substrate substrate 10 is a flexible substrate, it may Including flexible substrates such as polyimide (PI) films and ultra-thin glass films.
  • PI polyimide
  • a plurality of gate scan lines GL are provided on the base substrate 10 and located in the display area AA.
  • Each of the gate scan lines GL extends along the first direction X, and the plurality of gate scan lines GL extend along the first direction X.
  • the gate scanning lines GL are arranged at intervals along the second direction Y.
  • a plurality of data lines DL are disposed on the base substrate 10 and located in the display area AA.
  • Each of the data lines DL extends along the second direction Y, and the plurality of data lines DL extend along the The first direction X is arranged at intervals.
  • the gate scanning line GL and the data line DL intersect to define a plurality of pixels.
  • the gate scanning line GL is used to provide gate driving signals to the pixels
  • the data line DL is used to provide data signals to the pixels.
  • the first direction X is a horizontal direction
  • the second direction Y is a vertical direction, but the application is not limited thereto.
  • a plurality of first lead groups R1 are arranged on the base substrate 10 and are located in the first non-display area NA1.
  • Each of the first lead groups R1 includes at least two gate leads extending along the first direction X.
  • Each gate lead is electrically connected to a corresponding gate scanning line GL, and there is a voltage difference between each two adjacent gate leads.
  • a plurality of second lead groups R2 are disposed on the base substrate 10 and located in the first non-display area NA1.
  • Each second lead group R2 includes at least two wires extending along the first direction X.
  • Each gate lead is electrically connected to a corresponding gate scan line GL, and there is a voltage difference between each two adjacent gate leads. In this way, adjacent gate leads on the same layer transmit different signals. When a short circuit occurs between adjacent gate leads on the same layer, the voltage on the gate lead after the short circuit will be obvious due to the short circuit between different signals. Changes can then be detected through lighting tests, effectively reducing missed detections.
  • first lead set R1 and the second lead set R2 are located on different layers, and the orthographic projection of the gate leads in the second lead set R2 on the base substrate 10 is different from that of the first lead set R2.
  • the orthographic projections of the gate leads in the lead group R1 on the base substrate 10 are alternately arranged.
  • the first lead group R1 is formed of a first metal layer
  • the second lead group R2 is formed of a second metal layer
  • the first metal layer is located away from the second metal layer and the substrate one side of the substrate 10 .
  • the first lead line group R1 or the second lead line group R2 is arranged in the same layer as the gate scanning line GL.
  • the number of gate leads in the first lead group R1 is equal to the number of gate leads in the second lead group R2, and the voltage on the gate leads in the first lead group R1 is the same as the voltage on the gate leads in the second lead group R2.
  • the voltages on the corresponding gate leads in the two lead sets R2 are the same.
  • the first wire group R1 includes adjacent first gate wires G1 and second gate wires G2.
  • the first gate wires G1 and the second The gate leads G2 both extend along the first direction X, and the first gate leads G1 and the second gate leads G2 are insulated from each other.
  • the voltage on the first gate lead G1 is 9V
  • the voltage on the second gate lead G2 is -7V.
  • the second lead group R2 includes adjacent third gate lead G3 and fourth gate lead G4, both of the third gate lead G3 and the fourth gate lead G4 are along the first direction X. extending, and the third gate lead G3 and the fourth gate lead G4 are spaced apart and insulated.
  • the voltage on the third gate lead G3 is the same as the voltage on the first gate lead G1
  • the voltage on the fourth gate lead G4 is the same as the voltage on the second gate lead G2.
  • the same voltage means that the amplitude of the voltage is the same.
  • the voltage on the third gate lead G3 is also 9V
  • the voltage on the fourth gate lead G4 is also -7V.
  • the first gate lead G1 and the third gate lead G3 are located on different metal layers.
  • the gate lead G2 and the fourth gate lead G4 are located on different metal layers, as shown in FIG. 3 .
  • An interlayer insulating layer 20 is provided between the first gate lead G1 and the third gate lead G3, so that the gate leads in the first lead group R1 are in contact with the second lead group R2. insulation between the gate leads.
  • each of the first lead groups R1 further includes a plurality of connecting wires, and within the same first lead group R1, each connecting wire is electrically connected to a corresponding gate wire, and there is a voltage difference between each two adjacent connecting wires.
  • the connecting wires within the first lead group R1 and the gate wires within the first lead group R1 are formed by the same metal layer.
  • the first lead group R1 further includes adjacent first connecting wires C1 and second connecting wires C2, the first connecting wires C1 are electrically connected to the first gate lead G1, and part of the first connecting wires C1 extend along the second direction Y.
  • the second connecting wires C2 are electrically connected to the second gate lead G2, and part of the second connecting wires C2 extend along the second direction Y.
  • the first connecting wires C1 and the second connecting wires C2 are arranged alternately, and the first connecting wires C1 and the second connecting wires C2 are insulated from each other.
  • Each second lead group R2 also includes a plurality of connecting wires. Within the same second lead group R2, each connecting wire is electrically connected to a corresponding gate wire. Each two adjacent wires are electrically connected to each other. There is a voltage difference between the connecting traces. In this way, adjacent connection traces on the same layer transmit different signals. When a short circuit occurs between adjacent connection traces on the same layer, the voltage on the connection trace after the short circuit will be obvious due to the short circuit between different signals. Changes can then be detected through lighting tests, further effectively reducing the chance of missed detections. Of course, in order to further reduce the probability of missed detection, there is a voltage difference between any two adjacent connection traces on the same metal layer along the first direction X.
  • connection traces in the second lead group R2 and the gate traces in the first lead group R1 are formed from the same metal layer. In this way, the connection traces in the second lead group R2 and the first The connection traces in the lead group R1 are located in different metal layers, so that the width of the first non-display area NA1 in the first direction X can be reduced, thereby reducing the frame of the display panel 100 .
  • the second lead group R2 also includes adjacent third connection wires C3 and fourth connection wires C4, and the third connection wire C3 is electrically connected to the third gate lead G3, And part of the third connection trace C3 extends along the second direction Y.
  • the fourth connection line C4 is electrically connected to the fourth gate lead G4, and part of the fourth connection line C4 extends along the second direction Y.
  • the third connection wire C3 and the fourth connection wire C4 are arranged at intervals, and there is Insulated from each other.
  • the orthographic projection of the connection traces in the first lead group R1 on the base substrate 10 At least partially overlaps with the orthographic projection of the connection traces in the second lead group R2 on the base substrate 10 .
  • part of the connection traces in the first lead group R1 covers part of the connection traces in the second lead group R2
  • part of the first connection trace C1 covers part of the fourth Connection trace C4
  • part of the second connection trace C2 covers part of the third connection trace C3.
  • the coverage refers to the orthographic projection of the connection traces in the first lead group R1 on the base substrate 10 and the connection traces in the second lead group R2 on the base substrate 10
  • the positional relationship of the orthographic projection for example, part of the first connection trace C1 covering part of the fourth connection trace C4 refers to the orthographic projection of the first connection trace C1 on the base substrate 10 and
  • the orthographic projection of the fourth connection trace C4 on the base substrate 10 overlaps in the first direction X, but the same is true between the first connection trace C1 and the fourth connection trace C4.
  • the interlayer insulating layer 20 is spaced so that the first connection trace C1 and the fourth connection trace C4 are insulated from each other, as shown in FIG. 4 .
  • connection traces in the second lead set R2 that are blocked by the connection traces in the first lead set R1
  • the second lead set is removed in Figure 2
  • the connection traces in R2 are above some of the connection traces in the first lead group R1.
  • the second connection trace C2 in FIG. 2 covers the third connection trace C3, so that the third connection trace C3 is blocked by the second connection trace C2.
  • the third connection trace C3 removes the part of the second connection trace C2 above the third connection trace C3.
  • the second non-display area NA2 is also provided with a plurality of first lead groups R1 and a plurality of second lead groups R2, and the first lead group R1 and a plurality of second lead groups R2 of the second non-display area NA2 are
  • the first lead group R1 of the first non-display area NA1 has the same structure
  • the second lead group R2 of the second non-display area NA2 is the same as the second lead group R2 of the first non-display area NA1
  • the structure is the same.
  • first lead group R1 and the second lead group R2 of the first non-display area NA1 are electrically connected to the gate scan lines GL of odd-numbered rows, and the second non-display area NA1
  • the first lead group R1 and the second lead group R2 of NA2 are electrically connected to the gate scan lines GL of the even rows.
  • a terminal area is provided in the third non-display area NA3.
  • the terminal area includes a first gate terminal area GP1 and a second gate terminal area GP2 and is located between the first gate terminal area GP1 and the second gate terminal area GP2.
  • the source terminal SP region between the second gate terminal region GP2, wherein a gate terminal GP is provided in both the first gate terminal region GP1 and the second gate terminal region GP2, and the first gate terminal region GP2 is provided with a gate terminal GP.
  • the gate terminal GP in the terminal area GP1 is electrically connected to the first lead group R1 and the second lead group R2 in the first non-display area NA1, and is used to provide power to the first non-display area NA1.
  • the first lead group R1 and the second lead group R2 provide gate driving signals.
  • the gate terminal GP in the second gate terminal area GP2 is electrically connected to the first lead group R1 and the second lead group R2 in the second non-display area NA2, and is used to provide power to the second gate terminal area GP2.
  • the first lead group R1 and the second lead group R2 of the non-display area NA2 provide gate driving signals.
  • An active terminal SP is provided in the source terminal SP area.
  • the source terminal SP is electrically connected to the data line DL in the display and is used to provide data signals to the data line DL.
  • the third non-display area NA3 is also provided with a fan-out path.
  • the fan-out wiring is electrically connected to the corresponding connecting wiring in each lead group (including the first lead group R1, the second lead group R2, etc.).
  • the third non-display area NA3 is also provided with a first signal access point GS1 and a second signal access point GS2.
  • the first signal access point GS1 and the second signal access point GS2 provide different voltages.
  • the first signal access point GS1 provides a voltage of 9V
  • the second signal access point GS2 provides -7V. voltage.
  • the first gate lead G1, the third gate lead G3, the first connection line C1 and the third connection line C3 are all connected to the voltage of the first signal point
  • the third connection line C1 is connected to the voltage of the first signal point.
  • the second gate lead G2, the fourth gate lead G4, the second connection line C2, and the fourth connection line C4 are all connected to the voltage of the second signal point.
  • FIG. 5 is another top structural schematic diagram of a display panel provided by an embodiment of the present application
  • FIG. 6 is a detailed structural schematic diagram of the first non-display area in FIG. 5
  • the display panel 101 also includes a plurality of third lead groups R3 and a plurality of fourth lead groups R4 arranged on the same layer as the first lead group R1.
  • a third lead group R3 and a fourth lead group R4 are provided between the first lead group R1, and each of the third lead group R3 and the fourth lead group R4 includes at least two gates. There is a voltage difference between every two adjacent gate leads in the third lead group R3, and there is a voltage difference between every two adjacent gate leads in the fourth lead group R4.
  • the voltage on at least one gate lead in the third lead group R3 is different from the voltage on the gate lead in the first lead group R1, and in the adjacent first lead group R1 and the third lead group R3, there is a voltage difference between the gate lead in the third lead group R3 close to the first lead group R1 and the gate lead in the first lead group R1 close to the third lead group R3.
  • the voltage on at least one gate lead in the fourth lead group R4 is different from the voltage on the gate lead in the first lead group R1, and between the adjacent first lead group R1 and the In the fourth lead group R4, there is a gap between the gate lead in the fourth lead group R4 close to the first lead group R1 and the gate lead in the first lead group R1 close to the fourth lead group R4. voltage difference; and in the adjacent third lead group R3 and the fourth lead group R4, the gate lead in the third lead group R3 close to the fourth lead group R4 and the fourth There is a voltage difference between the gate leads in the lead set R4 and close to the third lead set R3.
  • the third lead group R3 includes the adjacent fifth gate lead G5 and the first gate lead G1. There is a voltage difference between the fifth gate lead G5 and the second gate lead G2, and In the adjacent first lead group R1 and the third lead group R3, the fifth gate lead G5 is close to the first lead group R1.
  • the fourth lead group R4 includes the adjacent sixth gate lead G6 and the second gate lead G2. There is a voltage difference between the sixth gate lead G6 and the first gate lead G1, and In the adjacent first lead group R1 and the fourth lead group R4, the sixth gate lead G6 is close to the first lead group R1.
  • the display panel 100 further includes a plurality of fifth lead groups R5 and a plurality of sixth lead groups R6 arranged in the same layer as the second lead group R2.
  • Each adjacent two second lead groups One fifth lead group R5 and one sixth lead group R6 are disposed between the groups R2.
  • Each of the fifth lead group R5 and the sixth lead group R6 includes at least two gate leads, and all There is a voltage difference between every two adjacent gate leads in the fifth lead group R5, and there is a voltage difference between every two adjacent gate leads in the sixth lead group R6.
  • the voltage on at least one gate lead in the fifth lead group R5 is different from the voltage on the gate lead in the second lead group R2, and in the adjacent second lead group R2 and the fifth lead group R5, there is a voltage difference between the gate lead in the fifth lead group R5 close to the second lead group R2 and the gate lead in the second lead group R2 close to the fifth lead group R5.
  • the voltage on at least one gate lead in the sixth lead group R6 is different from the voltage on the gate lead in the second lead group R2, and between the adjacent second lead group R2 and the In the sixth lead group R6, there is a gap between the gate lead in the sixth lead group R6 close to the second lead group R2 and the gate lead in the second lead group R2 close to the sixth lead group R6. voltage difference; and in the adjacent fifth lead group R5 and the sixth lead group R6, the gate lead in the fifth lead group R5 close to the sixth lead group R6 and the sixth There is a voltage difference between the gate leads in the lead set R6 close to the fifth lead set R5.
  • the fifth lead group R5 includes the adjacent seventh gate lead G7 and the first gate lead G1. There is a voltage difference between the sixth gate lead G6 and the second gate lead G2, and In the adjacent second lead group R2 and the fifth lead group R5, the sixth gate lead G6 is close to the second lead group R2.
  • the sixth lead group R6 includes an adjacent eighth gate lead G8 and the second gate lead G2. There is a voltage difference between the eighth gate lead G8 and the first gate lead G1, and In the adjacent second lead group R2 and the sixth lead group R6, the eighth gate lead G8 is close to the second lead group R2.
  • the voltage on the fifth gate lead G5 is the same as the voltage on the sixth gate lead G6, and the voltage on the seventh gate lead G7 is the same as the voltage on the eighth gate lead G8.
  • the voltages on the fifth gate lead G5 and the voltage on the seventh gate lead G7 are the same. In this way, it is only necessary to add the third signal access point GS3 in the third non-display area NA3 to avoid adding too many signal access points and thereby reduce the difficulty of the lighting test.
  • the third lead group R3, the fourth lead group R4, the fifth lead group R5 and the sixth lead group R6 all further include a connection line electrically connected to the gate lead.
  • the third lead group R3 includes the adjacent fifth connection line C5 and the first connection line C1
  • the fourth lead group R4 includes the adjacent second connection line C2 and the sixth connection line C6
  • the fifth lead group R5 includes the adjacent seventh connection line C7 and the third connection line C3
  • the sixth lead group R6 includes the adjacent fourth connection line C4 and the eighth connection line C8.
  • the first direction X there is a voltage difference between any two adjacent connection lines on the same metal layer.
  • FIG. 7 is another top structural schematic diagram of a display panel provided by an embodiment of the present application. Different from the above embodiment, the display panel 102 also includes a second non-display area NA2 located on the other side of the display area AA.
  • an embodiment of the present application also provides an electronic device, which includes the display panel of one of the foregoing embodiments.
  • the electronic devices include mobile phones, tablets, televisions and other electronic display products.
  • the present application provides a display panel and an electronic device.
  • the display panel includes a plurality of first lead groups and a plurality of second lead groups provided on a substrate.
  • the first lead group and the second lead group are located on different layers.
  • Each of the first lead group and the second lead group includes at least two gate leads, each gate lead is electrically connected to a corresponding gate scan line, and there is a gap between each two adjacent gate leads in the first lead group.
  • There is a voltage difference and there is a voltage difference between each two adjacent gate leads in the second lead group.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示面板(100,101,102)和电子装置，显示面板(100,101,102)的第一引线组(R1)和第二引线组(R2)位于不同层，第一引线组(R1)内每相邻的两条栅极引线(G)间具有电压差，第二引线组(R2)内每相邻的两条栅极引线(G)间也具有电压差，当同一层相邻的栅极引线(G)之间发生短路时，栅极引线(G)上的电压会有明显变化，进而可以通过点灯测试检测出来，有效减少漏检。

Description

显示面板和电子装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板和电子装置。
 背景技术
在显示面板的制造过程中，为了及时拦检到不良品，会对显示面板进行点灯测试（Cell Test）。为此通常会在阵列基板上设计能够检测信号线短路等不良现象的检测电路。比如用于检测栅极扫描线的栅极检测电路，而为了提高检测效率通常会采用两种检测信号。同时为了减小显示面板的边框，用于传输两种检测信号的金属走线会布置在两个金属层，每个金属层上的金属走线传输一种检测信号。但当同一金属层上相邻的金属走线之间发生短路时，由于是相同信号之间的短路，无法通过点灯测试检出不良，如此会导致漏检。
 发明概述
本申请提供一种显示面板和电子装置，以缓解现有显示面板在点灯测试制程中存在漏检的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，其包括显示区和位于显示区一侧的第一非显示区，所述显示面板还包括：
衬底基板；
多条栅极扫描线，设置在所述衬底基板上，并位于所述显示区内，每条所述栅极扫描线沿第一方向延伸，且多条所述栅极扫描线沿第二方向间隔排布；
多个第一引线组，设置在所述衬底基板上，并位于所述第一非显示区内，每个所述第一引线组包括至少两条沿所述第一方向延伸的栅极引线，每条栅极引线与对应的一条栅极扫描线电连接，且每相邻的两条栅极引线间具有电压差；以及
多个第二引线组，设置在所述衬底基板上，并位于所述第一非显示区内，每个所述第二引线组包括至少两条沿所述第一方向延伸的栅极引线，每条栅极引线与对应的一条栅极扫描线电连接，且每相邻的两条栅极引线间具有电压差；
其中，所述第一引线组和所述第二引线组位于不同层，且所述第二引线组内的栅极引线在所述衬底基板上的正投影与所述第一引线组内的栅极引线在所述衬底基板上的正投影交替排布。
在本申请实施例提供的显示面板中，每个所述第一引线组还包括多条连接走线，在同一所述第一引线组内，每条连接走线分别与对应的一条栅极走线电连接，每相邻的两个连接走线间具有电压差；
每个所述第二引线组还包括多条连接走线，在同一所述第二引线组内，每条连接走线分别与对应的一条栅极走线电连接，每相邻的两个连接走线间具有电压差；
其中，所述第一引线组内的连接走线在所述衬底基板上的正投影与所述第二引线组内的连接走线在所述衬底基板上的正投影至少部分重叠。
在本申请实施例提供的显示面板中，所述第一引线组内的栅极引线的数量等于所述第二引线组内的栅极引线的数量，且所述第一引线组内的栅极引线上的电压与所述第二引线组内的对应的栅极引线上的电压相同。
在本申请实施例提供的显示面板中，所述第一引线组包括相邻的第一栅极引线和第二栅极引线，所述第二引线组包括相邻的第三栅极引线和第四栅极引线，所述第一栅极引线上的电压与所述第三栅极引线上的电压相同，所述第二栅极引线上的电压与所述第四栅极引线上的电压相同。
在本申请实施例提供的显示面板中，所述显示面板还包括与所述第一引线组同层设置的多个第三引线组和多个第四引线组，每相邻的两个所述第一引线组之间设置有一个所述第三引线组和一个所述第四引线组，所述第三引线组和所述第四引线组均包括至少两个栅极引线，且所述第三引线组内每相邻的两个栅极引线间具有电压差，所述第四引线组内每相邻的两个栅极引线间具有电压差；
所述第三引线组内的至少一条栅极引线上的电压与所述第一引线组内的栅极引线上的电压不同，且在相邻的所述第一引线组和所述第三引线组中，所述第三引线组内靠近所述第一引线组的栅极引线与所述第一引线组内靠近所述第三引线组的栅极引线间具有电压差；
所述第四引线组内的至少一条栅极引线上的电压与所述第一引线组内的栅极引线上的电压不同，且在相邻的所述第一引线组和所述第四引线组中，所述第四引线组内靠近所述第一引线组的栅极引线与所述第一引线组内靠近所述第四引线组的栅极引线间具有电压差；并在相邻的所述第三引线组和所述第四引线组内，所述第三引线组内靠近所述第四引线组的栅极引线与所述第四引线组内靠近所述第三引线组的栅极引线间具有电压差。
在本申请实施例提供的显示面板中，所述第一引线组包括相邻的第一栅极引线和第二栅极引线；所述第三引线组包括相邻的第五栅极引线和所述第一栅极引线，所述第五栅极引线与所述第二栅极引线间具有电压差，且在相邻的所述第一引线组和所述第三引线组中，所述第五栅极引线靠近所述第一引线组；
所述第四引线组包括相邻的第六栅极引线和所述第二栅极引线，所述第六栅极引线与所述第一栅极引线间具有电压差，且在相邻的所述第一引线组和所述第四引线组中，所述第六栅极引线靠近所述第一引线组。
在本申请实施例提供的显示面板中，所述第五栅极引线上的电压与所述第六栅极引线上的电压相同。
在本申请实施例提供的显示面板中，所述显示面板还包括位于所述显示区的另一侧的第二非显示区，所述第二非显示区和所述第一非显示区相对设置，所述第二非显示区内设置有所述第一引线组和所述第二引线组，其中所述第一非显示区的所述第一引线组和所述第二引线组与奇数行的所述栅极扫描线电连接，所述第二非显示区的所述第一引线组和所述第二引线组与偶数行的所述栅极扫描线电连接。
在本申请实施例提供的显示面板中，所述显示面板还包括位于所述显示区的另一侧的第二非显示区，所述第二非显示区和所述第一非显示区相对设置，所述第二非显示区内设置有所述第一引线组和所述第二引线组，其中所述第一非显示区的所述第一引线组与所述第二非显示区的所述第一引线组对称设置，所述第一非显示区的所述第二引线组与所述第二非显示区的所述第二引线组对称设置。
在本申请实施例提供的显示面板中，所述第一引线组或所述第二引线组与所述栅极扫描线同层设置。
本申请实施例还提供一种电子装置，其包括前述实施例其中之一的显示面板。
有益效果
本申请提供的显示面板和电子装置中，显示面板包括设置在衬底基板上的多个第一引线组和多个第二引线组，第一引线组和第二引线组位于不同层，第一引线组和第二引线组内均包括至少两条栅极引线，每条栅极引线与对应的一条栅极扫描线电连接，且第一引线组内每相邻的两条栅极引线间具有电压差，第二引线组内每相邻的两条栅极引线间也具有电压差，如此同一层相邻的栅极引线传输不同的信号，当同一层相邻的栅极引线之间发生短路时，由于是不同信号间的短路，使得短路后的栅极引线上的电压会有明显变化，进而可以通过点灯测试检测出来，有效减少漏检。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的一种俯视结构示意图。
图2为图1中第一非显示区的细节结构示意图。
图3为图2中沿M-M’方向的剖面结构示意图。
图4为图2中沿N-N’方向的剖面结构示意图。
图5为本申请实施例提供的显示面板的另一种俯视结构示意图。
图6为图5中第一非显示区的细节结构示意图。
图7为本申请实施例提供的显示面板的又一种俯视结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
请参照图1至图4，图1为本申请实施例提供的显示面板的一种俯视结构示意图，图2为图1中第一非显示区的细节结构示意图，图3为图2中沿M-M’方向的剖面结构示意图，图4为图2中沿N-N’方向的剖面结构示意图。显示面板100包括显示区AA和围绕所述显示区AA的非显示区，所述非显示区包括第一非显示区NA1、第二非显示区NA2以及第三非显示区NA3，所述第一非显示区NA1位于所述显示区AA的一侧，所述第二非显示区NA2位于所述显示区AA的另一侧，也即所述第二非显示区NA2位于所述显示区AA远离所述第一非显示区NA1的一侧，使所述第一非显示区NA1和所述第二非显示区NA2相对设置。所述第三非显示区NA3位于所述第一非显示区NA1和所述第二非显示区NA2之间。可选地，所述显示面板100包括液晶显示面板、OLED显示面板等。
所述显示面板100还包括衬底基板10以及设置在所述衬底基板10上的多条栅极扫描线GL、多条数据线DL、多个第一引线组R1、多个第二引线组R2。可选地，所述衬底基板10为刚性基板或柔性基板；当所述衬底基板10为刚性基板时，可包括玻璃基板等硬性基板；当所述衬底基板10为柔性基板时，可包括聚酰亚胺（Polyimide，PI）薄膜、超薄玻璃薄膜等柔性基板。
参照图1，多条栅极扫描线GL设置在所述衬底基板10上，并位于所述显示区AA内，每条所述栅极扫描线GL沿第一方向X延伸，且多条所述栅极扫描线GL沿第二方向Y间隔排布。多条数据线DL设置在所述衬底基板10上，并位于所述显示区AA内，每条所述数据线DL沿所述第二方向Y延伸，且多条所述数据线DL沿所述第一方向X间隔排布。所述栅极扫描线GL和所述数据线DL交叉限定出多个像素，所述栅极扫描线GL用于给像素提供栅极驱动信号，所述数据线DL用于给像素提供数据信号。其中所述第一方向X为水平方向，所述第二方向Y为竖直方向，但本申请不限于此。
多个第一引线组R1设置在所述衬底基板10上，并位于所述第一非显示区NA1内，每个所述第一引线组R1包括至少两条沿所述第一方向X延伸的栅极引线，每条栅极引线与对应的一条栅极扫描线GL电连接，且每相邻的两条栅极引线间具有电压差。
多个第二引线组R2设置在所述衬底基板10上，并位于所述第一非显示区NA1内，每个所述第二引线组R2包括至少两条沿所述第一方向X延伸的栅极引线，每条栅极引线与对应的一条栅极扫描线GL电连接，且每相邻的两条栅极引线间具有电压差。如此同一层相邻的栅极引线传输不同的信号，当同一层相邻的栅极引线之间发生短路时，由于是不同信号间的短路，使得短路后的栅极引线上的电压会有明显变化，进而可以通过点灯测试检测出来，有效减少漏检。
其中，所述第一引线组R1和所述第二引线组R2位于不同层，且所述第二引线组R2内的栅极引线在所述衬底基板10上的正投影与所述第一引线组R1内的栅极引线在所述衬底基板10上的正投影交替排布。
可选地，所述第一引线组R1由第一金属层形成，所述第二引线组R2由第二金属层形成，所述第一金属层位于所述第二金属层远离所述衬底基板10的一侧。所述第一引线组R1或所述第二引线组R2与所述栅极扫描线GL同层设置。所述第一引线组R1内的栅极引线的数量等于所述第二引线组R2内的栅极引线的数量，且所述第一引线组R1内的栅极引线上的电压与所述第二引线组R2内的对应的栅极引线上的电压相同。
可选地，结合参照图1和图2，所述第一引线组R1包括相邻的第一栅极引线G1和第二栅极引线G2，所述第一栅极引线G1和所述第二栅极引线G2均沿所述第一方向X延伸，且所述第一栅极引线G1和所述第二栅极引线G2之间间隔绝缘设置。所述第一栅极引线G1和所述第二栅极引线G2之间具有电压差，比如所述第一栅极引线G1上的电压为9V，所述第二栅极引线G2上的电压为-7V。
所述第二引线组R2包括相邻的第三栅极引线G3和第四栅极引线G4，所述第三栅极引线G3和所述第四栅极引线G4均沿所述第一方向X延伸，且所述第三栅极引线G3和所述第四栅极引线G4之间间隔绝缘设置。所述第三栅极引线G3上的电压与所述第一栅极引线G1上的电压相同，所述第四栅极引线G4上的电压与所述第二栅极引线G2上的电压相同。其中所述电压相同是指电压的幅值相同，比如所述第三栅极引线G3上的电压也为9V，所述第四栅极引线G4上的电压也为-7V。
同时由于所述第一引线组R1和所述第二引线组R2位于不同金属层，则所述第一栅极引线G1和所述第三栅极引线G3位于不同的金属层，所述第二栅极引线G2和所述第四栅极引线G4位于不同的金属层，如图3所示。所述第一栅极引线G1和所述第三栅极引线G3之间设置有层间绝缘层20，以使所述第一引线组R1内的栅极引线与所述第二引线组R2内的栅极引线之间绝缘。
进一步地，继续参照图1和图2，每个所述第一引线组R1还包括多条连接走线，在同一所述第一引线组R1内，每条连接走线分别与对应的一条栅极走线电连接，每相邻的两个连接走线间具有电压差。所述第一引线组R1内的连接走线与所述第一引线组R1内的栅极走线由同一金属层形成。可选地，所述第一引线组R1还包括相邻的第一连接走线C1和第二连接走线C2，所述第一连接走线C1与所述第一栅极引线G1电连接，且部分所述第一连接走线C1沿所述第二方向Y延伸。所述第二连接走线C2与所述第二栅极引线G2电连接，且部分所述第二连接走线C2沿所述第二方向Y延伸。在所述第一方向X上，所述第一连接走线C1和所述第二连接走线C2间隔排布，且所述第一连接走线C1和所述第二连接走线C2之间彼此绝缘。
每个所述第二引线组R2还包括多条连接走线，在同一所述第二引线组R2内，每条连接走线分别与对应的一条栅极走线电连接，每相邻的两个连接走线间具有电压差。如此同一层相邻的连接走线传输不同的信号，当同一层相邻的连接走线之间发生短路时，由于是不同信号间的短路，使得短路后的连接走线上的电压会有明显变化，进而可以通过点灯测试检测出来，进一步有效降低漏检的几率。当然地，为了更进一步降低漏检的几率，在沿所述第一方向X上，同一金属层上任意相邻的两个连接走线间均具有电压差。
所述第二引线组R2内的连接走线与所述第一引线组R1内的栅极走线由同一金属层形成，如此所述第二引线组R2内的连接走线与所述第一引线组R1内的连接走线位于不同的金属层，从而能够减小所述第一非显示区NA1在所述第一方向X上的宽度，进而减小所述显示面板100的边框。
可选地，所述第二引线组R2还包括相邻的第三连接走线C3和第四连接走线C4，所述第三连接走线C3与所述第三栅极引线G3电连接，且部分所述第三连接走线C3沿所述第二方向Y延伸。所述第四连接走线C4与所述第四栅极引线G4电连接，且部分所述第四连接走线C4沿所述第二方向Y延伸。在所述第一方向X上，所述第三连接走线C3和所述第四连接走线C4间隔排布，且所述第三连接走线C3和所述第四连接走线C4之间彼此绝缘。
可选地，为了进一步减小所述第一非显示区NA1在所述第一方向X上的宽度，所述第一引线组R1内的连接走线在所述衬底基板10上的正投影与所述第二引线组R2内的连接走线在所述衬底基板10上的正投影至少部分重叠。如图2所示，所述第一引线组R1内的部分连接走线覆盖所述第二引线组R2内的部分连接走线，比如部分所述第一连接走线C1覆盖部分所述第四连接走线C4，部分所述第二连接走线C2覆盖部分所述第三连接走线C3。其中所述覆盖是指所述第一引线组R1内的连接走线在所述衬底基板10上的正投影与所述第二引线组R2内的连接走线在所述衬底基板10上的正投影的位置关系，比如部分所述第一连接走线C1覆盖部分所述第四连接走线C4即是指所述第一连接走线C1在所述衬底基板10上的正投影与所述第四连接走线C4在所述衬底基板10上的正投影在所述第一方向X上重叠，但所述第一连接走线C1与所述第四连接走线C4之间同样有所述层间绝缘层20间隔，使得所述第一连接走线C1和所述第四连接走线C4之间彼此绝缘，如图4所示。
需要说明的是，图2为了清楚示出被所述第一引线组R1内的连接走线遮挡的所述第二引线组R2内的连接走线，图2中去除了所述第二引线组R2内的连接走线上面的所述第一引线组R1内的部分连接走线。比如图2中的所述第二连接走线C2覆盖所述第三连接走线C3，使得所述第三连接走线C3被所述第二连接走线C2遮挡，而为了清楚示出所述第三连接走线C3，去除了所述第三连接走线C3上面的部分所述第二连接走线C2。
进一步地，所述第二非显示区NA2也设置有多个所述第一引线组R1和多个第二引线组R2，而且所述第二非显示区NA2的所述第一引线组R1与所述第一非显示区NA1的所述第一引线组R1结构相同，所述第二非显示区NA2的第二引线组R2与所述第一非显示区NA1的所述第二引线组R2结构相同。不同的地方在于，所述第一非显示区NA1的所述第一引线组R1和所述第二引线组R2与奇数行的所述栅极扫描线GL电连接，所述第二非显示区NA2的所述第一引线组R1和所述第二引线组R2与偶数行的所述栅极扫描线GL电连接。
进一步地，所述第三非显示区NA3内设置有端子区，所述端子区包括第一栅极端子区GP1和第二栅极端子区GP2以及位于所述第一栅极端子区GP1和所述第二栅极端子区GP2之间的源端子SP区，其中所述第一栅极端子区GP1和所述第二栅极端子区GP2内均设置有栅极端子GP，所述第一栅极端子区GP1内的栅极端子GP与所述第一非显示区NA1内的所述第一引线组R1以及所述第二引线组R2电连接，用于给所述第一非显示区NA1的所述第一引线组R1以及所述第二引线组R2提供栅极驱动信号。所述第二栅极端子区GP2内的栅极端子GP与所述第二非显示区NA2的所述第一引线组R1以及所述第二引线组R2电连接，用于给所述第二非显示区NA2的所述第一引线组R1以及所述第二引线组R2提供栅极驱动信号。所述源端子SP区内设置有源端子SP，所述源端子SP与所述显示内的所述数据线DL电连接，用于给所述数据线DL提供数据信号。
当然地，为了使所述第三非显示区NA3的栅极端子GP与所述第一引线组R1和所述第二引线组R2电连接，所述第三非显示区NA3还设置有扇出走线，所述扇出走线与各引线组（包括第一引线组R1、第二引线组R2等）内对应的连接走线电连接。
而为了给各引线组内的连接走线以及栅极引线提供不同的电压信号，所述第三非显示区NA3还设置有第一信号接入点GS1和第二信号接入点GS2，所述第一信号接入点GS1和所述第二信号接入点GS2提供的电压不同，比如所述第一信号接入点GS1提供9V的电压，而所述第二信号接入点GS2提供-7V的电压。所述第一栅极引线G1、所述第三栅极引线G3、所述第一连接走线C1以及所述第三连接走线C3均接入所述第一信号点的电压，所述第二栅极引线G2、所述第四栅极引线G4、所述第二连接走线C2以及所述第四连接走线C4均接入所述第二信号点的电压。
在一种实施例中，结合参照图1至图6，图5为本申请实施例提供的显示面板的另一种俯视结构示意图，图6为图5中第一非显示区的细节结构示意图。与上述实施例不同的是，所述显示面板101还包括与所述第一引线组R1同层设置的多个第三引线组R3和多个第四引线组R4，每相邻的两个所述第一引线组R1之间设置有一个所述第三引线组R3和一个所述第四引线组R4，所述第三引线组R3和所述第四引线组R4均包括至少两个栅极引线，且所述第三引线组R3内每相邻的两个栅极引线间具有电压差，所述第四引线组R4内每相邻的两个栅极引线间具有电压差。
所述第三引线组R3内的至少一条栅极引线上的电压与所述第一引线组R1内的栅极引线上的电压不同，且在相邻的所述第一引线组R1和所述第三引线组R3中，所述第三引线组R3内靠近所述第一引线组R1的栅极引线与所述第一引线组R1内靠近所述第三引线组R3的栅极引线间具有电压差。
所述第四引线组R4内的至少一条栅极引线上的电压与所述第一引线组R1内的栅极引线上的电压不同，且在相邻的所述第一引线组R1和所述第四引线组R4中，所述第四引线组R4内靠近所述第一引线组R1的栅极引线与所述第一引线组R1内靠近所述第四引线组R4的栅极引线间具有电压差；并在相邻的所述第三引线组R3和所述第四引线组R4内，所述第三引线组R3内靠近所述第四引线组R4的栅极引线与所述第四引线组R4内靠近所述第三引线组R3的栅极引线间具有电压差。
所述第三引线组R3包括相邻的第五栅极引线G5和所述第一栅极引线G1，所述第五栅极引线G5与所述第二栅极引线G2间具有电压差，且在相邻的所述第一引线组R1和所述第三引线组R3中，所述第五栅极引线G5靠近所述第一引线组R1。所述第四引线组R4包括相邻的第六栅极引线G6和所述第二栅极引线G2，所述第六栅极引线G6与所述第一栅极引线G1间具有电压差，且在相邻的所述第一引线组R1和所述第四引线组R4中，所述第六栅极引线G6靠近所述第一引线组R1。
相对应地，所述显示面板100还包括与所述第二引线组R2同层设置的多个第五引线组R5和多个第六引线组R6，每相邻的两个所述第二引线组R2之间设置有一个所述第五引线组R5和一个所述第六引线组R6，所述第五引线组R5和所述第六引线组R6均包括至少两个栅极引线，且所述第五引线组R5内每相邻的两个栅极引线间具有电压差，所述第六引线组R6内每相邻的两个栅极引线间具有电压差。
所述第五引线组R5内的至少一条栅极引线上的电压与所述第二引线组R2内的栅极引线上的电压不同，且在相邻的所述第二引线组R2和所述第五引线组R5中，所述第五引线组R5内靠近所述第二引线组R2的栅极引线与所述第二引线组R2内靠近所述第五引线组R5的栅极引线间具有电压差。
所述第六引线组R6内的至少一条栅极引线上的电压与所述第二引线组R2内的栅极引线上的电压不同，且在相邻的所述第二引线组R2和所述第六引线组R6中，所述第六引线组R6内靠近所述第二引线组R2的栅极引线与所述第二引线组R2内靠近所述第六引线组R6的栅极引线间具有电压差；并在相邻的所述第五引线组R5和所述第六引线组R6内，所述第五引线组R5内靠近所述第六引线组R6的栅极引线与所述第六引线组R6内靠近所述第五引线组R5的栅极引线间具有电压差。
所述第五引线组R5包括相邻的第七栅极引线G7和所述第一栅极引线G1，所述第六栅极引线G6与所述第二栅极引线G2间具有电压差，且在相邻的所述第二引线组R2和所述第五引线组R5中，所述第六栅极引线G6靠近所述第二引线组R2。所述第六引线组R6包括相邻的第八栅极引线G8和所述第二栅极引线G2，所述第八栅极引线G8与所述第一栅极引线G1间具有电压差，且在相邻的所述第二引线组R2和所述第六引线组R6中，所述第八栅极引线G8靠近所述第二引线组R2。
可选地，所述第五栅极引线G5上的电压与所述第六栅极引线G6上的电压相同，所述第七栅极引线G7上的电压与所述第八栅极引线G8上的电压相同，且所述第五栅极引线G5上的电压与所述第七栅极引线G7上的电压相同。如此只需在所述第三非显示区NA3内增加第三信号接入点GS3即可，避免增加过多的信号接入点，进而降低点灯测试的难度。
可以理解的，参照图6，所述第三引线组R3、所述第四引线组R4、所述第五引线组R5以及所述第六引线组R6均还包括与栅极引线电连接的连接走线。可选地，所述第三引线组R3包括相邻的第五连接走线C5和所述第一连接走线C1，所述第四引线组R4包括相邻的所述第二连接走线C2和第六连接走线C6，所述第五引线组R5包括相邻的所述第七连接走线C7和第三连接走线C3，所述第六引线组R6包括相邻的所述第四连接走线C4和第八连接走线C8。在沿所述第一方向X上，同一金属层上任意相邻的两个连接走线间具有电压差。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，请参照图1至图7，图7为本申请实施例提供的显示面板的又一种俯视结构示意图。与上述实施例不同的是，所述显示面板102还包括位于所述显示区AA的另一侧的第二非显示区NA2，所述第二非显示区NA2和所述第一非显示区NA1相对设置，所述第二非显示区NA2内设置有所述第一引线组R1和所述第二引线组R2，其中所述第一非显示区NA1的所述第一引线组R1与所述第二非显示区NA2的所述第一引线组R1对称设置，所述第一非显示区NA1的所述第二引线组R2与所述第二非显示区NA2的所述第二引线组R2对称设置。其他说明请参照上述实施例，在此不再赘述。
基于同一发明构思，本申请实施例还提供一种电子装置，所述电子装置包括前述实施例其中之一的显示面板。所述电子装置包括手机、平板、电视等电子显示产品。
根据上述实施例可知：
本申请提供一种显示面板和电子装置，该显示面板包括设置在衬底基板上的多个第一引线组和多个第二引线组，第一引线组和第二引线组位于不同层，第一引线组和第二引线组内均包括至少两条栅极引线，每条栅极引线与对应的一条栅极扫描线电连接，且第一引线组内每相邻的两条栅极引线间具有电压差，第二引线组内每相邻的两条栅极引线间也具有电压差，如此同一层相邻的栅极引线传输不同的信号，当同一层相邻的栅极引线之间发生短路时，由于是不同信号间的短路，使得短路后的栅极引线上的电压会有明显变化，进而可以通过点灯测试检测出来，有效减少漏检。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其包括显示区和位于显示区一侧的第一非显示区，所述显示面板还包括：
    衬底基板；
    多条栅极扫描线，设置在所述衬底基板上，并位于所述显示区内，每条所述栅极扫描线沿第一方向延伸，且多条所述栅极扫描线沿第二方向间隔排布；
    多个第一引线组，设置在所述衬底基板上，并位于所述第一非显示区内，每个所述第一引线组包括至少两条沿所述第一方向延伸的栅极引线，每条栅极引线与对应的一条栅极扫描线电连接，且每相邻的两条栅极引线间具有电压差；以及
    多个第二引线组，设置在所述衬底基板上，并位于所述第一非显示区内，每个所述第二引线组包括至少两条沿所述第一方向延伸的栅极引线，每条栅极引线与对应的一条栅极扫描线电连接，且每相邻的两条栅极引线间具有电压差；
    其中，所述第一引线组和所述第二引线组位于不同层，且所述第二引线组内的栅极引线在所述衬底基板上的正投影与所述第一引线组内的栅极引线在所述衬底基板上的正投影交替排布。
  2. 根据权利要求1所述的显示面板，其中，每个所述第一引线组还包括多条连接走线，在同一所述第一引线组内，每条连接走线分别与对应的一条栅极走线电连接，每相邻的两个连接走线间具有电压差；
    每个所述第二引线组还包括多条连接走线，在同一所述第二引线组内，每条连接走线分别与对应的一条栅极走线电连接，每相邻的两个连接走线间具有电压差；
    其中，所述第一引线组内的连接走线在所述衬底基板上的正投影与所述第二引线组内的连接走线在所述衬底基板上的正投影至少部分重叠。
  3. 根据权利要求2所述的显示面板，其中，所述第一引线组内的栅极引线的数量等于所述第二引线组内的栅极引线的数量，且所述第一引线组内的栅极引线上的电压与所述第二引线组内的对应的栅极引线上的电压相同。
  4. 根据权利要求3所述的显示面板，其中，所述第一引线组包括相邻的第一栅极引线和第二栅极引线，所述第二引线组包括相邻的第三栅极引线和第四栅极引线，所述第一栅极引线上的电压与所述第三栅极引线上的电压相同，所述第二栅极引线上的电压与所述第四栅极引线上的电压相同。
  5. 根据权利要求2所述的显示面板，其中，所述显示面板还包括与所述第一引线组同层设置的多个第三引线组和多个第四引线组，每相邻的两个所述第一引线组之间设置有一个所述第三引线组和一个所述第四引线组，所述第三引线组和所述第四引线组均包括至少两个栅极引线，且所述第三引线组内每相邻的两个栅极引线间具有电压差，所述第四引线组内每相邻的两个栅极引线间具有电压差；
    所述第三引线组内的至少一条栅极引线上的电压与所述第一引线组内的栅极引线上的电压不同，且在相邻的所述第一引线组和所述第三引线组中，所述第三引线组内靠近所述第一引线组的栅极引线与所述第一引线组内靠近所述第三引线组的栅极引线间具有电压差；
    所述第四引线组内的至少一条栅极引线上的电压与所述第一引线组内的栅极引线上的电压不同，且在相邻的所述第一引线组和所述第四引线组中，所述第四引线组内靠近所述第一引线组的栅极引线与所述第一引线组内靠近所述第四引线组的栅极引线间具有电压差；并在相邻的所述第三引线组和所述第四引线组内，所述第三引线组内靠近所述第四引线组的栅极引线与所述第四引线组内靠近所述第三引线组的栅极引线间具有电压差。
  6. 根据权利要求5所述的显示面板，其中，所述第一引线组包括相邻的第一栅极引线和第二栅极引线；所述第三引线组包括相邻的第五栅极引线和所述第一栅极引线，所述第五栅极引线与所述第二栅极引线间具有电压差，且在相邻的所述第一引线组和所述第三引线组中，所述第五栅极引线靠近所述第一引线组；
    所述第四引线组包括相邻的第六栅极引线和所述第二栅极引线，所述第六栅极引线与所述第一栅极引线间具有电压差，且在相邻的所述第一引线组和所述第四引线组中，所述第六栅极引线靠近所述第一引线组。
  7. 根据权利要求6所述的显示面板，其中，所述第五栅极引线上的电压与所述第六栅极引线上的电压相同。
  8. 根据权利要求1所述的显示面板，其中，所述显示面板还包括位于所述显示区的另一侧的第二非显示区，所述第二非显示区和所述第一非显示区相对设置，所述第二非显示区内设置有所述第一引线组和所述第二引线组，其中所述第一非显示区的所述第一引线组和所述第二引线组与奇数行的所述栅极扫描线电连接，所述第二非显示区的所述第一引线组和所述第二引线组与偶数行的所述栅极扫描线电连接。
  9. 根据权利要求1所述的显示面板，其中，所述显示面板还包括位于所述显示区的另一侧的第二非显示区，所述第二非显示区和所述第一非显示区相对设置，所述第二非显示区内设置有所述第一引线组和所述第二引线组，其中所述第一非显示区的所述第一引线组与所述第二非显示区的所述第一引线组对称设置，所述第一非显示区的所述第二引线组与所述第二非显示区的所述第二引线组对称设置。
  10. 根据权利要求1所述的显示面板，其中，所述第一引线组或所述第二引线组与所述栅极扫描线同层设置。
  11. 一种电子装置，其包括显示面板，所述显示面板包括显示区和位于显示区一侧的第一非显示区，所述显示面板还包括：
    衬底基板；
    多条栅极扫描线，设置在所述衬底基板上，并位于所述显示区内，每条所述栅极扫描线沿第一方向延伸，且多条所述栅极扫描线沿第二方向间隔排布；
    多个第一引线组，设置在所述衬底基板上，并位于所述第一非显示区内，每个所述第一引线组包括至少两条沿所述第一方向延伸的栅极引线，每条栅极引线与对应的一条栅极扫描线电连接，且每相邻的两条栅极引线间具有电压差；以及
    多个第二引线组，设置在所述衬底基板上，并位于所述第一非显示区内，每个所述第二引线组包括至少两条沿所述第一方向延伸的栅极引线，每条栅极引线与对应的一条栅极扫描线电连接，且每相邻的两条栅极引线间具有电压差；
    其中，所述第一引线组和所述第二引线组位于不同层，且所述第二引线组内的栅极引线在所述衬底基板上的正投影与所述第一引线组内的栅极引线在所述衬底基板上的正投影交替排布。
  12. 根据权利要求11所述的电子装置，其中，每个所述第一引线组还包括多条连接走线，在同一所述第一引线组内，每条连接走线分别与对应的一条栅极走线电连接，每相邻的两个连接走线间具有电压差；
    每个所述第二引线组还包括多条连接走线，在同一所述第二引线组内，每条连接走线分别与对应的一条栅极走线电连接，每相邻的两个连接走线间具有电压差；
    其中，所述第一引线组内的连接走线在所述衬底基板上的正投影与所述第二引线组内的连接走线在所述衬底基板上的正投影至少部分重叠。
  13. 根据权利要求12所述的电子装置，其中，所述第一引线组内的栅极引线的数量等于所述第二引线组内的栅极引线的数量，且所述第一引线组内的栅极引线上的电压与所述第二引线组内的对应的栅极引线上的电压相同。
  14. 根据权利要求13所述的电子装置，其中，所述第一引线组包括相邻的第一栅极引线和第二栅极引线，所述第二引线组包括相邻的第三栅极引线和第四栅极引线，所述第一栅极引线上的电压与所述第三栅极引线上的电压相同，所述第二栅极引线上的电压与所述第四栅极引线上的电压相同。
  15. 根据权利要求12所述的电子装置，其中，所述显示面板还包括与所述第一引线组同层设置的多个第三引线组和多个第四引线组，每相邻的两个所述第一引线组之间设置有一个所述第三引线组和一个所述第四引线组，所述第三引线组和所述第四引线组均包括至少两个栅极引线，且所述第三引线组内每相邻的两个栅极引线间具有电压差，所述第四引线组内每相邻的两个栅极引线间具有电压差；
    所述第三引线组内的至少一条栅极引线上的电压与所述第一引线组内的栅极引线上的电压不同，且在相邻的所述第一引线组和所述第三引线组中，所述第三引线组内靠近所述第一引线组的栅极引线与所述第一引线组内靠近所述第三引线组的栅极引线间具有电压差；
    所述第四引线组内的至少一条栅极引线上的电压与所述第一引线组内的栅极引线上的电压不同，且在相邻的所述第一引线组和所述第四引线组中，所述第四引线组内靠近所述第一引线组的栅极引线与所述第一引线组内靠近所述第四引线组的栅极引线间具有电压差；并在相邻的所述第三引线组和所述第四引线组内，所述第三引线组内靠近所述第四引线组的栅极引线与所述第四引线组内靠近所述第三引线组的栅极引线间具有电压差。
  16. 根据权利要求15所述的电子装置，其中，所述第一引线组包括相邻的第一栅极引线和第二栅极引线；所述第三引线组包括相邻的第五栅极引线和所述第一栅极引线，所述第五栅极引线与所述第二栅极引线间具有电压差，且在相邻的所述第一引线组和所述第三引线组中，所述第五栅极引线靠近所述第一引线组；
    所述第四引线组包括相邻的第六栅极引线和所述第二栅极引线，所述第六栅极引线与所述第一栅极引线间具有电压差，且在相邻的所述第一引线组和所述第四引线组中，所述第六栅极引线靠近所述第一引线组。
  17. 根据权利要求16所述的电子装置，其中，所述第五栅极引线上的电压与所述第六栅极引线上的电压相同。
  18. 根据权利要求11所述的电子装置，其中，所述显示面板还包括位于所述显示区的另一侧的第二非显示区，所述第二非显示区和所述第一非显示区相对设置，所述第二非显示区内设置有所述第一引线组和所述第二引线组，其中所述第一非显示区的所述第一引线组和所述第二引线组与奇数行的所述栅极扫描线电连接，所述第二非显示区的所述第一引线组和所述第二引线组与偶数行的所述栅极扫描线电连接。
  19. 根据权利要求11所述的电子装置，其中，所述显示面板还包括位于所述显示区的另一侧的第二非显示区，所述第二非显示区和所述第一非显示区相对设置，所述第二非显示区内设置有所述第一引线组和所述第二引线组，其中所述第一非显示区的所述第一引线组与所述第二非显示区的所述第一引线组对称设置，所述第一非显示区的所述第二引线组与所述第二非显示区的所述第二引线组对称设置。
  20. 根据权利要求11所述的电子装置，其中，所述第一引线组或所述第二引线组与所述栅极扫描线同层设置。
PCT/CN2023/103882 2022-09-21 2023-06-29 显示面板和电子装置 Ceased WO2024060765A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/558,177 US20250089366A1 (en) 2022-09-21 2023-06-29 Display panel and electronic device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211152835.XA CN115542622B (zh) 2022-09-21 2022-09-21 显示面板
CN202211152835.X 2022-09-21

Publications (1)

Publication Number Publication Date
WO2024060765A1 true WO2024060765A1 (zh) 2024-03-28

Family

ID=84728202

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/103882 Ceased WO2024060765A1 (zh) 2022-09-21 2023-06-29 显示面板和电子装置

Country Status (3)

Country Link
US (1) US20250089366A1 (zh)
CN (1) CN115542622B (zh)
WO (1) WO2024060765A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115542622B (zh) * 2022-09-21 2026-02-06 武汉华星光电技术有限公司 显示面板
CN117042525A (zh) * 2023-08-22 2023-11-10 京东方科技集团股份有限公司 显示基板和显示装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1800925A (zh) * 2004-12-27 2006-07-12 东芝松下显示技术有限公司 显示装置
US20110221719A1 (en) * 2010-03-10 2011-09-15 Samsung Mobile Display Co., Ltd. Liquid crystal display
CN103106858A (zh) * 2012-11-16 2013-05-15 友达光电股份有限公司 显示面板及其检测方法
CN202975551U (zh) * 2012-12-26 2013-06-05 北京京东方光电科技有限公司 一种阵列基板及显示装置
CN104218042A (zh) * 2014-09-02 2014-12-17 合肥鑫晟光电科技有限公司 一种阵列基板及其制备方法、显示装置
CN105427748A (zh) * 2016-01-04 2016-03-23 京东方科技集团股份有限公司 一种阵列基板、显示面板、显示装置及显示方法
CN106782249A (zh) * 2017-01-13 2017-05-31 京东方科技集团股份有限公司 一种显示面板、其电学检测方法及显示装置
CN111863903A (zh) * 2020-07-23 2020-10-30 上海天马有机发光显示技术有限公司 显示面板及其制作方法、显示装置
CN115542622A (zh) * 2022-09-21 2022-12-30 武汉华星光电技术有限公司 显示面板

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI325507B (en) * 2006-02-21 2010-06-01 Au Optronics Corp Electronic device with uniform-resistance fan-out blocks
TWI446314B (zh) * 2010-08-19 2014-07-21 友達光電股份有限公司 畫素陣列基板、導電結構以及顯示面板
CN206696561U (zh) * 2017-05-22 2017-12-01 信利半导体有限公司 一种窄边框阵列基板检测电路
KR102729328B1 (ko) * 2020-07-31 2024-11-11 엘지디스플레이 주식회사 표시 장치용 어레이 기판, 이를 포함하는 표시 장치, 및 그 제조 방법
CN114724485B (zh) * 2022-04-27 2025-07-25 京东方科技集团股份有限公司 显示面板、显示装置及其测试系统

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1800925A (zh) * 2004-12-27 2006-07-12 东芝松下显示技术有限公司 显示装置
US20110221719A1 (en) * 2010-03-10 2011-09-15 Samsung Mobile Display Co., Ltd. Liquid crystal display
CN103106858A (zh) * 2012-11-16 2013-05-15 友达光电股份有限公司 显示面板及其检测方法
CN202975551U (zh) * 2012-12-26 2013-06-05 北京京东方光电科技有限公司 一种阵列基板及显示装置
CN104218042A (zh) * 2014-09-02 2014-12-17 合肥鑫晟光电科技有限公司 一种阵列基板及其制备方法、显示装置
CN105427748A (zh) * 2016-01-04 2016-03-23 京东方科技集团股份有限公司 一种阵列基板、显示面板、显示装置及显示方法
CN106782249A (zh) * 2017-01-13 2017-05-31 京东方科技集团股份有限公司 一种显示面板、其电学检测方法及显示装置
CN111863903A (zh) * 2020-07-23 2020-10-30 上海天马有机发光显示技术有限公司 显示面板及其制作方法、显示装置
CN115542622A (zh) * 2022-09-21 2022-12-30 武汉华星光电技术有限公司 显示面板

Also Published As

Publication number Publication date
CN115542622B (zh) 2026-02-06
CN115542622A (zh) 2022-12-30
US20250089366A1 (en) 2025-03-13

Similar Documents

Publication Publication Date Title
US11126050B2 (en) Pixel array substrate
WO2024060765A1 (zh) 显示面板和电子装置
CN105511688A (zh) 一种阵列基板、显示器以及电子设备
CN107966862B (zh) 显示器及其显示面板、显示器的制作方法
CN106526995B (zh) 一种阵列基板和显示面板
CN103217843A (zh) 阵列基板及其制造方法和液晶面板
CN109658855A (zh) 阵列基板、显示模组及其测试方法、显示面板
CN106444182A (zh) 一种阵列基板和显示面板
CN111682027A (zh) 阵列基板、显示模组及显示装置
CN111430373A (zh) 一种阵列基板、显示面板和显示装置
WO2020232916A1 (zh) 一种阵列基板及显示面板
CN114446255B (zh) 显示面板及显示装置
TW201411254A (zh) 顯示面板
WO2023231104A1 (zh) 显示面板及显示终端
WO2023221214A1 (zh) 触控显示面板及显示装置
CN101799605A (zh) 像素阵列
WO2023216305A1 (zh) 阵列基板及显示面板
WO2023035318A1 (zh) 阵列基板及电子装置
WO2021232901A1 (zh) 显示面板和显示装置
WO2020000549A1 (zh) 一种阵列基板、显示面板及显示设备
JP4725358B2 (ja) カラー液晶表示パネル
CN118092029A (zh) 一种显示面板及显示装置
CN107808864A (zh) 扇出线结构及其制造方法
WO2021223290A1 (zh) 显示面板及显示装置
WO2018161393A1 (zh) 阵列基板测试电路及其制作方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 18558177

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23867060

Country of ref document: EP

Kind code of ref document: A1

WWP Wipo information: published in national office

Ref document number: 18558177

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 23867060

Country of ref document: EP

Kind code of ref document: A1