WO2023035318A1 - 阵列基板及电子装置 - Google Patents

阵列基板及电子装置 Download PDF

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Publication number
WO2023035318A1
WO2023035318A1 PCT/CN2021/119340 CN2021119340W WO2023035318A1 WO 2023035318 A1 WO2023035318 A1 WO 2023035318A1 CN 2021119340 W CN2021119340 W CN 2021119340W WO 2023035318 A1 WO2023035318 A1 WO 2023035318A1
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WIPO (PCT)
Prior art keywords
substrate
via hole
electrode
orthographic projection
insulating layer
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PCT/CN2021/119340
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English (en)
French (fr)
Inventor
唐维
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武汉华星光电技术有限公司
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Priority to US17/607,875 priority Critical patent/US11990482B2/en
Publication of WO2023035318A1 publication Critical patent/WO2023035318A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate and an electronic device.
  • FIG. 1a and FIG. 1b are structural schematic diagrams of an existing array substrate, including a barrier layer 11, a gate insulating layer 12, a common signal line 13, an interlayer dielectric layer 14,
  • the conductive electrode 15, the flat layer 16, the common electrode 17, the passivation layer 18 and the pixel electrode 19, the common signal line 13 is connected to the conductive electrode 15 through the first via hole 141 arranged on the interlayer dielectric layer 14, and the common electrode 17
  • the conductive electrode 15 is connected to the conductive electrode 15 through the second via hole 161 provided on the flat layer 16.
  • the second via hole 161 is set on the first via hole 141, and exposes the first via hole 141 and is formed in the first via hole 141.
  • the junction a between the sidewall of the first via hole 141 and the surface of the interlayer dielectric layer 14 will form a step angle with a certain angle, and electrostatic discharge during the subsequent process may cause the step angle at the junction a
  • the upper conductive electrode 15 melts, and the melted conductive electrode 15 presses against the common electrode 17 and the passivation layer 18 above the common electrode 17, and breaks through the passivation layer 18, resulting in the formation of the passivation layer 18 at the joint a cracks as shown in Figure 1b.
  • the common electrode 17 located below the passivation layer 18 is separated out through the cracks of the passivation layer 18, and is short-circuited with the pixel electrode 19 located above the passivation layer 18, resulting in a group of dark spots or dark spots in the array substrate and electronic devices during the lighting test. Abnormal display of horizontal lines etc.
  • the existing array substrates and electronic devices have the problem of short circuit between the common electrode and the pixel electrode. Therefore, it is necessary to provide an array substrate and an electronic device to improve this defect.
  • Embodiments of the present application provide an array substrate and an electronic device, which are used to solve the problem of short circuit between a common electrode and a pixel electrode existing in the existing array substrate and electronic device.
  • An embodiment of the present application provides an array substrate, including:
  • the first metal layer includes a plurality of common signal lines
  • first insulating layer covering the first metal layer, and a plurality of first via holes are provided on the first insulating layer;
  • the second metal layer is disposed on the side of the first insulating layer away from the first metal layer, the second metal layer includes a plurality of conductive electrodes, and the conductive electrodes communicate with the first via hole through the first via hole.
  • the second insulating layer is disposed on a side of the first insulating layer away from the first metal layer and covers the second metal layer, and the second insulating layer is provided with a plurality of second via holes;
  • the first electrode layer is disposed on the side of the second insulating layer away from the second metal layer, the first electrode layer includes a first electrode, and the first electrode communicates with the second via hole through the second via hole. conductive electrode connections;
  • a second electrode layer disposed on a side of the first electrode layer away from the second insulating layer, the second electrode layer comprising a second electrode
  • the orthographic projection of at least one of the second via hole and the second electrode on the substrate is staggered from the orthographic projection of the first via hole on the substrate.
  • the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate are completely staggered, and the first via hole is located on the substrate
  • the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second electrode on the substrate.
  • the orthographic projection of the second via hole on the substrate and the orthographic projection of the second electrode on the substrate are completely staggered or at least partially overlapped.
  • the conductive electrode includes:
  • the body part is formed in the first via hole and connected to the common signal line, the second insulating layer covers the body part and fills the first via hole;
  • the extension part is formed on a side of the first insulating layer away from the first metal layer, the second via hole exposes the extension part, and the first The electrodes are connected to the extension part.
  • the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate are completely staggered, and the first via hole is located on the substrate
  • the orthographic projection on the substrate is completely staggered from the orthographic projection of the second electrode on the substrate.
  • the orthographic projection of the second via hole on the substrate and the orthographic projection of the second electrode on the substrate are completely staggered or at least partially overlapped.
  • the conductive electrode includes:
  • the body part is formed in the first via hole and connected to the common signal line, the second insulating layer covers the body part and fills the first via hole;
  • the extension part is formed on a side of the first insulating layer away from the first metal layer, the second via hole exposes the extension part, and the first electrode is connected to the extension part .
  • the orthographic projection of the first via hole on the substrate at least partially overlaps the orthographic projection of the second via hole on the substrate, and the first via hole on the substrate
  • the orthographic projection on the substrate is completely staggered from the orthographic projection of the second electrode on the substrate.
  • the orthographic projection of the second via hole on the substrate and the orthographic projection of the second electrode on the substrate are completely staggered or partially overlapped.
  • the array substrate includes a first area, and the second electrode array is arranged in the first area;
  • the second metal layer includes a common voltage signal line
  • the common voltage signal line surrounds the outer periphery of the first region, and connects with the common signal line through a third via hole penetrating through the first insulating layer. connect.
  • the array substrate further includes a plurality of gate signal lines and a plurality of data signal lines;
  • the common signal line is arranged on the same layer as the gate signal line, and the common voltage signal line is arranged on the same layer as the data signal line.
  • the embodiment of the present application also provides an electronic device, the electronic device includes a display panel, the display panel includes an array substrate, and the array substrate includes:
  • the first metal layer includes a plurality of common signal lines
  • first insulating layer covering the first metal layer, and a plurality of first via holes are provided on the first insulating layer;
  • the second metal layer is disposed on the side of the first insulating layer away from the first metal layer, the second metal layer includes a plurality of conductive electrodes, and the conductive electrodes communicate with the first via hole through the first via hole.
  • the second insulating layer is disposed on a side of the first insulating layer away from the first metal layer and covers the second metal layer, and the second insulating layer is provided with a plurality of second via holes;
  • the first electrode layer is disposed on the side of the second insulating layer away from the second metal layer, the first electrode layer includes a first electrode, and the first electrode communicates with the second via hole through the second via hole. conductive electrode connections;
  • a second electrode layer disposed on a side of the first electrode layer away from the second insulating layer, the second electrode layer comprising a second electrode
  • the orthographic projection of at least one of the second via hole and the second electrode on the substrate is staggered from the orthographic projection of the first via hole on the substrate.
  • the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate are completely staggered, and the first via hole is located on the substrate
  • the orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second electrode on the substrate.
  • the orthographic projection of the second via hole on the substrate and the orthographic projection of the second electrode on the substrate are completely staggered or at least partially overlapped.
  • the conductive electrode includes:
  • the body part is formed in the first via hole and connected to the common signal line, the second insulating layer covers the body part and fills the first via hole;
  • the extension part is formed on a side of the first insulating layer away from the first metal layer, the second via hole exposes the extension part, and the first The electrodes are connected to the extension part.
  • the orthographic projection of the first via hole on the substrate and the orthographic projection of the second via hole on the substrate are completely staggered, and the first via hole is located on the substrate
  • the orthographic projection on the substrate is completely staggered from the orthographic projection of the second electrode on the substrate.
  • the orthographic projection of the second via hole on the substrate and the orthographic projection of the second electrode on the substrate are completely staggered or at least partially overlapped.
  • the conductive electrode includes:
  • the body part is formed in the first via hole and connected to the common signal line, the second insulating layer covers the body part and fills the first via hole;
  • the extension part is formed on a side of the first insulating layer away from the first metal layer, the second via hole exposes the extension part, and the first The electrodes are connected to the extension part.
  • the orthographic projection of the first via hole on the substrate at least partially overlaps the orthographic projection of the second via hole on the substrate, and the first via hole on the substrate
  • the orthographic projection on the substrate is completely staggered from the orthographic projection of the second electrode on the substrate.
  • the orthographic projection of the second via hole on the substrate and the orthographic projection of the second electrode on the substrate are completely staggered or partially overlapped.
  • the embodiments of the present application provide an array substrate and an electronic device, the electronic device includes a display panel, the display panel includes an array substrate, and the array substrate includes successively stacked substrates, a first Metal layer, first insulating layer, second metal layer, second insulating layer, first electrode layer and second electrode layer, the first metal layer includes a plurality of common signal lines, the first insulating layer covers the first metal layer , the first insulating layer is provided with a plurality of first via holes, the second metal layer is arranged on the side of the first insulating layer away from the first metal layer, and the second metal layer includes a plurality of conductive An electrode, the conductive electrode is connected to the common signal line through the first via hole, and the second insulating layer is arranged on the side of the first insulating layer away from the first metal layer and covers the second metal layer.
  • the second insulating layer is provided with a plurality of second via holes
  • the first electrode layer is arranged on the side of the second insulating layer away from the second metal layer
  • the first electrode layer includes a first An electrode
  • the first electrode is connected to the conductive electrode through the second via hole
  • the second electrode layer is arranged on the side of the first electrode layer away from the second insulating layer
  • the second electrode layer Including a second electrode, the orthographic projection of at least one of the second via hole and the second electrode on the substrate is staggered from the orthographic projection of the first via hole on the substrate, so as to avoid
  • the insulating layer between the first electrode layer and the second electrode layer is cracked or the second electrode does not exist above the first electrode separated out through the crack between the first electrode layer and the second electrode layer, thereby avoiding the contact between the first electrode and the second electrode layer.
  • the second electrode is shorted.
  • Figure 1a is a schematic structural view of an existing array substrate
  • Figure 1b is a schematic structural view of an existing array substrate
  • FIG. 2 is a schematic plan view of the array substrate provided by the embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional view along the A-A direction of the first array substrate provided in the embodiment of the present application;
  • FIG. 4 is a partially enlarged schematic diagram of the first array substrate provided in the embodiment of the present application.
  • FIG. 5 is a partially enlarged schematic diagram of a second array substrate provided in an embodiment of the present application.
  • FIG. 6 is a partially enlarged schematic diagram of a third array substrate provided in an embodiment of the present application.
  • FIG. 7 is a partially enlarged schematic diagram of a fourth array substrate provided in an embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional view along the A-A direction of the fourth array substrate provided by the embodiment of the present application.
  • FIG. 9 is a partially enlarged schematic view of a fifth type of array substrate provided in an embodiment of the present application.
  • Embodiments of the present application provide an array substrate and an electronic device, the electronic device includes a display panel, and the display panel includes an array substrate.
  • the electronic device can be a vehicle-mounted display terminal, such as a vehicle-mounted display, a driving recorder, etc.
  • the electronic device can also be a mobile terminal, such as a smart phone, a tablet computer, a notebook computer, etc., or a wearable terminal, such as a smart watch, Smart bracelets, smart glasses, augmented reality equipment, etc.
  • the electronic device can also be a fixed terminal, such as a desktop computer, a TV, etc., or a vehicle-mounted display terminal, such as a vehicle-mounted display or a driving recorder.
  • FIG. 2 is a schematic plan view of the array substrate provided by the embodiment of the present application.
  • the array substrate 200 includes a substrate 20 and sub-pixel units P arrayed on the substrate 20 in multiple rows and columns. , each sub-pixel unit P correspondingly has a thin film transistor T and a second electrode 310, and the second electrode 310 is a pixel electrode.
  • the array substrate 200 also has a plurality of gate signal lines 253 extending along the first direction x and data signal lines 272 extending along the second direction y. The gate is connected, and the data signal line 272 is connected to the drains of the thin film transistors T of a corresponding column of pixel units P.
  • FIG. 3 is a schematic cross-sectional view of the first array substrate provided in the embodiment of the present application along the A-A direction.
  • the array substrate 200 includes a substrate 20 and a light-shielding layer 21 and a barrier layer stacked on the substrate 20 in sequence. 22. Active layer 23, gate insulating layer 24.
  • the light-shielding layer 21 has a plurality of patterned light-shielding patterns 211 , and the material of the light-shielding layer 21 includes any one of metal materials or non-metallic materials that are opaque or light-absorbing.
  • the light-shielding pattern 211 is arranged in alignment with the active layer 23, and the light-shielding pattern 211 is used to shield the active layer 23, preventing ambient light or internal light from irradiating the active layer 23 through the side of the substrate 20, resulting in a decrease in the electrical performance of the active layer 23, Thus, the electrical performance of the active layer 23 is ensured.
  • the barrier layer 22 is disposed on the substrate 20 and covers the light-shielding layer 21 for preventing outside water vapor or oxygen from corroding thin film transistors and other devices in the array substrate 200 through one side of the substrate 20 .
  • the active layer 23 is disposed on the side of the barrier layer 22 facing away from the substrate 20 , the active layer 23 has a channel portion 231 and a conductive portion 232 connected to an opposite end of the channel portion 231 .
  • the gate insulating layer 24 is disposed on a side of the barrier layer 22 away from the substrate 20 and covers the active layer 23 .
  • the array substrate 200 further includes a first metal layer 25, a first insulating layer 26, a second metal layer 27, a second insulating layer 28, a first electrode layer 29, a third The insulating layer 30 and the second electrode layer 31 .
  • the first metal layer 25 includes a plurality of common signal lines 250, and each common signal line 250 includes a main body portion 251 and a plurality of connecting portions 252.
  • the main body portion 251 is elongated and extends along the first Extending in one direction x, the main body portions 251 of the plurality of common signal lines 250 are arranged at intervals in the second direction y.
  • the connection part 252 is a block electrode, and a plurality of connection parts 252 are respectively connected to the same side of the body part 251 and arranged at intervals in the first direction x.
  • the gate signal line 253, the gate 254 and the common signal line 250 are arranged on the same layer, that is, the gate signal line 253 and the common signal line 250 are both arranged on the first metal layer 25, and can pass through the same layer. Road process preparation is formed. Both the common signal line 250 and the gate signal line 253 extend along the first direction x and are spaced apart along the second direction y. In practical applications, the gate signal lines 253 and the gates 254 are not limited to be disposed on the first metal layer 25, and may also be disposed in other metal layers on the side of the first metal layer 25 that is close to or far from the substrate 20, which is not described here. limit.
  • the first insulating layer 26 is disposed on a side of the gate insulating layer 24 away from the substrate 20 and covers the first metal layer 25 .
  • the first insulating layer 26 is an interlayer dielectric layer (interlayer dielectric layer, ILD), the first insulating layer 26 is composed of a silicon oxide layer and a silicon nitride layer stacked. In practical applications, the first insulating layer 26 may also be a single-layer or multi-layer structure formed of any one of silicon nitride or silicon oxide or other insulating materials.
  • the first insulating layer 26 is provided with a plurality of first via holes 261, the first via holes 261 penetrate the first insulating layer 26 in the third direction z, and expose the connection of the common signal line 250 at the bottom of the first insulating layer 26 Section 252.
  • the second metal layer 27 is disposed on a side of the first insulating layer 26 away from the first metal layer 25 .
  • the second metal layer 27 includes a plurality of conductive electrodes 271 , and the conductive electrodes 271 are connected to the common signal line 250 through the first via holes 261 .
  • the conductive electrode 271 is a block electrode, and the orthographic projection area of the conductive electrode 271 on the substrate 20 is larger than the orthographic projection area of the first via hole 261 on the substrate 20, and the conductive electrode 271 connects with the common signal line through the first via hole 261.
  • the connection part 252 of the 250 is connected to receive the common voltage signal transmitted by the common signal line 250 .
  • the data signal line 272, the source electrode 273, and the drain electrode 274 can be arranged on the same layer as the conductive electrode 271, that is, the data signal line 272, the source electrode 273, the drain electrode 274, and the conductive electrode 271 are all arranged on the first layer.
  • the conductive electrode 271 can be formed through the same process as the data signal line 272 , the source electrode 273 and the drain electrode 274 .
  • the data signal line 272, the source electrode 273 and the drain electrode 274 are not limited to the second metal layer 27, and can also be arranged in other metal layers on the side of the second metal layer 27 close to or away from the substrate 20. There are no restrictions.
  • the second insulating layer 28 is a flat layer.
  • the second insulating layer 28 is disposed on the side of the first insulating layer 26 away from the first metal layer 25 .
  • the second insulating layer 28 covers the second metal layer 27 .
  • a plurality of second via holes 281 are disposed on the second insulating layer 28 , and the second via holes 281 penetrate the second insulating layer 28 in the third direction z and expose the conductive electrodes 271 at the bottom of the second insulating layer 28 .
  • a plurality of fourth via holes 282 are also disposed on the second insulating layer 28 , and the fourth via holes 282 penetrate the second insulating layer 28 in the third direction z and expose the source electrode 273 at the bottom of the second insulating layer 28 .
  • the first electrode layer 29 is disposed on a side of the second insulating layer 28 away from the second metal layer 27 , and the first electrode layer 29 includes a first electrode 291 .
  • the first electrode 291 is a common electrode, and the first electrode 291 can be tiled on the entire surface of the second insulating layer 28, and connected to the conductive electrode 271 through the second via hole 281 on the second insulating layer 28, so as to receive The common voltage signal transmitted by the signal line 250 .
  • a fifth via hole 292 is also disposed on the first electrode layer 29 , and the fifth via hole 292 is sleeved on the fourth via hole 282 to expose the source electrode 273 .
  • the third insulating layer 30 is a passivation layer (passivation layer, PV), the third insulating layer 30 is disposed on the side of the first electrode layer 29 facing away from the second insulating layer 28, and covers the first electrode layer 29, and the third insulating layer 30 also fills the fourth via hole 282 and The fifth via hole 292 .
  • a plurality of sixth via holes 301 are provided on the third insulating layer 30, and the sixth via holes 301 are sleeved on the fifth via hole 292 and the fourth via hole 282, and penetrate the third insulating layer in the third direction z. layer 30 to expose the source electrode 273 covered by the third insulating layer 30 .
  • the second electrode layer 31 is disposed on a side of the first electrode layer 29 away from the second insulating layer 28 .
  • the second electrode layer 31 is disposed on the third insulating layer 30 .
  • the second electrode layer 31 includes a plurality of patterned second electrodes 310, the second electrodes 310 are pixel electrodes, and the second electrodes 310 are connected to the source electrode 273 through the sixth via hole 301 to pass the source electrode 273 and the data signal
  • the wire 272 charges the second electrode 310 and forms an electric field with the first electrode 291 to drive the liquid crystal in the display panel to deflect.
  • the array substrate 200 further includes a first area A1 and a second area A2 surrounding the first area A1, the first area A1 is a display area, and the sub-pixels The units P are all arranged in the first area A1, and the second area A2 is a non-display area.
  • the array substrate 200 further includes a common voltage signal line 275 disposed on the outer periphery of the first area A1 and surrounding the first area A1 .
  • the common voltage signal line 275 is disposed on the second metal layer 27 for transmitting the common voltage signal required by the first electrode 291 .
  • the first insulating layer 26 is also provided with a plurality of third via holes 262 penetrating through the first insulating layer 26 in the third direction z, and the third via holes 262 are also divided into opposite sides of the first area A1.
  • the opposite ends of the signal line 250 are respectively connected to the common voltage signal line 275 through the third via hole 262 , so that the common voltage signal can be transmitted to the first electrode 291 quickly and uniformly.
  • the second insulating layer 28 is further provided with a plurality of seventh via holes 283 penetrating through the second insulating layer 28 in the third direction z, and the seventh via holes 283 expose the common voltage signal line 275 .
  • a plurality of seventh via holes 283 are disposed on the outer periphery of the first area A1, and the first electrode 293 can pass through the seventh via holes 283 and the common voltage signal line 275, so that the common voltage signal can be further quickly and uniformly transmitted to the second An electrode 291, so as to improve the problem of display unevenness existing in medium and large size display panels.
  • the orthographic projection of at least one of the second via hole 281 and the second electrode 310 on the substrate 20 is staggered from the orthographic projection of the first via hole 261 on the substrate 20, so as to avoid
  • the third insulating layer 30 between the first electrode layer 29 and the second electrode layer 31 is cracked; or, even if the third insulating layer between the first electrode layer 29 and the second electrode layer 31 cracks, through the crack
  • the orthographic projection of the first via hole 261 on the substrate 20 is completely staggered from the orthographic projection of the second via hole 281 on the substrate 20 .
  • the conductive electrode 271 includes a body portion 271 a and an extension portion 271 b.
  • the body portion 271 a is formed in the first via hole 261 and distributed on the bottom and the inner wall of the first via hole 261 .
  • the extension portion 271b is connected to the main body portion 271a, and the extension portion 271b is formed on a side of the first insulating layer 26 away from the first metal layer 25 . Since the orthographic projection of the second via hole 281 on the substrate 20 does not overlap with the orthographic projection of the first via hole 261 on the substrate 20, the second insulating layer 28 can cover the body portion 271a and fill the The recessed area formed by the first via hole 261 .
  • the second insulating layer 28 can also cover the extension portion 271b and fill the first via hole 261.
  • the second via hole 281 on the second insulating layer 28 exposes part of the extension portion 271b, so that the first electrode 291 can pass through
  • the second via hole 281 is connected to the extension portion 271b.
  • the thickness of the second insulating layer 28 is 2.5 microns. In practical applications, the thickness of the second insulating layer 28 is not limited to 2.5 microns, but can also be 2 microns, 2.3 microns, 2.7 microns or 3 microns.
  • filling the recessed area formed by the first via hole 261 with the second insulating layer 28 can make the first electrode layer 29, the third insulating layer 30 and the first electrode layer 29 formed on the second insulating layer 28 subsequently formed
  • the area corresponding to a via hole 261 can obtain a flat surface, avoiding direct contact between the first electrode layer 29 and the third insulating layer 30 and the step angle of the first insulating layer 26 at the first via hole 261, thus reducing the Due to the extrusion of the first electrode layer 29 and the third insulating layer 30 caused by the molten conductive electrode 271 due to electrostatic discharge, the risk of cracks in the third insulating layer 30 is reduced, thereby effectively preventing the first electrode 291 from contacting the second insulating layer 30.
  • the electrodes 310 are shorted.
  • the orthographic projection of the first via hole 261 on the substrate 20 at least partially overlaps the orthographic projection of the second electrode 310 on the substrate 20 .
  • FIG. 4 is a partially enlarged schematic diagram of the first type of array substrate provided in the embodiment of the present application, and the orthographic projection of the first via hole 261 on the substrate 20
  • the orthographic projection of the second via hole 281 on the substrate 20 overlaps, and the orthographic projection of the first via hole 261 on the substrate 20 partially overlaps the orthographic projection of the second electrode 310 on the substrate 20 .
  • the orthographic projection of the second via hole 281 on the substrate 20 partially overlaps the orthographic projection of the second electrode 310 on the substrate 20 .
  • the orthographic projection of the second electrode 310 on the substrate 20 may also completely cover the orthographic projection of the second via hole 281 on the substrate 20 .
  • the orthographic projection of the first via hole 261 on the substrate 20 is not different from that of the second via hole 261 .
  • the orthographic projections of the holes 281 on the substrate 20 overlap, the orthographic projections of the second electrode 310 on the substrate 20 completely cover the orthographic projections of the first via holes 261 on the substrate 20, and
  • the orthographic projection of the second electrode 310 on the substrate 20 also completely covers the orthographic projection of the second via hole 281 on the substrate 20 .
  • the orthographic projection of the second via hole 281 on the substrate 20 may partially overlap with the orthographic projection of the second electrode 310 on the substrate 20 .
  • the orthographic projection of the first via hole 261 on the substrate 20 is not the same as that of the second via hole 261 .
  • the orthographic projections of the holes 281 on the substrate 20 overlap, and the orthographic projections of the first via hole 261 on the substrate 20 and the orthographic projections of the second electrode 310 on the substrate 20 are completely staggered. They do not overlap, and the orthographic projection of the second via hole 281 on the substrate 20 is completely staggered from the orthographic projection of the second electrode 310 on the substrate 20 .
  • the orthographic projection of the second electrode 310 on the substrate 20 may partially overlap with the orthographic projection of the second via hole 281 on the substrate 20, or completely cover the second via hole 281 in the third direction. Orthographic projection on z.
  • the formation of the first via hole 261 by the second insulating layer 28 can be used.
  • the recessed area is filled, so that each film layer above the first via hole 261 has a flat surface, so even if the second electrode 310 is not provided above the first via hole 261 and the second via hole 281, or a part of the second electrode 310 is provided.
  • the electrode 310 or completely covered by the second electrode 310 , will not cause the problem of short circuit between the first electrode 291 and the second electrode 310 .
  • the orthographic projection of the second electrode 310 is partially overlapped or completely covered with the orthographic projection of the first via hole 261 and/or the second via hole 281, it will not be caused by the staggered setting of the first via hole 261 and the second via hole 281. As a result, the area of the second electrode 310 is reduced, thereby ensuring the aperture ratio of each sub-pixel in the array substrate 200 .
  • the orthographic projection of the first via hole 261 on the substrate at least partially overlaps the orthographic projection of the second via hole 281 on the substrate, and the first via hole is located on the substrate.
  • the orthographic projection on the substrate and the orthographic projection of the second electrode on the substrate are completely staggered.
  • FIG. 7 is a partially enlarged schematic view of the fourth array substrate provided by the embodiment of the present application.
  • the orthographic projections on the substrate 20 are completely staggered, and the two do not overlap.
  • the orthographic projections of the second electrode 310 on the substrate 20 and the orthographic projections of the second via hole 281 on the substrate 20 are also completely staggered. set up.
  • the first via hole 261 can be filled with the second insulating layer 28 , thereby reducing the risk of cracks in the third insulating layer 30 above the first via hole 261 and avoiding the short circuit between the first electrode 291 and the second electrode 310 .
  • Figure 8 is a schematic cross-sectional view of the fourth type of array substrate provided in the embodiment of the present application along the A-A direction, the second via hole 281 is sleeved on the first via hole 261, and the second via hole 281
  • the orthographic projection in the third direction z completely covers the orthographic projection of the first via hole 261 in the third direction z.
  • the occupation of the first via hole 261 and the second via hole 281 can be reduced. of the plane area.
  • FIG. 9 is a partially enlarged schematic view of the fifth array substrate provided in the embodiment of the present application.
  • causing the second electrode 310 is compressed so that the orthographic projection of the second electrode 310 on the substrate 20 partially overlaps the orthographic projection of the second via hole 281 on the substrate 20 , and the second via hole 281 on the substrate 20
  • the orthographic projection on the substrate 20 and the orthographic projection of the first via hole 261 on the substrate 20 are completely staggered. In this way, the short circuit between the first electrode 291 and the second electrode 310 can be avoided, and the area of the second electrode 310 can be prevented from being compressed by the first via hole 261 and the second via hole 281 .
  • the embodiments of the present application provide an array substrate and an electronic device, the electronic device includes a display panel, the display panel includes an array substrate, and the array substrate includes a sequentially stacked substrate, a first Metal layer, first insulating layer, second metal layer, second insulating layer, first electrode layer and second electrode layer, the first metal layer includes a plurality of common signal lines, the first insulating layer covers the first metal layer , the first insulating layer is provided with a plurality of first via holes, the second metal layer is arranged on the side of the first insulating layer away from the first metal layer, and the second metal layer includes a plurality of conductive An electrode, the conductive electrode is connected to the common signal line through the first via hole, and the second insulating layer is arranged on the side of the first insulating layer away from the first metal layer and covers the second metal layer.
  • the second insulating layer is provided with a plurality of second via holes
  • the first electrode layer is arranged on the side of the second insulating layer away from the second metal layer
  • the first electrode layer includes a first An electrode
  • the first electrode is connected to the conductive electrode through the second via hole
  • the second electrode layer is arranged on the side of the first electrode layer away from the second insulating layer
  • the second electrode layer Including a second electrode, the orthographic projection of at least one of the second via hole and the second electrode on the substrate is staggered from the orthographic projection of the first via hole on the substrate, so as to avoid
  • the insulating layer between the first electrode layer and the second electrode layer is cracked or the second electrode does not exist above the first electrode separated out through the crack between the first electrode layer and the second electrode layer, thereby avoiding the contact between the first electrode and the second electrode layer.
  • the second electrode is shorted.

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Abstract

一种阵列基板(200)，包括：基板(20)；第一金属层(25)，设置在所述基板(20)上，所述第一金属层(25)包括多条公共信号线(250)；第一绝缘层(26)，覆盖所述第一金属层(25)，所述第一绝缘层(26)上设有多个第一过孔(261)；第二金属层(27)，设置于所述第一绝缘层(26)背离所述第一金属层(25)的一侧，所述第二金属层(27)包括多个导电电极(271)，所述导电电极(271)通过所述第一过孔(261)与所述公共信号线(250)连接；第二绝缘层(28)，设置于所述第一绝缘层(26)背离所述第一金属层(25)的一侧并覆盖所述第二金属层(27)，所述第二绝缘层(28)上设有多个第二过孔(281)；第一电极层(29)，设置于所述第二绝缘层(28)背离所述第二金属层(27)的一侧，所述第一电极层(29)包括第一电极(291)，所述第一电极(291)通过所述第二过孔(281)与所述导电电极(271)连接；以及第二电极层(31)，设置于所述第一电极层(29)背离所述第二绝缘层(28)的一侧，所述第二电极层(31)包括第二电极(310)；其中，所述第二过孔(281)和所述第二电极(310)中的至少一个在基板(20)上的正投影与所述第一过孔(261)在所述基板(20)上的正投影错开设置。

Description

阵列基板及电子装置 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及电子装置。
 背景技术
近年来随着电子技术的发展，手机、平板等移动式显示电子装置已成为人们日常生活中必不可少的社交媒介与信息存储载体。对于大尺寸的电子装置，由于显示面板的横向宽度较大，导致显示区中间与四周容易出现显示不均的问题。现有电子装置会在阵列基板上增加设计公共信号线，并通过设置在显示区内的多条公共信号线与公共电极连接，以使公共电极能够及时并均匀的接收到公共电极信号，以此改善显示面板的显示不均的问题。
 技术问题
如图1a和图1b所示，图1a和图1b均为现有阵列基板的结构示意图，包括依次设置的阻挡层11、栅极绝缘层12、公共信号线13、层间介电层14、导电电极15、平坦层16、公共电极17、钝化层18以及像素电极19，公共信号线13通过设置于层间介电层14上的第一过孔141与导电电极15连接，公共电极17通过设置于平坦层16上的第二过孔161与导电电极15连接，第二过孔161套设在第一过孔141上，并暴露出第一过孔141以及形成于第一过孔141内的导电电极15。第一过孔141的侧壁至层间介电层14的表面之间的衔接处a会形成具有一定角度的台阶角，后续制程过程中的静电释放可能会导致位于该衔接处a的台阶角上方的导电电极15熔化，熔化后的导电电极15向公共电极17以及公共电极17上方的钝化层18挤压，并顶破钝化层18，导致位于该衔接处a的钝化层18产生如图1b所示的裂缝。位于钝化层18下方的公共电极17通过钝化层18的裂缝析出，并与位于钝化层18上方的像素电极19短接，导致阵列基板及电子装置在点灯测试时会出现群暗点或水平线等显示异常。
综上所述，现有阵列基板及电子装置存在公共电极和像素电极短接的问题。故，有必要提供一种阵列基板及电子装置来改善这一缺陷。
 技术解决方案
本申请实施例提供一种阵列基板及电子装置，用于解决现有阵列基板及电子装置存在的公共电极和像素电极短接的问题。
本申请实施例提供一种阵列基板，包括：
基板；
第一金属层，设置在所述基板上，所述第一金属层包括多条公共信号线；
第一绝缘层，覆盖所述第一金属层，所述第一绝缘层上设有多个第一过孔；
第二金属层，设置于所述第一绝缘层背离所述第一金属层的一侧，所述第二金属层包括多个导电电极，所述导电电极通过所述第一过孔与所述公共信号线连接；
第二绝缘层，设置于所述第一绝缘层背离所述第一金属层的一侧并覆盖所述第二金属层，所述第二绝缘层上设有多个第二过孔；
第一电极层，设置于所述第二绝缘层背离所述第二金属层的一侧，所述第一电极层包括第一电极，所述第一电极通过所述第二过孔与所述导电电极连接；以及
第二电极层，设置于所述第一电极层背离所述第二绝缘层的一侧，所述第二电极层包括第二电极；
其中，所述第二过孔和所述第二电极中的至少一个在基板上的正投影与所述第一过孔在基板上的正投影错开设置。
根据本申请一实施例，所述第一过孔在所述基板上的正投影与所述第二过孔在所述基板上的正投影完全错开设置，所述第一过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影至少部分重叠。
根据本申请一实施例，所述第二过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置或者至少部分重叠。
根据本申请一实施例，所述导电电极包括：
本体部，所述本体部形成于所述第一过孔内并与所述公共信号线连接，所述第二绝缘层覆盖所述本体部并填充所述第一过孔；以及
延伸部，连接于所述本体部，所述延伸部形成于所述第一绝缘层背离所述第一金属层的一侧，所述第二过孔暴露出所述延伸部，所述第一电极连接于所述延伸部。
根据本申请一实施例，所述第一过孔在所述基板上的正投影与所述第二过孔在所述基板上的正投影完全错开设置，所述第一过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置。
根据本申请一实施例，所述第二过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置或者至少部分重叠。
根据本申请一实施例，所述导电电极包括：
本体部，所述本体部形成于所述第一过孔内并与所述公共信号线连接，所述第二绝缘层覆盖所述本体部并填充所述第一过孔；以及
延伸部，所述延伸部形成于所述第一绝缘层背离所述第一金属层的一侧，所述第二过孔暴露出所述延伸部，所述第一电极连接于所述延伸部。
根据本申请一实施例，所述第一过孔在所述基板上的正投影与所述第二过孔在所述基板上的正投影至少部分重叠，所述第一过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置。
根据本申请一实施例，所述第二过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置或者部分重叠。
根据本申请一实施例，所述阵列基板包括第一区，所述第二电极阵列排布于所述第一区内；
其中，所述第二金属层包括公共电压信号线，所述公共电压信号线环绕所述第一区的外周缘，并通过贯穿所述第一绝缘层的第三过孔与所述公共信号线连接。
根据本申请一实施例，所述阵列基板还包括多条栅极信号线和多条数据信号线；
其中，所述公共信号线与所述栅极信号线设置于同一层，所述公共电压信号线与所述数据信号线设置于同一层。
本申请实施例还提供一种电子装置，所述电子装置包括显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
基板；
第一金属层，设置在所述基板上，所述第一金属层包括多条公共信号线；
第一绝缘层，覆盖所述第一金属层，所述第一绝缘层上设有多个第一过孔；
第二金属层，设置于所述第一绝缘层背离所述第一金属层的一侧，所述第二金属层包括多个导电电极，所述导电电极通过所述第一过孔与所述公共信号线连接；
第二绝缘层，设置于所述第一绝缘层背离所述第一金属层的一侧并覆盖所述第二金属层，所述第二绝缘层上设有多个第二过孔；
第一电极层，设置于所述第二绝缘层背离所述第二金属层的一侧，所述第一电极层包括第一电极，所述第一电极通过所述第二过孔与所述导电电极连接；以及
第二电极层，设置于所述第一电极层背离所述第二绝缘层的一侧，所述第二电极层包括第二电极；
其中，所述第二过孔和所述第二电极中的至少一个在基板上的正投影与所述第一过孔在基板上的正投影错开设置。
根据本申请一实施例，所述第一过孔在所述基板上的正投影与所述第二过孔在所述基板上的正投影完全错开设置，所述第一过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影至少部分重叠。
根据本申请一实施例，所述第二过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置或者至少部分重叠。
根据本申请一实施例，所述导电电极包括：
本体部，所述本体部形成于所述第一过孔内并与所述公共信号线连接，所述第二绝缘层覆盖所述本体部并填充所述第一过孔；以及
延伸部，连接于所述本体部，所述延伸部形成于所述第一绝缘层背离所述第一金属层的一侧，所述第二过孔暴露出所述延伸部，所述第一电极连接于所述延伸部。
根据本申请一实施例，所述第一过孔在所述基板上的正投影与所述第二过孔在所述基板上的正投影完全错开设置，所述第一过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置。
根据本申请一实施例，所述第二过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置或者至少部分重叠。
根据本申请一实施例，所述导电电极包括：
本体部，所述本体部形成于所述第一过孔内并与所述公共信号线连接，所述第二绝缘层覆盖所述本体部并填充所述第一过孔；以及
延伸部，连接于所述本体部，所述延伸部形成于所述第一绝缘层背离所述第一金属层的一侧，所述第二过孔暴露出所述延伸部，所述第一电极连接于所述延伸部。
根据本申请一实施例，所述第一过孔在所述基板上的正投影与所述第二过孔在所述基板上的正投影至少部分重叠，所述第一过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置。
根据本申请一实施例，所述第二过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置或者部分重叠。
 有益效果
本揭示实施例的有益效果：本申请实施例提供一种阵列基板及电子装置，所述电子装置包括显示面板，所述显示面板包括阵列基板，所述阵列基板包括依次层叠设置的基板、第一金属层、第一绝缘层、第二金属层、第二绝缘层、第一电极层以及第二电极层，第一金属层包括多条公共信号线，第一绝缘层覆盖所述第一金属层，所述第一绝缘层上设有多个第一过孔，第二金属层设置于所述第一绝缘层背离所述第一金属层的一侧，所述第二金属层包括多个导电电极，所述导电电极通过所述第一过孔与所述公共信号线连接，第二绝缘层设置于所述第一绝缘层背离所述第一金属层的一侧并覆盖所述第二金属层，所述第二绝缘层上设有多个第二过孔，第一电极层设置于所述第二绝缘层背离所述第二金属层的一侧，所述第一电极层包括第一电极，所述第一电极通过所述第二过孔与所述导电电极连接，第二电极层设置于所述第一电极层背离所述第二绝缘层的一侧，所述第二电极层包括第二电极，所述第二过孔和所述第二电极中的至少一个在所述基板上的正投影与所述第一过孔在所述基板上的正投影错开设置，以此避免第一电极层和第二电极层之间的绝缘层发生破裂或者使得通过第一电极层和第二电极层之间的裂缝析出的第一电极上方不存在第二电极，从而避免第一电极与第二电极短接。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a为现有阵列基板的结构示意图；
图1b为现有阵列基板的结构示意图；
图2为本申请实施例提供的阵列基板的平面结构示意图；
图3为本申请实施例提供的第一种阵列基板沿A-A方向的截面示意图；
图4为本申请实施例提供的第一种阵列基板的局部放大示意图；
图5为本申请实施例提供的第二种阵列基板的局部放大示意图；
图6为本申请实施例提供的第三种阵列基板的局部放大示意图；
图7为本申请实施例提供的第四种阵列基板的局部放大示意图；
图8为本申请实施例提供的第四种阵列基板沿A-A方向的截面示意图；
图9为本申请实施例提供的第五种阵列基板的局部放大示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本揭示做进一步的说明：
本申请实施例提供一种阵列基板及电子装置，所述电子装置包括显示面板，所述显示面板包括阵列基板。所述电子装置可以车载显示终端，例如车载显示器、行车记录仪等，所述电子装置也可以是移动终端，例如智能手机、平板电脑、笔记本电脑等，或者是可穿戴式终端，例如智能手表、智能手环、智能眼镜、增强现实设备等，所述电子装置还可以是固定终端，如台式电脑、电视等，也可以是车载显示终端，如车载显示器或行车记录仪等。
如图2所述，图2为本申请实施例提供的阵列基板的平面结构示意图，阵列基板200包括基板20和阵列排布于基板20上并呈多行和多列排布的子像素单元P，每一个子像素单元P对应具有一个薄膜晶体管T和一个第二电极310，第二电极310为像素电极。阵列基板200还具有多条沿第一方向x延伸的栅极信号线253以及沿第二方向y延伸的数据信号线272，栅极信号线253与对应的一行子像素单元P的薄膜晶体管T的栅极连接，数据信号线272与对应的一列自像素单元P的薄膜晶体管T的漏极连接。
如图3所示，图3为本申请实施例提供的第一种阵列基板沿A-A方向的截面示意图，所述阵列基板200包括基板20和依次层叠设置于基板20上的遮光层21、阻挡层22、有源层23、栅极绝缘层24。
遮光层21具有多个图案化的遮光图案211，遮光层21的材料包括金属材料或不透光、吸光的非金属材料中的任意一种。遮光图案211与有源层23对位设置，遮光图案211用于遮挡有源层23，防止环境光线或内部光线通过基板20一侧照射至有源层23导致有源层23的电学性能下降，从而保证有源层23的电学性能。
阻挡层22设置于基板20上并覆盖遮光层21，用于防止外界水汽或氧通过基板20一侧侵蚀阵列基板200中的薄膜晶体管等器件。
有源层23设置于阻挡层22背离所述基板20的一侧上，有源层23具有沟道部分231和连接于沟道部分231的相对端的导体化部分232。栅极绝缘层24设置于阻挡层22背离所述基板20的一侧上，并覆盖所述有源层23。
所述阵列基板200还包括依次层叠设置于栅极绝缘层24上的第一金属层25、第一绝缘层26、第二金属层27、第二绝缘层28、第一电极层29、第三绝缘层30以及第二电极层31。
结合图2和图3所示，第一金属层25包括多条公共信号线250，每一条公共信号线250均包括主体部251和多个连接部252，主体部251呈长条状且沿第一方向x延伸，多条公共信号线250的主体部251在第二方向y上间隔排布。连接部252呈块状电极，多个连接部252分别连接于所述本体部251的同一侧，并在第一方向x上间隔排布。
在本申请实施例中，栅极信号线253、栅极254与公共信号线250设置于同一层，即栅极信号线253与公共信号线250均设置于第一金属层25，并且可以通过同一道工艺制备形成。公共信号线250与栅极信号线253均沿第一方向x延伸，并且在第二方向y上间隔开。在实际应用中，栅极信号线253和栅极254不仅限设置于第一金属层25，也可以设置于第一金属层25靠近或远离基板20一侧的其他金属层中，此处不做限制。
第一绝缘层26设置于栅极绝缘层24背离所述基板20的一侧上，并且覆盖所述第一金属层25。第一绝缘层26为层间介电层（interlayer dielectric layer, ILD），第一绝缘层26由层叠设置的氧化硅层和氮化硅层构成。在实际应用中，第一绝缘层26也可以由氮化硅或氧化硅中的任意一种或其他绝缘材料形成的单层或多层结构。
第一绝缘层26上设置有多个第一过孔261，第一过孔261第三方向z上贯穿第一绝缘层26，并且暴露出位于第一绝缘层26底部的公共信号线250的连接部252。
第二金属层27设置于第一绝缘层26背离第一金属层25的一侧。第二金属层27包括多个导电电极271，所述导电电极271通过所述第一过孔261与所述公共信号线250连接。
具体的，导电电极271呈块状电极，导电电极271在基板20上的正投影面积大于第一过孔261在基板20上的正投影面积，导电电极271通过第一过孔261与公共信号线250的连接部252连接，用于接收公共信号线250传输的公共电压信号。
在本申请实施例中，数据信号线272、源极273和漏极274可以与导电电极271设置于同一层，即数据信号线272、源极273、漏极274和导电电极271均设置于第二金属层27。导电电极271可以与数据信号线272、源极273以及漏极274通过同一道工艺制备形成。在实际应用中，数据信号线272、源极273和漏极274不仅限设置于第二金属层27，也可以设置于第二金属层27靠近或远离基板20一侧的其他金属层中，此处不做限制。
第二绝缘层28为平坦层，第二绝缘那层28设置于第一绝缘层26背离第一金属层25的一侧上，第二绝缘层28覆盖第二金属层27。第二绝缘层28上设置有多个第二过孔281，第二过孔281在第三方向z上贯穿第二绝缘层28，并且暴露出位于第二绝缘层28底部的导电电极271。
第二绝缘层28上还设置有多个第四过孔282，第四过孔282在第三方向z上贯穿第二绝缘层28，并且暴露出位于第二绝缘层28底部的源极273。
第一电极层29设置于第二绝缘层28背离第二金属层27的一侧，第一电极层29包括第一电极291。第一电极291为公共电极，第一电极291可以整面平铺设置于第二绝缘层28上，并且通过第二绝缘层28上的第二过孔281与导电电极271连接，从而接收由公共信号线250传递的公共电压信号。第一电极层29上还设置有第五过孔292，第五过孔292套设于第四过孔282上，以暴露出所述源极273。
第三绝缘层30为钝化层（passivation layer, PV），第三绝缘层30设置于第一电极层29背离第二绝缘层28的一侧上，并且覆盖所述第一电极层29，第三绝缘层30同时还填充第四过孔282和第五过孔292。第三绝缘层30上设置有多个第六过孔301，第六过孔301套设于第五过孔292和第四过孔282上，并且在第三方向z上贯穿所述第三绝缘层30，以暴露被第三绝缘层30覆盖的源极273。
第二电极层31，设置于所述第一电极层29背离所述第二绝缘层28的一侧。在本申请实施例中，第二电极层31设置于第三绝缘层30上。所述第二电极层31包括多个图案化的第二电极310，第二电极310为像素电极，第二电极310通过第六过孔301与源极273连接，以通过源极273和数据信号线272为第二电极310充电，并与第一电极291之间形成电场从而驱动显示面板中的液晶发生偏转。
结合图2和图3所示，在申请实施例中，阵列基板200还包括第一区A1和环绕所述第一区A1的第二区A2，第一区A1为显示区，所述子像素单元P均设置于所述第一区A1内，第二区A2为非显示区。阵列基板200还包括公共电压信号线275，公共电压信号线275设置于第一区A1的外周缘并环绕所述第一区A1。
在本申请实施例中，所述公共电压信号线275设置于第二金属层27，用于传递第一电极291所需的公共电压信号。第一绝缘层26上还设置有多个在第三方向z上贯穿所述第一绝缘层26的第三过孔262，第三过孔262同样分部于第一区A1的相对侧，公共信号线250的相对端分别通过第三过孔262与公共电压信号线275连接，以使公共电压信号能够快速且均匀地传递至第一电极291。
进一步的，第二绝缘层28上还设置有多个在第三方向z上贯穿所述第二绝缘层28的第七过孔283，第七过孔283暴露出所述公共电压信号线275。多个第七过孔283设置于第一区A1的外周缘，第一电极293可以通过第七过孔283与公共电压信号线275，如此可以使公共电压信号能够进一步快速且均匀地传递至第一电极291，从而改善中大尺寸显示面板存在的显示不均的问题。
所述第二过孔281和所述第二电极310中的至少一个在所述基板20上的正投影与所述第一过孔261在所述基板20上的正投影错开设置，如此可以避免第一电极层29和第二电极层31之间的第三绝缘层30发生破裂；或者，即使第一电极层29和第二电极层31之间的第三绝缘层发生裂缝，通过该裂缝析出的第一电极291上方也不存在第二电极310，以此避免第一电极291与第二电极310发生短接，从而解决阵列基板及电子装置在点灯测试时会出现群暗点或水平线等显示异常的问题，并提高阵列基板的良品率。
所述第一过孔261在所述基板20上的正投影与所述第二过孔281在所述基板20上的正投影完全错开设置。
在一实施例中，如图3所示，所述导电电极271包括本体部271a和延伸部271b。本体部271a形成于第一过孔261内，并且分布于所述第一过孔261的底部以及内壁上。延伸部271b连接于所述本体部271a，延伸部271b形成于第一绝缘层26背离所述第一金属层25的一侧上。由于第二过孔281在所述基板20上的正投影不与第一过孔261在所述基板20上的正投影相交叠，使得第二绝缘层28可以覆盖所述本体部271a，并且填充第一过孔261所形成的凹陷的区域。第二绝缘层28还可以覆盖所述延伸部271b，并且填充第一过孔261，第二绝缘层28上的第二过孔281暴露出部分所述延伸部271b，以便于第一电极291通过第二过孔281与延伸部271b连接。
在本申请实施例中，所述第二绝缘层28的厚度为2.5微米。在实际应用中，所述第二绝缘层28的厚度不仅限于2.5微米，也可以为2微米、2.3微米、2.7微米或3微米等。
需要说明的是，利用第二绝缘层28对第一过孔261所形成的凹陷区域进行填充，可使得后续形成在第二绝缘层28上方的第一电极层29、第三绝缘层30与第一过孔261对应的区域都可以获得平整的表面，避免第一电极层29和第三绝缘层30直接与第一绝缘层26在第一过孔261处的台阶角直接接触，如此可以减小由于静电释放导致的熔化后的导电电极271对第一电极层29以及第三绝缘层30造成的挤压，使得第三绝缘层30产生裂缝的风险降低，从而有效防止第一电极291与第二电极310发生短接。
进一步的，所述第一过孔261在所述基板20上的正投影与所述第二电极310在所述基板20上的正投影至少部分重叠。
在一实施例中，结合图3和图4所示，图4为本申请实施例提供的第一种阵列基板的局部放大示意图，第一过孔261在所述基板20上的正投影不与第二过孔281在所述基板20上的正投影相交叠，且第一过孔261在所述基板20上的正投影与第二电极310在所述基板20上的正投影部分重叠。第二过孔281在所述基板20上的正投影与所述第二电极310在所述基板20上的正投影部分重叠。在实际应用中，第二电极310在所述基板20上的正投影也可以完全覆盖第二过孔281在所述基板20上的正投影。
在一实施例中，如图5所示，图5为本申请实施例提供的第二种阵列基板的局部放大示意图，第一过孔261在所述基板20上的正投影不与第二过孔281在所述基板20上的正投影相交叠，所述第二电极310在所述基板20上的正投影完全覆盖所述第一过孔261在所述基板20上的正投影，并且第二电极310在所述基板20上的正投影同时也完全覆盖第二过孔281在所述基板20上的正投影。在实际应用中，第二过孔281在所述基板20上的正投影也可以与所述第二电极310在所述基板20上的正投影部分重叠。
在一实施例中，如图6所示，图6为本申请实施例提供的第三种阵列基板的局部放大示意图，第一过孔261在所述基板20上的正投影不与第二过孔281在所述基板20上的正投影相交叠，所述第一过孔261在所述基板20上的正投影与第二电极310在所述基板20上的正投影完全错开设置，两者并不相交叠，且第二过孔281在所述基板20上的正投影与第二电极310在所述基板20上的正投影同样完全错开设置。在实际应用中，第二电极310在所述基板20上的正投影也可以与第二过孔281在所述基板20上的正投影部分重叠，或者完全覆盖第二过孔281在第三方向z上的正投影。
可以理解的是，上述各实施例中，由于第一过孔261和第二过孔281在所述基板上的正投影完全错开设置，可以利用第二绝缘层28对第一过孔261形成的凹陷的区域进行填充，使得第一过孔261上方的各膜层具有平坦表面，因此即使第一过孔261和第二过孔281上方并未设置有第二电极310、或者设置有部分第二电极310、或者完全覆盖有第二电极310，也不会造成第一电极291与第二电极310短接的问题。若将第二电极310的正投影与第一过孔261和/或第二过孔281的正投影部分重叠或完全覆盖，如此不会由于将第一过孔261和第二过孔281错开设置导致第二电极310的面积减小，从而保证阵列基板200中各子像素的开口率。
在另一实施例中，所述第一过孔261在所述基板上的正投影与所述第二过孔281在所述基板上的正投影至少部分重叠，所述第一过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置。
具体的，结合图7所示，图7为本申请实施例提供的第四种阵列基板的局部放大示意图，第二电极310在所述基板20上的正投影与第一过孔261在所述基板20上的正投影完全错开设置，两者之间并不相交叠，第二电极310在所述基板20上的正投影与第二过孔281在所述基板20上的正投影也完全错开设置。如此可以利用第二绝缘层28填充第一过孔261，从而降低位于第一过孔261上方的第三绝缘层30发生裂缝的风险，避免第一电极291与第二电极310发生短接。
如图8所示，图8为本申请实施例提供的第四种阵列基板沿A-A方向的截面示意图，所述第二过孔281套设在第一过孔261上，且第二过孔281在第三方向z上的正投影完全覆盖第一过孔261在第三方向z上的正投影。相较于将第一过孔261和第二过孔281错开设计，通过将第二过孔281套设在第一过孔261上，可以减少第一过孔261和第二过孔281所占据的平面面积。
在另一实施例中，如图9所示，图9为本申请实施例提供的第五种阵列基板的局部放大示意图，为避免开设第一过孔261和第二过孔281导致第二电极310的面积被压缩，可以使第二电极310在所述基板20上的正投影与第二过孔281在所述基板20上的正投影部分重叠，且第二过孔281在所述基板20上的正投影与第一过孔261在所述基板20上的正投影完全错开设置。如此，既可以避免第一电极291与第二电极310发生短接，又可以避免第一过孔261和第二过孔281压缩第二电极310的面积。
本申请实施例的有益效果：本申请实施例提供一种阵列基板及电子装置，所述电子装置包括显示面板，所述显示面板包括阵列基板，所述阵列基板包括依次层叠设置的基板、第一金属层、第一绝缘层、第二金属层、第二绝缘层、第一电极层以及第二电极层，第一金属层包括多条公共信号线，第一绝缘层覆盖所述第一金属层，所述第一绝缘层上设有多个第一过孔，第二金属层设置于所述第一绝缘层背离所述第一金属层的一侧，所述第二金属层包括多个导电电极，所述导电电极通过所述第一过孔与所述公共信号线连接，第二绝缘层设置于所述第一绝缘层背离所述第一金属层的一侧并覆盖所述第二金属层，所述第二绝缘层上设有多个第二过孔，第一电极层设置于所述第二绝缘层背离所述第二金属层的一侧，所述第一电极层包括第一电极，所述第一电极通过所述第二过孔与所述导电电极连接，第二电极层设置于所述第一电极层背离所述第二绝缘层的一侧，所述第二电极层包括第二电极，所述第二过孔和所述第二电极中的至少一个在所述基板上的正投影与所述第一过孔在所述基板上的正投影错开设置，以此避免第一电极层和第二电极层之间的绝缘层发生破裂或者使得通过第一电极层和第二电极层之间的裂缝析出的第一电极上方不存在第二电极，从而避免第一电极与第二电极短接。
综上所述，虽然本申请以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为基准。

Claims (20)

  1. 一种阵列基板，包括：
    基板；
    第一金属层，设置在所述基板上，所述第一金属层包括多条公共信号线；
    第一绝缘层，覆盖所述第一金属层，所述第一绝缘层上设有多个第一过孔；
    第二金属层，设置于所述第一绝缘层背离所述第一金属层的一侧，所述第二金属层包括多个导电电极，所述导电电极通过所述第一过孔与所述公共信号线连接；
    第二绝缘层，设置于所述第一绝缘层背离所述第一金属层的一侧并覆盖所述第二金属层，所述第二绝缘层上设有多个第二过孔；
    第一电极层，设置于所述第二绝缘层背离所述第二金属层的一侧，所述第一电极层包括第一电极，所述第一电极通过所述第二过孔与所述导电电极连接；以及
    第二电极层，设置于所述第一电极层背离所述第二绝缘层的一侧，所述第二电极层包括第二电极；
    其中，所述第二过孔和所述第二电极中的至少一个在基板上的正投影与所述第一过孔在所述基板上的正投影错开设置。
  2. 如权利要求1所述的阵列基板，其中，所述第一过孔在所述基板上的正投影与所述第二过孔在所述基板上的正投影完全错开设置，所述第一过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影至少部分重叠。
  3. 如权利要求2所述的阵列基板，其中，所述第二过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置或者至少部分重叠。
  4. 如权利要求2所述的阵列基板，其中，所述导电电极包括：
    本体部，所述本体部形成于所述第一过孔内并与所述公共信号线连接，所述第二绝缘层覆盖所述本体部并填充所述第一过孔；以及
    延伸部，连接于所述本体部，所述延伸部形成于所述第一绝缘层背离所述第一金属层的一侧，所述第二过孔暴露出所述延伸部，所述第一电极连接于所述延伸部。
  5. 如权利要求1所述的阵列基板，其中，所述第一过孔在所述基板上的正投影与所述第二过孔在所述基板上的正投影完全错开设置，所述第一过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置。
  6. 如权利要求5所述的阵列基板，其中，所述第二过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置或者至少部分重叠。
  7. 如权利要求5所述的阵列基板，其中，所述导电电极包括：
    本体部，所述本体部形成于所述第一过孔内并与所述公共信号线连接，所述第二绝缘层覆盖所述本体部并填充所述第一过孔；以及
    延伸部，连接于所述本体部，所述延伸部形成于所述第一绝缘层背离所述第一金属层的一侧，所述第二过孔暴露出所述延伸部，所述第一电极连接于所述延伸部。
  8. 如权利要求1所述的阵列基板，其中，所述第一过孔在所述基板上的正投影与所述第二过孔在所述基板上的正投影至少部分重叠，所述第一过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置。
  9. 如权利要求8所述的阵列基板，其中，所述第二过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置或者部分重叠。
  10. 如权利要求1所述的阵列基板，其中，所述阵列基板包括第一区，所述第二电极阵列排布于所述第一区内；
    其中，所述第二金属层包括公共电压信号线，所述公共电压信号线环绕所述第一区的外周缘，并通过贯穿所述第一绝缘层的第三过孔与所述公共信号线连接。
  11. 如权利要求10所述的阵列基板，其中，所述阵列基板还包括多条栅极信号线和多条数据信号线；
    其中，所述公共信号线与所述栅极信号线设置于同一层，所述公共电压信号线与所述数据信号线设置于同一层。
  12. 一种电子装置，所述电子装置包括显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
    基板；
    第一金属层，设置在所述基板上，所述第一金属层包括多条公共信号线；
    第一绝缘层，覆盖所述第一金属层，所述第一绝缘层上设有多个第一过孔；
    第二金属层，设置于所述第一绝缘层背离所述第一金属层的一侧，所述第二金属层包括多个导电电极，所述导电电极通过所述第一过孔与所述公共信号线连接；
    第二绝缘层，设置于所述第一绝缘层背离所述第一金属层的一侧并覆盖所述第二金属层，所述第二绝缘层上设有多个第二过孔；
    第一电极层，设置于所述第二绝缘层背离所述第二金属层的一侧，所述第一电极层包括第一电极，所述第一电极通过所述第二过孔与所述导电电极连接；以及
    第二电极层，设置于所述第一电极层背离所述第二绝缘层的一侧，所述第二电极层包括第二电极；
    其中，所述第二过孔和所述第二电极中的至少一个在基板上的正投影与所述第一过孔在所述基板上的正投影错开设置。
  13. 如权利要求12所述的电子装置，其中，所述第一过孔在所述基板上的正投影与所述第二过孔在所述基板上的正投影完全错开设置，所述第一过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影至少部分重叠。
  14. 如权利要求13所述的电子装置，其中，所述第二过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置或者至少部分重叠。
  15. 如权利要求13所述的电子装置，其中，所述导电电极包括：
    本体部，所述本体部形成于所述第一过孔内并与所述公共信号线连接，所述第二绝缘层覆盖所述本体部并填充所述第一过孔；以及
    延伸部，连接于所述本体部，所述延伸部形成于所述第一绝缘层背离所述第一金属层的一侧，所述第二过孔暴露出所述延伸部，所述第一电极连接于所述延伸部。
  16. 如权利要求12所述的电子装置，其中，所述第一过孔在所述基板上的正投影与所述第二过孔在所述基板上的正投影完全错开设置，所述第一过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置。
  17. 如权利要求16所述的电子装置，其中，所述第二过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置或者至少部分重叠。
  18. 如权利要求16所述的电子装置，其中，所述导电电极包括：
    本体部，所述本体部形成于所述第一过孔内并与所述公共信号线连接，所述第二绝缘层覆盖所述本体部并填充所述第一过孔；以及
    延伸部，连接于所述本体部，所述延伸部形成于所述第一绝缘层背离所述第一金属层的一侧，所述第二过孔暴露出所述延伸部，所述第一电极连接于所述延伸部。
  19. 如权利要求12所述的电子装置，其中，所述第一过孔在所述基板上的正投影与所述第二过孔在所述基板上的正投影至少部分重叠，所述第一过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置。
  20. 如权利要求19所述的电子装置，其中，所述第二过孔在所述基板上的正投影与所述第二电极在所述基板上的正投影完全错开设置或者部分重叠。
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