WO2024060320A1 - 一种半导体结构及其制备方法 - Google Patents

一种半导体结构及其制备方法 Download PDF

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Publication number
WO2024060320A1
WO2024060320A1 PCT/CN2022/123998 CN2022123998W WO2024060320A1 WO 2024060320 A1 WO2024060320 A1 WO 2024060320A1 CN 2022123998 W CN2022123998 W CN 2022123998W WO 2024060320 A1 WO2024060320 A1 WO 2024060320A1
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conductive
chips
conductive structures
semiconductor structure
adjacent layers
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PCT/CN2022/123998
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English (en)
French (fr)
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方媛
王彦武
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长鑫存储技术有限公司
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Priority to US18/525,467 priority Critical patent/US20240096853A1/en
Publication of WO2024060320A1 publication Critical patent/WO2024060320A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same.
  • high-bandwidth memory (HBM) chips can be stacked on the upper surface of a packaging substrate.
  • the HBM chip can be electrically connected to the packaging substrate via conductive bumps.
  • TSV through-silicon via
  • embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof.
  • a semiconductor structure including:
  • a plurality of chips a plurality of chips stacked in sequence along a first direction, the first direction being a direction perpendicular to the plane of the chips;
  • Each of the chips includes:
  • n first conductive structures penetrating the substrate along a first direction, wherein n is greater than or equal to 2;
  • the projections of the group of first conductive structures in two adjacent layers of chips in the first direction do not overlap.
  • it also includes:
  • First interconnection lines corresponding first conductive structures in the chips on two adjacent layers are connected through the first interconnection lines.
  • the n first conductive structures are located on the same circumference
  • the projections of the corresponding first conductive structures in the chips of two adjacent layers do not overlap.
  • the projections of the corresponding first conductive structures in the two adjacent layers of the chip respectively form a preset angle with the line connecting the center of the circle, and the preset angle ranges from 30° to 90°.
  • the corresponding first conductive structure in each layer of the chip rotates and rises at a preset angle in a preset direction, wherein the preset direction is clockwise or counterclockwise. direction.
  • the first conductive structure includes a first through silicon via and a first conductive bump, the first through silicon via is located on the first conductive bump, and the first through silicon via is along the A first direction penetrates the substrate, and the first conductive bump is located between two adjacent layers of chips.
  • the first conductive bump includes at least one concave surface, and the concave surfaces adjacent to the first conductive bump are arranged oppositely.
  • one end of the first interconnection line is connected to the first through silicon via, and the other end of the first interconnection line is connected to the first conductive bump.
  • each chip further includes: a second conductive structure located at the center of a circle formed by the n first conductive structures and penetrating the substrate along the first direction.
  • it also includes:
  • Second interconnection lines the second conductive structures in two adjacent layers of the chips are connected through the second interconnection lines.
  • the first conductive structure is a signal conductive structure
  • the second conductive structure is a dummy conductive structure
  • a method for forming a semiconductor structure including:
  • the formation of chips includes:
  • n first conductive structures penetrating the substrate along a first direction, where n is greater than or equal to 2;
  • the projections of the group of first conductive structures in two adjacent layers of chips in the first direction do not overlap.
  • it also includes:
  • a first interconnection line is formed, and corresponding first conductive structures in two adjacent layers of the chips are connected through the first interconnection line.
  • the n first conductive structures are located on the same circumference
  • the projections of the corresponding first conductive structures in the chips of two adjacent layers do not overlap.
  • forming a chip further includes:
  • a second conductive structure is formed, the second conductive structure is located at the center of a circle formed by the n first conductive structures and penetrates the substrate along the first direction.
  • it also includes:
  • a second interconnection line is formed, and the second conductive structures in two adjacent layers of the chip are connected through the second interconnection line.
  • the projections of the corresponding first conductive structures in the two adjacent layers of chips do not overlap, indicating that the corresponding first conductive structures in the two adjacent layers of chips are offset at a certain angle.
  • the same signal is The internal rotation of the structure formed by stacking multiple chips can reduce crosstalk between different signals.
  • the spatial structure is optimized to form a higher bandwidth memory.
  • Figure 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a perspective view of the first conductive structure provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of the first conductive structure provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of two adjacent layers of chips connected through a first interconnection line
  • Figure 5 is a schematic structural diagram of each layer of chips provided by an embodiment of the present disclosure.
  • Figure 6 is a perspective view of a semiconductor structure provided by another embodiment of the present disclosure.
  • FIG7 is a flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG 8a to 9b are schematic structural diagrams of the semiconductor structure during the preparation process according to embodiments of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure includes:
  • a plurality of chips 21 are stacked in sequence along a first direction, and the first direction is a direction perpendicular to the plane of the chips 21;
  • Each of said chips 21 includes:
  • n first conductive structures 30 penetrate the substrate 210 along the first direction, and n is greater than or equal to 2;
  • the projections of the group of first conductive structures 30 in two adjacent layers of chips 21 along the first direction do not overlap.
  • the projections of the corresponding first conductive structures in two adjacent layers of chips do not overlap, indicating that the corresponding first conductive structures in two adjacent layers of chips are staggered at a certain angle, so that the same signal rotates and rises in the structure formed by stacking multiple chips, which can reduce the crosstalk between different signals.
  • the spatial structure is optimized to form a memory with higher bandwidth.
  • the substrate 210 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium on Insulator) substrate.
  • On Insulator) substrate, etc. may also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), and It can be a stacked structure, such as Si/SiGe, etc., or other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • FIG. 2 is a perspective view of the first conductive structure provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of the first conductive structure provided by an embodiment of the present disclosure.
  • the first conductive structure 30 includes a first conductive bump 31 , and the first conductive bump 31 includes at least one concave surface 301 , adjacent to the first conductive bump 301 .
  • the concave surfaces 301 on the conductive bump 31 are arranged oppositely.
  • the first conductive bump is configured to include at least one concave surface. In this way, the volume of the first conductive bump is reduced, thereby reducing the parasitic capacitance of the first conductive bump itself.
  • the first conductive structures 30 are arranged in a square shape, and among the plurality of first conductive structures 30 arranged in a square shape, two first conductive structures 30 are located at diagonal positions.
  • the concave surfaces 301 of the first conductive bumps 31 are arranged opposite to each other.
  • the concave surfaces of the first conductive bumps at diagonal positions are arranged oppositely. In this way, the distance between the first conductive bumps increases, thereby reducing the fringe field between the first conductive bumps, and thus Reduced RLC parasitic parameters.
  • the first conductive bump 31 further includes at least one convex surface 302 , and the convex surface 302 is arranged adjacent to the concave surface 301 .
  • the convex surface 302 is arranged adjacent to the concave surface 301 .
  • the distance from the intersection of the diagonals of each square arrangement to the concave surface 301 of each first conductive bump 31 is a first distance h1.
  • the distance from the concave surface 301 of the bump 31 to the center of the first conductive bump 31 is the second distance h2, and the ratio of the first distance h1 to the second distance h2 is 5:3 ⁇ 5:2.
  • the ratio of the first distance to the second distance is set too large, it means that the concave surface of the first conductive bump is too close to the center of the first conductive bump. This will cause the area of the first conductive bump to be too small, affecting The conductive performance of the first conductive bump; and if the ratio of the first distance and the second distance is set too small, it means that the concave surface of the first conductive bump is close to the intersection of the diagonals, so that the adjacent first conductive bumps The distance between blocks is reduced, thereby increasing the parasitic parameters. Therefore, setting the ratio of the first distance to the second distance to 5:3 ⁇ 5:2 not only ensures the conductive performance of the first conductive bump, but also reduces parasitic parameters.
  • the first conductive structure 30 further includes a first through silicon via 32 and a first test pad 33 .
  • the first through silicon via 32 is located on the first conductive bump.
  • the first test pad 33 is located between the first through silicon via 32 and the first conductive bump 31 .
  • the first through silicon via and the first conductive bump ensure electrical connection between the subsequent substrate and the chip stack, and the first test pad can be used for test functions.
  • the conductive material inside the first through silicon via 32 includes but is not limited to Cu, and the conductive material is wrapped with a layer of insulating material.
  • the insulating material includes but is not limited to SiO2.
  • the material of the first test pad 33 includes but is not limited to Al.
  • the first conductive bump 31 includes a first solder pad 311 and a first solder ball 312, and the first solder pad 311 is located on the first solder ball 312; Wherein, the orthographic projection of the first solder pad 311 on the substrate is located inside the orthographic projection of the first solder ball 312 on the substrate.
  • the first pad 311 includes a first sub-pad 311 a and a second sub-pad 311 b , and the first sub-pad 311 a is located on the second sub-pad 311 b ; wherein the volume of the first sub-pad 311 a is smaller than the volume of the second sub-pad 311 b .
  • an insulating layer is first placed on the first test pad, the insulating layer covers the first test pad, and then the insulating layer is exposed.
  • An opening is formed on the test pad, that is to say, the depth of the opening is equal to the thickness of the insulating layer on the first test pad, that is to say, the width of the opening can be smaller than the width of the first test pad, thereby making the first sub-pad 311a smaller in volume.
  • the second sub-pad 311b has a larger volume.
  • the first sub-pad 311a with a smaller volume is formed, and the first sub-pad 311b with a larger volume is formed. It should be noted that the first sub-pad 311a and the second sub-pad 311b may be formed at the same time.
  • the projections of the group of first conductive structures 30 in the two adjacent layers of the chips 21 in the first direction do not overlap, including: the group of the first conductive structures 30 located in the chip 21
  • the projections of the first through silicon vias 32 of the first conductive structure 30 along the first direction do not overlap.
  • the semiconductor structure further includes: a first interconnection line 71 through which corresponding first conductive structures 30 in two adjacent layers of the chip 21 are connected.
  • a first interconnection line 71 through which corresponding first conductive structures 30 in two adjacent layers of the chip 21 are connected.
  • each layer of the chip may include four first conductive structures 30 , which are CHO, CH1, CH2 and CH3 respectively.
  • the corresponding CHO in each layer of the chip passes through the first interconnection line 71 are connected, and rotate and rise at a certain angle.
  • CH1, CH2 and CH3 are also connected through the first interconnection line 71, and rotate and rise at a certain angle.
  • the first interconnection lines connecting the two corresponding first conductive structures in the same layer are deflected at a certain angle, thereby reducing the facing area of the first interconnection lines, thereby reducing the number of first interconnection lines. crosstalk between.
  • one end of the first interconnection line is connected to the first through silicon via, and the other end of the first interconnection line is connected to the first conductive bump.
  • the first interconnection line is a metal line, as shown in Figure 4, including metal lines M0 to M4.
  • one end of the first interconnection line 71 is M0, and M0 is connected to the first through silicon via or the first conductive bump of the first conductive structure in one of the chips, and the other end M4 is connected to The first conductive bumps or first through-silicon vias of the corresponding first conductive structures in adjacent chips are connected, that is, one end is connected to the first through-silicon via, and the other end is connected to the first conductive bump, and vice versa.
  • M0 and M4 are connected through M1, M2 and M3.
  • the n first conductive structures 30 are located on the same circumference; in the projection along the first direction, the projections of the corresponding first conductive structures 30 in the two adjacent layers of the chips 21 do not overlap. .
  • the projections of all corresponding first conductive structures in two adjacent chips do not overlap, that is, all the first conductive structures rotate and rise at a certain angle. In this way, the interference between different signals is minimized. crosstalk between.
  • the projections of the corresponding first conductive structures 30 in the two adjacent layers of the chips 21 respectively form a preset angle with the line connecting the center of the circle, and the preset angle ranges from 30° to 90°.
  • the preset angle may be 45°.
  • the first conductive structures 30 arranged in a square shape in each layer of the chip 21 will only be arranged in two ways as shown in FIG.
  • a conductive structure 30 is shown as stack1, stack3, stack5 and stack7 in Figure 5
  • the first conductive structure 30 in the even-numbered layer chip 21 will be as shown in stack2, stack4, stack6 and stack8 in Figure 5, and vice versa.
  • the complexity of the process is also reduced.
  • CH0 in two adjacent layers of chips will not be placed facing each other.
  • the first conductive structures 30 (such as CHO and CH1) in the semiconductor structure are arranged spirally in the stacking direction instead of vertically. That is, the same first conductive structure 30 in two adjacent layers of chips is arranged spirally in the stacking direction.
  • the distance of conductive structure 30 (eg CHO) will increase.
  • the first conductive structures 30 for example, CHO and CH1 in the semiconductor structure are arranged vertically, the first conductive structures 30 in the chips (stack1 to stack8) will all generate signal crosstalk due to the fringe field effect, and at the same time, due to the first conductive structure 30 are arranged vertically, that is, the same first conductive structure 30 in adjacent chips (for example, stack1 to stack2) is closer, a superposition of crosstalk effects will occur, and at the same time, as the length of the signal formed by the first conductive structure 30 becomes longer, , the superposition effect of the crosstalk effect will be stronger, which will eventually cause signal distortion in the top chip (stack8).
  • the first conductive structures 30 for example, CHO and CH1 are arranged in a spiral, that is, the distance between the same first conductive structure 30 (for example, CH0) in two adjacent layers of chips will increase, so that in the same chip
  • the crosstalk effect will not be superimposed on another chip (for example, stack2), thereby improving the impact of crosstalk on the signal.
  • the first conductive structure 30 may be a through-silicon via structure, and CHO and CH1 may represent different through-silicon vias, that is, through-silicon vias that transmit different signals.
  • the corresponding first conductive structure 30 in each layer of the chip 21 rotates and rises at a preset angle in a preset direction, wherein the preset angle Let the direction be clockwise or counterclockwise.
  • each chip 21 may also include a second conductive structure 40 located at the center of a circle formed by the n first conductive structures 30 , and penetrating the base 210 along the first direction.
  • the semiconductor structure further includes: a second interconnection line 72 through which the second conductive structure 40 in two adjacent layers of the chip 21 is connected.
  • the second interconnection line 72 includes, for example, a bonding pad and a bonding pad structure, thereby realizing the connection of the second conductive structure 40 .
  • the first conductive structure is a signal conductive structure
  • the second conductive structure is a dummy conductive structure.
  • the conductive structure forms a virtual TSV channel, which can dissipate the heat generated by the first conductive structure in each layer of the chip, changing the heat dissipation method to spreading heat to the center point, increasing heat dissipation efficiency and improving device performance.
  • Embodiments of the present disclosure also provide a method for preparing a semiconductor structure. Please refer to FIG. 7 for details. As shown in the figure, the method includes the following steps:
  • Step 701 Form a plurality of sequentially stacked chips along a first direction, where the first direction is a direction perpendicular to the plane of the chips;
  • the forming of the chip comprises:
  • n first conductive structures penetrating the substrate along a first direction, where n is greater than or equal to 2;
  • the projections of the group of first conductive structures in two adjacent layers of chips in the first direction do not overlap.
  • FIG 8a to 9b are schematic structural diagrams of the semiconductor structure during the preparation process according to embodiments of the present disclosure.
  • the forming of the first conductive structure 30 includes:
  • the initial first conductive structure 300 includes an initial first conductive bump 310, the shape of the initial first conductive bump 310 is circular;
  • first mask layer 61 Form at least one first mask layer 61 on each of the initial first conductive bumps 310, and the first mask layer 61 covers part of the periphery of the initial first conductive bumps 310;
  • the portion of the initial first conductive bump 310 covered by the first mask layer 61 is etched away to form the first conductive structure 30 .
  • the shape of the first mask layer 61 is circular, so that the first conductive bump formed after part of the initial first conductive bump 310 is removed includes at least one concave surface.
  • the first mask layer can also have other arc-shaped structures.
  • the first conductive structures 30 are arranged in a square shape, and among the plurality of first conductive structures 30 arranged in a square shape, two first conductive structures 30 are located at diagonal positions.
  • the concave surfaces 301 of the first conductive bumps 31 are arranged opposite to each other.
  • the concave surfaces of the first conductive bumps at diagonal positions are arranged oppositely. In this way, the distance between the first conductive bumps increases, thereby reducing the fringe field between the first conductive bumps, and thus Reduced RLC parasitic parameters.
  • the first conductive bump 31 further includes at least one convex surface 302 , and the convex surface 302 is arranged adjacent to the concave surface 301 .
  • the convex surface 302 is arranged adjacent to the concave surface 301 .
  • the distance from each intersection of the diagonals of the square arrangement to the concave surface 301 of each first conductive bump 31 is a first distance h1
  • the distance from the concave surface 301 of the first conductive bump 31 to the center of the first conductive bump 31 is a second distance h2
  • the ratio of the first distance h1 to the second distance h2 is 5:3 to 5:2.
  • the ratio of the first distance to the second distance is set too large, it means that the concave surface of the first conductive bump is too close to the center of the first conductive bump. This will cause the area of the first conductive bump to be too small, affecting The conductive performance of the first conductive bump; and if the ratio of the first distance and the second distance is set too small, it means that the concave surface of the first conductive bump is close to the intersection of the diagonals, so that the adjacent first conductive bumps The distance between blocks is reduced, thereby increasing the parasitic parameters. Therefore, setting the ratio of the first distance to the second distance to 5:3 ⁇ 5:2 not only ensures the conductive performance of the first conductive bump, but also reduces parasitic parameters.
  • the first conductive structure 30 further includes a first through silicon via 32 and a first test pad 33 .
  • the first through silicon via 32 is located on the first conductive bump.
  • the first test pad 33 is located between the first through silicon via 32 and the first conductive bump 31 .
  • the first through silicon via and the first conductive bump ensure electrical connection between the subsequent substrate and the chip stack, and the first test pad can be used for test functions.
  • the conductive material inside the first through silicon hole 32 includes but is not limited to Cu, and the conductive material is wrapped with a layer of insulating material.
  • the insulating material includes but is not limited to SiO2.
  • the material of the first test pad 33 includes but is not limited to Al.
  • the first conductive bump 31 includes a first solder pad 311 and a first solder ball 312, and the first solder pad 311 is located on the first solder ball 312; Wherein, the orthographic projection of the first solder pad 311 on the substrate 10 is located inside the orthographic projection of the first solder ball 312 on the substrate 10 .
  • the first bonding pad 311 includes a first sub-bonding pad 311a and a second sub-bonding pad 311b, and the first sub-bonding pad 311a is located on the second sub-bonding pad 311b; wherein, the first sub-bonding pad 311a is located on the second sub-bonding pad 311b;
  • the volume of the first sub-pad 311a is smaller than the volume of the second sub-pad 311b.
  • the first sub-pad is connected to the first test pad, so the first sub-pad is smaller in size, which can reduce the contact area with the first test pad, thereby reducing contact resistance.
  • connection method of the chips in the chip stack prepared by the above method can be improved to further reduce the RLC parasitic parameters.
  • step 701 is performed to form a plurality of sequentially stacked chips 21 along a first direction, which is a direction perpendicular to the plane of the chips 21; forming the chips 21 includes: providing a substrate 210 ; Forming n first conductive structures 30 penetrating the substrate 210 along the first direction, where n is greater than or equal to 2; wherein, in at least one group of corresponding first conductive structures 30 in all chips 21 , The projections of the group of first conductive structures 30 in the chips 21 of two adjacent layers in the first direction do not overlap.
  • the substrate 210 may be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, an SOI (Silicon On Insulator) substrate or a GOI (Germanium on Insulator) substrate.
  • On Insulator) substrate, etc. may also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), and It can be a stacked structure, such as Si/SiGe, etc., or other epitaxial structures, such as SGOI (silicon germanium on insulator), etc.
  • the projections of the group of the first conductive structures 30 in the two adjacent layers of the chips 21 along the first direction do not overlap, including: the projections of the first through silicon vias 32 of the group of the first conductive structures 30 in the chip 21 along the first direction do not overlap.
  • the method also includes: after forming each layer of chips 21, forming a first interconnection line 71, and the corresponding first conductive structures 30 in the chips 21 of two adjacent layers pass through the first interconnection. Line 71 is connected.
  • each layer of the chip may include four first conductive structures 30 , which are CHO, CH1, CH2 and CH3 respectively.
  • the corresponding CHO in each layer of the chip passes through the first interconnection line 71 are connected, and rotate and rise at a certain angle.
  • CH1, CH2 and CH3 are also connected through the first interconnection line 71, and rotate and rise at a certain angle.
  • the first interconnection lines connecting the two corresponding first conductive structures in the same layer are deflected at a certain angle, thereby reducing the facing area of the first interconnection lines, thereby reducing the number of first interconnection lines. crosstalk between.
  • one end of the first interconnection line is connected to the first through silicon via, and the other end of the first interconnection line is connected to the first conductive bump.
  • the first interconnection line is a metal line, as shown in Figure 4, including metal lines M0 to M4.
  • one end of the first interconnection line 71 is M0, and M0 is connected to the first through silicon via or the first conductive bump of the first conductive structure in one of the chips, and the other end M4 is connected to The first conductive bumps or first through-silicon vias of the corresponding first conductive structures in adjacent chips are connected, that is, one end is connected to the first through-silicon via, and the other end is connected to the first conductive bump, and vice versa.
  • M0 and M4 are connected through M1, M2 and M3.
  • the n first conductive structures 30 are located on the same circumference; in the projection along the first direction, the projections of the corresponding first conductive structures 30 in the two adjacent layers of the chips 21 do not overlap. .
  • the projections of all corresponding first conductive structures in two adjacent chips do not overlap, that is, all the first conductive structures rotate and rise at a certain angle. In this way, the interference between different signals is minimized. crosstalk between.
  • the projections of the corresponding first conductive structures 30 in the two adjacent layers of the chips 21 respectively form a preset angle with the line connecting the center of the circle, and the preset angle ranges from 30° to 90°.
  • the preset angle may be 45°.
  • the first conductive structures 30 arranged in a square shape in each layer of the chip 21 will only be arranged in two ways as shown in FIG.
  • a conductive structure 30 is shown as stack1, stack3, stack5 and stack7 in Figure 5
  • the first conductive structure 30 in the even-numbered chip 21 will be as shown in stack2, stack4, stack6 and stack8 in Figure 5, and vice versa.
  • the complexity of the process is also reduced.
  • CH0 in two adjacent layers of chips will not be placed facing each other.
  • CH1, CH2 and CH3 in two adjacent layers of chips will not be placed facing each other. In this way, the corresponding number of adjacent chips in the adjacent chips will be reduced.
  • a facing area of a conductive structure thereby reducing signal crosstalk and parasitic capacitance.
  • the corresponding first conductive structure 30 in each layer of the chip 21 rotates and rises at a preset angle in a preset direction, wherein the preset angle Let the direction be clockwise or counterclockwise.
  • forming the chip 21 also includes:
  • a second conductive structure 40 is formed.
  • the second conductive structure 40 is located at the center of a circle formed by the n first conductive structures 30 and penetrates the substrate 210 along the first direction.
  • the method further includes forming a second interconnection line 72 through which the second conductive structures 40 in two adjacent layers of the chips 21 are connected.
  • the first conductive structure is a signal conductive structure
  • the second conductive structure is a dummy conductive structure.
  • the conductive structure forms a virtual TSV channel, which can dissipate the heat generated by the first conductive structure in each layer of the chip, changing the heat dissipation method to spreading heat to the center point, increasing heat dissipation efficiency and improving device performance.
  • the projections of the corresponding first conductive structures in the two adjacent layers of chips do not overlap, indicating that the corresponding first conductive structures in the two adjacent layers of chips are offset at a certain angle.
  • the same signal is The internal rotation of the structure formed by stacking multiple chips can reduce crosstalk between different signals.
  • the spatial structure is optimized to form a higher bandwidth memory.

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Abstract

本公开实施例公开了一种半导体结构及其制备方法，其中，所述半导体结构包括：多个芯片，多个所述芯片沿第一方向依次堆叠，所述第一方向为垂直于所述芯片的平面的方向；每个所述芯片包括：基底；n个第一导电结构，沿第一方向贯穿所述基底，所述n大于或等于2；其中，在所有芯片内的至少一组相对应的第一导电结构中，相邻两层所述芯片内的该组所述第一导电结构，在沿第一方向的投影不重叠。

Description

一种半导体结构及其制备方法
相关申请的交叉引用
本公开基于申请号为202211139021.2、申请日为2022年09月19日、发明名称为“一种半导体结构及其制备方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及其制备方法。
背景技术
通常，高带宽存储器(HBM)芯片可以堆叠在封装基底的上表面上。HBM芯片可以经由导电凸块而与封装基底电连接。3D封装堆叠技术的发展，高带宽和低功耗的需求推动更高的芯片堆叠和更密集的硅通孔(Through-Silicon Via，TSV)互连。但是HBM的集成度越高，信号之间的串扰效应会增强。
发明内容
有鉴于此，本公开实施例提供一种半导体结构及其制备方法。
根据本公开实施例的第一方面，提供了一种半导体结构，包括：
多个芯片，多个所述芯片沿第一方向依次堆叠，所述第一方向为垂直于所述芯片的平面的方向；
每个所述芯片包括：
基底；
n个第一导电结构，沿第一方向贯穿所述基底，所述n大于或等于2；
其中，在所有芯片内的至少一组相对应的第一导电结构中，相邻两层所述芯片内的该组所述第一导电结构，在沿第一方向的投影不重叠。
在一些实施例中，还包括：
第一互连线，相邻两层所述芯片内的相对应的第一导电结构通过第一互连线连接。
在一些实施例中，所述n个第一导电结构位于同一圆周上；
在沿第一方向的投影中，相邻两层所述芯片内相对应的第一导电结构的投影不重叠。
在一些实施例中，相邻两层所述芯片内相对应的第一导电结构的投影分别与圆心的连线形成预设角度，所述预设角度的范围为30°～90°。
在一些实施例中，沿第一方向，每层所述芯片内相对应的第一导电结构沿预设方向，以预设角度旋转上升，其中，所述预设方向为顺时针方向或逆时针方向。
在一些实施例中，所述第一导电结构包括第一硅通孔和第一导电凸块，所述第一硅通孔位于所述第一导电凸块上，所述第一硅通孔沿第一方向贯穿所述基底，所述第一导电凸块位于相邻两层所述芯片之间。
在一些实施例中，所述第一导电凸块包括至少一个凹面，相邻所述第一导电凸块上的所述凹面相对设置。
在一些实施例中，所述第一互连线的一端与所述第一硅通孔连接，所述第一互连线的另一端与所述第一导电凸块连接。
在一些实施例中，每个所述芯片还包括：第二导电结构，位于所述n个第一导电结构形成的圆周的圆心处，且沿所述第一方向贯穿所述基底。
在一些实施例中，还包括：
第二互连线，相邻两层所述芯片内的所述第二导电结构通过所述第二互连线连接。
在一些实施例中，所述第一导电结构为信号导电结构，所述第二导电结构为虚拟导电结构。
根据本公开实施例的第二方面，提供了一种半导体结构的形成方法，包括：
沿第一方向形成多个依次堆叠的芯片，所述第一方向为垂直于所述芯片的平面的方向；
所述形成芯片，包括：
提供基底；
形成沿第一方向贯穿所述基底的n个第一导电结构，所述n大于或等于2；
其中，在所有芯片内的至少一组相对应的第一导电结构中，相邻两层所述芯片内的该组所述第一导电结构，在沿第一方向的投影不重叠。
在一些实施例中，还包括：
在形成每层芯片后，形成第一互连线，相邻两层所述芯片内的相对应的第一导电结构通过第一互连线连接。
在一些实施例中，所述n个第一导电结构位于同一圆周上；
在沿第一方向的投影中，相邻两层所述芯片内相对应的第一导电结构的投影不重叠。
在一些实施例中，所述形成芯片，还包括：
形成第二导电结构，所述第二导电结构位于所述n个第一导电结构形成的圆周的圆心处，且沿所述第一方向贯穿所述基底。
在一些实施例中，还包括：
形成第二互连线，相邻两层所述芯片内的所述第二导电结构通过所述第二互连线连接。
本公开实施例中，相邻两层芯片内相对应的第一导电结构的投影不重叠，说明相邻两层芯片内相对应的第一导电结构以一定角度错位设置，如此，同一个信号在多个芯片堆叠形成的结构内旋转上升，可以减少不同信号之间的串扰。同时优化了空间结构，可以形成更高带宽的存储器。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的半导体结构的结构示意图；
图2为本公开实施例提供的第一导电结构的立体图；
图3为本公开实施例提供的第一导电结构的结构示意图；
图4为相邻两层芯片之间通过第一互连线连接的示意图；
图5为本公开实施例提供的每层芯片的结构示意图；
图6为本公开另一实施例提供的半导体结构的透视图；
图7为本公开实施例提供的半导体结构的制备方法的流程图；
图8a至图9b为本公开实施例提供的半导体结构在制备过程中的结构示意图。
附图标记说明：
21-芯片；210-基底；
30-第一导电结构；31-第一导电凸块；311-第一焊盘；311a-第一子焊盘；311b-第二子焊盘；312-第一焊球；301-凹面；302-凸面；32-第一硅通孔；33-第一测试垫；300-初始第一导电结构；310-初始第一导电凸块；
40-第二导电结构；
61-第一掩膜层；
71-第一互连线；72-第二互连线。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
本公开实施例提供了一种半导体结构。图1为本公开实施例提供的半导体结构的结构示意图。
如图1所示，所述半导体结构，包括：
多个芯片21，多个所述芯片21沿第一方向依次堆叠，所述第一方向为垂直于所述芯片21的平面的方向；
每个所述芯片21包括：
基底210；
n个第一导电结构30，沿第一方向贯穿所述基底210，所述n大于或等于2；
其中，在所有芯片21内的至少一组相对应的第一导电结构30中，相邻两层所述芯片21内的该组所述第一导电结构30，在沿第一方向的投影不重叠。
本公开实施例中，相邻两层芯片内相对应的第一导电结构的投影不重叠，说明相邻两层芯片内相对应的第一导电结构以一定角度错位设置，如此，同一个信号在多个芯片堆叠形成的结构内旋转上升，可以减少不同信号之间的串扰。同时优化了空间结构，可以形成更高带宽的存储器。
在一实施例中，所述基底210可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
图2为本公开实施例提供的第一导电结构的立体图，图3为本公开实施例提供的第一导电结构的结构示意图。
在一实施例中，如图2和图3所示，所述第一导电结构30包括第一导电凸块31，所述第一导电凸块31包括至少一个凹面301，相邻所述第一导电凸块31上的所述凹面301相对设置。
本公开实施例中，当信号经过其中一个第一导电凸块时，由于边缘场辐射效应，导致其周围的其他第一导电凸块引入寄生的RLC，且与距离成反比，距离越远，边缘场辐射效应越弱，因此，通过将相邻的第一导电凸块的凹面相对设置，从而减弱边缘场在空间的交叠范围，从而减少有边缘场辐射带来的寄生参数。同时将第一导电凸块设置成包括至少一个凹面，如此，第一导电凸块的体积减小，从而减小了第一导电凸块本身的寄生电容。
在一实施例中，所述第一导电结构30呈四方排布，每个四方排布的多个所述第一导电结构30中，对角线位置处的两个所述第一导电结构30的第一导电凸块31的凹面301相对设置。
本实施例中，对角线位置处的第一导电凸块的凹面相对设置，如此， 第一导电凸块之间的距离增大，从而第一导电凸块之间的边缘场减小，进而减少了RLC寄生参数。
在一实施例中，参见图3，所述第一导电凸块31还包括至少一个凸面302，所述凸面302与所述凹面301相邻设置。通过设置凸面，便于第一导电结构后续进行焊接，保证第一导电凸块31的焊接质量。
在一实施例中，如图3所示，每个四方排布的对角线交点处至每个所述第一导电凸块31的凹面301的距离为第一距离h1，所述第一导电凸块31的凹面301至所述第一导电凸块31的中心的距离为第二距离h2，所述第一距离h1与所述第二距离h2的比值为5:3～5:2。
如果第一距离与第二距离的比值设置的过大，则说明第一导电凸块的凹面过于接近第一导电凸块的中心，如此，则会导致第一导电凸块的面积过小，影响第一导电凸块的导电性能；而如果第一距离和第二距离的比值设置的过小，则说明第一导电凸块的凹面接近对角线的交点处，如此，相邻第一导电凸块之间的距离减少，从而增大了寄生参数。因此，将第一距离和第二距离的比值设置成5:3～5:2，既保证了第一导电凸块的导电性能，又减少了寄生参数。
在一实施例中，如图2所示，所述第一导电结构30还包括第一硅通孔32和第一测试垫33，所述第一硅通孔32位于所述第一导电凸块31上，所述第一测试垫33位于所述第一硅通孔32和所述第一导电凸块31之间。
所述第一硅通孔和所述第一导电凸块保证了后续基板和芯片堆叠体之间的电连接，所述第一测试垫可用于测试功能。
所述第一硅通孔32内部的导电材料包括但不限于Cu，所述导电材料外面包裹了一层绝缘材料，所述绝缘材料包括但不限于SiO2。所述第一测试垫33的材料包括但不限于Al。
在一实施例中，如图3所示，所述第一导电凸块31包括第一焊盘311和第一焊球312，所述第一焊盘311位于所述第一焊球312上；其中，所述第一焊盘311在基板上的正投影位于所述第一焊球312在基板上的正投影内部。
如图2所示，所述第一焊盘311包括第一子焊盘311a和第二子焊盘311b，所述第一子焊盘311a位于所述第二子焊盘311b上；其中，所述第一子焊盘311a的体积小于所述第二子焊盘311b的体积。
在一些实施例中，在形成第一子焊盘311a和第二子焊盘311b时，先在第一测试垫上绝缘层，绝缘层覆盖第一测试垫，然后对绝缘层进行曝光，在第一测试垫上形成开口，也就是说开口的深度等于绝缘层在第一测试垫上的厚度，也就是说开口的宽度可以小于第一测试垫的宽度，从而使得第一子焊盘311a的体积较小，第二子焊盘311b的体积较大。如果在曝光时，想要形成较大宽度的开口，例如开口的宽度大于第一测试垫的宽度，则导致开口的深度增加，在曝光时则会受到漫反射的影响，导致曝光图形异常。 由此形成体积较小的第一子焊盘311a，形成较大体积的第一子焊盘311b。需要说明的是，第一子焊盘311a和第二子焊盘311b可以同时形成。
在一实施例中，所述相邻两层所述芯片21内的该组所述第一导电结构30，在沿第一方向的投影不重叠，包括：位于所述芯片21内的该组所述第一导电结构30的第一硅通孔32，在沿第一方向的投影不重叠。
在一实施例中，所述半导体结构还包括：第一互连线71，相邻两层所述芯片21内的相对应的第一导电结构30通过第一互连线71连接。通过在芯片中形成第一互连线71，从而实现第一导电结构30螺旋排列时的连接，从而保证信号正常传输。
具体地，如图4所示，例如每层芯片内可以包括4个第一导电结构30，分别为CH0、CH1、CH2和CH3，其中，每层芯片内对应的CH0通过第一互连线71连接，且以一定角度旋转上升，同时，CH1、CH2和CH3也是同样的通过第一互连线71连接，且以一定角度旋转上升。同一层内连接相对应的两个第一导电结构的第一互连线之间以一定角度偏转，因此减少了第一互连线彼此之间的正对面积，从而减少了第一互连线之间的串扰。
在一实施例中，所述第一互连线的一端与所述第一硅通孔连接，所述第一互连线的另一端与所述第一导电凸块连接。
所述第一互连线为金属线，如图4所示，包括金属线M0至M4。
如图4所示，所述第一互连线71的一端为M0，M0与其中一层芯片内的第一导电结构的第一硅通孔或第一导电凸块连接，则另一端M4与相邻芯片内相对应的第一导电结构的第一导电凸块或第一硅通孔连接，即一端与第一硅通孔连接，另一端就与第一导电凸块连接，反之亦然。其中，M0和M4之间通过M1、M2和M3连接。
需要解释的是，图4中M0连接的下层芯片中的CH0的端面与M4连接的上层芯片中的CH0的端面应在同一个水平面上，即第一互连线应平行于所述芯片的平面。
在一实施例中，所述n个第一导电结构30位于同一圆周上；在沿第一方向的投影中，相邻两层所述芯片21内相对应的第一导电结构30的投影不重叠。
在此实施例中，相邻两个芯片内所有相对应的第一导电结构的投影都不重叠，即所有的第一导电结构都以一定角度旋转上升，如此，最大程度的减少了不同信号之间的串扰。
在一实施例中，相邻两层所述芯片21内相对应的第一导电结构30的投影分别与圆心的连线形成预设角度，所述预设角度的范围为30°～90°。
更具体的，所述预设角度可以为45°。当预设角度为45°时，每一层芯片21内呈四方排布的第一导电结构30就只会有如图5所示的两种排布方式，即当奇数层的芯片21内的第一导电结构30如图5中stack1、stack3、stack5和stack7所示时，偶数层的芯片21内的第一导电结构30就会如图5 中stack2、stack4、stack6和stack8所示，反之亦然。如此，在保证缩短第一互连线的长度，减少串扰的同时，也降低了工艺的复杂度。同时，相邻两层芯片内的CH0不会正对设置，同理，相邻两层芯片内的CH1、CH2和CH3也不会正对设置，如此，减少了相邻芯片内相对应的第一导电结构的正对面积，从而降低了信号串扰和寄生电容。
如图1和图4所示，该半导体结构内的第一导电结构30(例如CH0和CH1)在堆叠方向上螺旋排列，而不是竖直排列，也就是相邻两层芯片内同一个第一导电结构30(例如CH0)的距离会增加。如果半导体结构内的第一导电结构30(例如CH0和CH1)竖直排列，则芯片(stack1至stack8)内的第一导电结构30均会由于边缘场效应产生信号串扰，同时由于第一导电结构30竖直排列，即相邻芯片(例如stack1至stack2)中相同的第一导电结构30距离较近，则会出现串扰效应的叠加，同时随着第一导电结构30形成的信号的长度越长，则串扰效应叠加效果更强，最终在顶层的芯片(stack8)中会导致信号发生畸变。
而本实施例中，由于第一导电结构30(例如CH0和CH1)螺旋排列，也就是相邻两层芯片内同一个第一导电结构30(例如CH0)的距离会增加，由此在同一个芯片(例如stack1)内当两个不同的信号发生串扰时，由于串扰效应不会叠加到另一个芯片(例如stack2)中，由此改善了串扰对信号的影响。
如图1和图4所示，第一导电结构30可以为硅通孔结构，CH0和CH1可以表示不同的硅通孔，也就是传输不同信号的硅通孔。
在一实施例中，沿垂直于所述基板10的平面的方向，每层所述芯片21内相对应的第一导电结构30沿预设方向，以预设角度旋转上升，其中，所述预设方向为顺时针方向或逆时针方向。
当每层所述芯片内相对应的第一导电结构只沿顺时针方向或逆时针方向旋转上升时，如此，每层内的第一互连线可以做成同样的结构，如此，减少了工艺难度。
在一实施例中，如图6所示，每个芯片21也可包括第二导电结构40，所述第二导电结构40位于所述n个第一导电结构30形成的圆周的圆心处，且沿所述第一方向贯穿所述基底210。
所述半导体结构还包括：第二互连线72，相邻两层所述芯片21内的所述第二导电结构40通过所述第二互连线72连接。在一些实施例中，第二互连线72例如包括焊垫和焊盘结构，从而实现第二导电结构40的连接。
通过在每层芯片内设置一个第二导电结构，且在此实施例中，第一导电结构为信号导电结构，第二导电结构为虚拟导电结构，如此，通过第二互连线连接的第二导电结构形成一个虚拟TSV通道，能够将每层芯片内的第一导电结构产生的热量散发出去，将散热方式变成向中心点传播散热，增加散热效率，提高器件性能。
本公开实施例还提供了一种半导体结构的制备方法，具体请参见附图7，如图所示，所述方法包括以下步骤：
步骤701：沿第一方向形成多个依次堆叠的芯片，所述第一方向为垂直于所述芯片的平面的方向；
所述形成芯片，包括：
提供基底；
形成沿第一方向贯穿所述基底的n个第一导电结构，所述n大于或等于2；
其中，在所有芯片内的至少一组相对应的第一导电结构中，相邻两层所述芯片内的该组所述第一导电结构，在沿第一方向的投影不重叠。
下面结合具体实施例对本公开实施例提供的半导体结构的制备方法再作进一步详细的说明。
图8a至图9b为本公开实施例提供的半导体结构在制备过程中的结构示意图。
先参见图8a至图8c，对第一导电结构的制备过程进行详细的说明。
所述形成第一导电结构30，包括：
形成初始第一导电结构300，所述初始第一导电结构300包括初始第一导电凸块310，所述初始第一导电凸块310的形状为圆形；
在每个所述初始第一导电凸块310上形成至少一个第一掩膜层61，所述第一掩膜层61覆盖部分所述初始第一导电凸块310的外围；
刻蚀去除所述初始第一导电凸块310被所述第一掩膜层61覆盖的部分，以形成第一导电结构30。
在一实施例中，所述第一掩膜层61的形状为圆形，以使所述初始第一导电凸块310被去除部分后形成的第一导电凸块包括至少一个凹面。
可以理解的是，所述第一掩膜层也可为其他弧形结构。
在一实施例中，所述第一导电结构30呈四方排布，每个四方排布的多个所述第一导电结构30中，对角线位置处的两个所述第一导电结构30的第一导电凸块31的凹面301相对设置。
本实施例中，对角线位置处的第一导电凸块的凹面相对设置，如此，第一导电凸块之间的距离增大，从而第一导电凸块之间的边缘场减小，进而减少了RLC寄生参数。
在一实施例中，参见图8c，所述第一导电凸块31还包括至少一个凸面302，所述凸面302与所述凹面301相邻设置。通过设置凸面，便于第一导电结构后续进行焊接，保证第一导电凸块31的焊接质量。
在一实施例中，如图8c所示，每个四方排布的对角线交点处至每个所述第一导电凸块31的凹面301的距离为第一距离h1，所述第一导电凸块31的凹面301至所述第一导电凸块31的中心的距离为第二距离h2，所述第一距离h1与所述第二距离h2的比值为5:3～5:2。
如果第一距离与第二距离的比值设置的过大，则说明第一导电凸块的凹面过于接近第一导电凸块的中心，如此，则会导致第一导电凸块的面积过小，影响第一导电凸块的导电性能；而如果第一距离和第二距离的比值设置的过小，则说明第一导电凸块的凹面接近对角线的交点处，如此，相邻第一导电凸块之间的距离减少，从而增大了寄生参数。因此，将第一距离和第二距离的比值设置成5:3～5:2，既保证了第一导电凸块的导电性能，又减少了寄生参数。
在一实施例中，如图2所示，所述第一导电结构30还包括第一硅通孔32和第一测试垫33，所述第一硅通孔32位于所述第一导电凸块31上，所述第一测试垫33位于所述第一硅通孔32和所述第一导电凸块31之间。
所述第一硅通孔和所述第一导电凸块保证了后续基板和芯片堆叠体之间的电连接，所述第一测试垫可用于测试功能。
所述第一硅通孔32内部的导电材料包括但不限于Cu，所述导电材料外面包裹了一层绝缘材料，所述绝缘材料包括但不限于SiO2。所述第一测试垫33的材料包括但不限于Al。
在一实施例中，如图8c所示，所述第一导电凸块31包括第一焊盘311和第一焊球312，所述第一焊盘311位于所述第一焊球312上；其中，所述第一焊盘311在所述基板10上的正投影位于所述第一焊球312在所述基板10上的正投影内部。
如图2所示，所述第一焊盘311包括第一子焊盘311a和第二子焊盘311b，所述第一子焊盘311a位于所述第二子焊盘311b上；其中，所述第一子焊盘311a的体积小于所述第二子焊盘311b的体积。
所述第一子焊盘与第一测试垫连接，因此第一子焊盘的体积较小，可以减少与第一测试垫的接触面积，进而减少接触电阻。
接下来，参见图9a和图9b，可以将上述方法中制备形成的芯片堆叠体中芯片的连接方式进行改进，进一步减少RLC寄生参数。
先参见图9a，执行步骤701，沿第一方向形成多个依次堆叠的芯片21，所述第一方向为垂直于所述芯片21的平面的方向；所述形成芯片21，包括：提供基底210；形成沿第一方向贯穿所述基底210的n个第一导电结构30，所述n大于或等于2；其中，在所有芯片21内的至少一组相对应的第一导电结构30中，相邻两层所述芯片21内的该组所述第一导电结构30，在沿第一方向的投影不重叠。
在一实施例中，所述基底210可以为硅衬底、锗衬底、硅锗衬底、碳化硅衬底、SOI(绝缘体上硅，Silicon On Insulator)衬底或GOI(绝缘体上锗，Germanium On Insulator)衬底等，还可以为包括其他元素半导体或化合物半导体的衬底，例如玻璃衬底或III-V族化合物衬底(例如氮化镓衬底或砷化镓衬底等)，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
在一实施例中，所述相邻两层所述芯片21内的该组所述第一导电结构30，在沿第一方向的投影不重叠，包括：位于所述芯片21内的该组所述第一导电结构30的第一硅通孔32，在沿第一方向的投影不重叠。
继续参见图9a，所述方法还包括：在形成每层芯片21后，形成第一互连线71，相邻两层所述芯片21内的相对应的第一导电结构30通过第一互连线71连接。
具体地，如图4所示，例如每层芯片内可以包括4个第一导电结构30，分别为CH0、CH1、CH2和CH3，其中，每层芯片内对应的CH0通过第一互连线71连接，且以一定角度旋转上升，同时，CH1、CH2和CH3也是同样的通过第一互连线71连接，且以一定角度旋转上升。同一层内连接相对应的两个第一导电结构的第一互连线之间以一定角度偏转，因此减少了第一互连线彼此之间的正对面积，从而减少了第一互连线之间的串扰。
在一实施例中，所述第一互连线的一端与所述第一硅通孔连接，所述第一互连线的另一端与所述第一导电凸块连接。
所述第一互连线为金属线，如图4所示，包括金属线M0至M4。
如图4所示，所述第一互连线71的一端为M0，M0与其中一层芯片内的第一导电结构的第一硅通孔或第一导电凸块连接，则另一端M4与相邻芯片内相对应的第一导电结构的第一导电凸块或第一硅通孔连接，即一端与第一硅通孔连接，另一端就与第一导电凸块连接，反之亦然。其中，M0和M4之间通过M1、M2和M3连接。
需要解释的是，图4中M0连接的下层芯片中的CH0的端面与M4连接的上层芯片中的CH0的端面应在同一个水平面上，即第一互连线应平行于所述芯片的平面。
在一实施例中，所述n个第一导电结构30位于同一圆周上；在沿第一方向的投影中，相邻两层所述芯片21内相对应的第一导电结构30的投影不重叠。
在此实施例中，相邻两个芯片内所有相对应的第一导电结构的投影都不重叠，即所有的第一导电结构都以一定角度旋转上升，如此，最大程度的减少了不同信号之间的串扰。
在一实施例中，相邻两层所述芯片21内相对应的第一导电结构30的投影分别与圆心的连线形成预设角度，所述预设角度的范围为30°～90°。
更具体的，所述预设角度可以为45°。当预设角度为45°时，每一层芯片21内呈四方排布的第一导电结构30就只会有如图5所示的两种排布方式，即当奇数层的芯片21内的第一导电结构30如图5中stack1、stack3、stack5和stack7所示时，偶数层的芯片21内的第一导电结构30就会如图5中stack2、stack4、stack6和stack8所示，反之亦然。如此，在保证缩短第一互连线的长度，减少串扰的同时，也降低了工艺的复杂度。同时，相邻两层芯片内的CH0不会正对设置，同理，相邻两层芯片内的CH1、CH2和 CH3也不会正对设置，如此，减少了相邻芯片内相对应的第一导电结构的正对面积，从而降低了信号串扰和寄生电容。
在一实施例中，沿垂直于所述基板10的平面的方向，每层所述芯片21内相对应的第一导电结构30沿预设方向，以预设角度旋转上升，其中，所述预设方向为顺时针方向或逆时针方向。
当每层所述芯片内相对应的第一导电结构只沿顺时针方向或逆时针方向旋转上升时，如此，每层内的第一互连线可以做成同样的结构，如此，减少了工艺难度。
接着，参见图9b，所述形成芯片21还包括：
形成第二导电结构40，所述第二导电结构40位于所述n个第一导电结构30形成的圆周的圆心处，且沿所述第一方向贯穿所述基底210。
所述方法还包括：形成第二互连线72，相邻两层所述芯片21内的所述第二导电结构40通过所述第二互连线72连接。
通过在每层芯片内设置一个第二导电结构，且在此实施例中，第一导电结构为信号导电结构，第二导电结构为虚拟导电结构，如此，通过第二互连线连接的第二导电结构形成一个虚拟TSV通道，能够将每层芯片内的第一导电结构产生的热量散发出去，将散热方式变成向中心点传播散热，增加散热效率，提高器件性能。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例中，相邻两层芯片内相对应的第一导电结构的投影不重叠，说明相邻两层芯片内相对应的第一导电结构以一定角度错位设置，如此，同一个信号在多个芯片堆叠形成的结构内旋转上升，可以减少不同信号之间的串扰。同时优化了空间结构，可以形成更高带宽的存储器。

Claims (16)

  1. 一种半导体结构，包括：
    多个芯片，多个所述芯片沿第一方向依次堆叠，所述第一方向为垂直于所述芯片的平面的方向；
    每个所述芯片包括：
    基底；
    n个第一导电结构，沿第一方向贯穿所述基底，所述n大于或等于2；
    其中，在所有芯片内的至少一组相对应的第一导电结构中，相邻两层所述芯片内的该组所述第一导电结构，在沿第一方向的投影不重叠。
  2. 根据权利要求1所述的半导体结构，其中，还包括：
    第一互连线，相邻两层所述芯片内的相对应的第一导电结构通过第一互连线连接。
  3. 根据权利要求1所述的半导体结构，其中，
    所述n个第一导电结构位于同一圆周上；
    在沿第一方向的投影中，相邻两层所述芯片内相对应的第一导电结构的投影不重叠。
  4. 根据权利要求3所述的半导体结构，其中，
    相邻两层所述芯片内相对应的第一导电结构的投影分别与圆心的连线形成预设角度，所述预设角度的范围为30°～90°。
  5. 根据权利要求4所述的半导体结构，其中，
    沿第一方向，每层所述芯片内相对应的第一导电结构沿预设方向，以预设角度旋转上升，其中，所述预设方向为顺时针方向或逆时针方向。
  6. 根据权利要求2所述的半导体结构，其中，
    所述第一导电结构包括第一硅通孔和第一导电凸块，所述第一硅通孔位于所述第一导电凸块上，所述第一硅通孔沿第一方向贯穿所述基底，所述第一导电凸块位于相邻两层所述芯片之间。
  7. 根据权利要求6所述的半导体结构，其中，
    所述第一导电凸块包括至少一个凹面，相邻所述第一导电凸块上的所述凹面相对设置。
  8. 根据权利要求6所述的半导体结构，其中，
    所述第一互连线的一端与所述第一硅通孔连接，所述第一互连线的另一端与所述第一导电凸块连接。
  9. 根据权利要求3所述的半导体结构，其中，
    每个所述芯片还包括：第二导电结构，位于所述n个第一导电结构形成的圆周的圆心处，且沿所述第一方向贯穿所述基底。
  10. 根据权利要求9所述的半导体结构，其中，还包括：
    第二互连线，相邻两层所述芯片内的所述第二导电结构通过所述第二 互连线连接。
  11. 根据权利要求9所述的半导体结构，其中，
    所述第一导电结构为信号导电结构，所述第二导电结构为虚拟导电结构。
  12. 一种半导体结构的形成方法，包括：
    沿第一方向形成多个依次堆叠的芯片，所述第一方向为垂直于所述芯片的平面的方向；
    所述形成芯片，包括：
    提供基底；
    形成沿第一方向贯穿所述基底的n个第一导电结构，所述n大于或等于2；
    其中，在所有芯片内的至少一组相对应的第一导电结构中，相邻两层所述芯片内的该组所述第一导电结构，在沿第一方向的投影不重叠。
  13. 根据权利要求12所述的方法，其中，还包括：
    在形成每层芯片后，形成第一互连线，相邻两层所述芯片内的相对应的第一导电结构通过第一互连线连接。
  14. 根据权利要求12所述的方法，其中，
    所述n个第一导电结构位于同一圆周上；
    在沿第一方向的投影中，相邻两层所述芯片内相对应的第一导电结构的投影不重叠。
  15. 根据权利要求14所述的方法，其中，
    所述形成芯片，还包括：
    形成第二导电结构，所述第二导电结构位于所述n个第一导电结构形成的圆周的圆心处，且沿所述第一方向贯穿所述基底。
  16. 根据权利要求15所述的方法，其中，还包括：
    形成第二互连线，相邻两层所述芯片内的所述第二导电结构通过所述第二互连线连接。
PCT/CN2022/123998 2022-09-19 2022-10-09 一种半导体结构及其制备方法 WO2024060320A1 (zh)

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JP2007235176A (ja) * 1994-05-13 2007-09-13 Hitachi Ltd 多層配線基板とそれを用いた半導体装置
CN102751261A (zh) * 2011-04-20 2012-10-24 南亚科技股份有限公司 芯片堆叠封装结构
CN102915996A (zh) * 2011-08-03 2013-02-06 矽品精密工业股份有限公司 用于3d集成电路的电性互连机构
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CN112670266A (zh) * 2019-10-15 2021-04-16 爱思开海力士有限公司 包括层叠的半导体芯片的半导体封装

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JP2007235176A (ja) * 1994-05-13 2007-09-13 Hitachi Ltd 多層配線基板とそれを用いた半導体装置
CN102751261A (zh) * 2011-04-20 2012-10-24 南亚科技股份有限公司 芯片堆叠封装结构
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