TW202234607A - 用於半導體元件的封裝結構 - Google Patents

用於半導體元件的封裝結構 Download PDF

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TW202234607A
TW202234607A TW110115464A TW110115464A TW202234607A TW 202234607 A TW202234607 A TW 202234607A TW 110115464 A TW110115464 A TW 110115464A TW 110115464 A TW110115464 A TW 110115464A TW 202234607 A TW202234607 A TW 202234607A
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semiconductor wafer
underfill
interposer substrate
substrate
semiconductor
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TW110115464A
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TWI769800B (zh
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李宗彥
汪金華
游明志
林柏堯
鄭心圃
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台灣積體電路製造股份有限公司
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Publication of TW202234607A publication Critical patent/TW202234607A/zh

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Abstract

本發明的實施例提供一種包括有機中介層基板、半導體晶片、導電凸塊、底部填充膠及絕緣封裝體的封裝結構。有機中介層基板包括堆疊的有機介電層及嵌置在堆疊的有機介電層中的導線。半導體晶片設置在有機中介層基板的導線之上且電連接到有機中介層基板的導線，且半導體晶片包括倒角的邊緣。導電凸塊設置在半導體晶片與有機中介層基板之間，且半導體晶片經由導電凸塊電連接到有機中介層基板。底部填充膠設置在半導體晶片與有機中介層基板之間，其中底部填充膠將導電凸塊封裝且接觸半導體晶片的倒角的邊緣。絕緣封裝體覆蓋有機中介層基板且在側向上將半導體晶片及底部填充膠封裝。

Description

用於半導體元件的封裝結構
由於各種電子元件（例如，電晶體、二極體、電阻器、電容器等）的積體密度不斷提高，半導體行業已經歷了迅速增長。在大多數情況下，積體密度的改進是由於最小特徵尺寸的持續減小，因此允許將更多元件聚集到特定區域中。隨著近來對小型化、更高的速度及更大的頻寬以及較低的功耗與等待時間的需求增加，對更小且更具創造性的半導體晶片封裝技術的需要也增加。目前，晶圓級封裝（Chip-on-Wafer-on-Substrate，CoWoS）（或基板上覆晶圓上覆晶片）的封裝結構因其多功能及高性能而越來越受青睞。然而，與CoWoS封裝結構的封裝製程有關的挑戰（例如，翹曲問題）仍然存在。
本發明提供用於實施本發明的不同特徵的許多不同實施例或實施例。以下闡述組件、數值、運算、材料、佈置或類似物及排列的具體實施例以簡化本發明。當然，該些僅為實施例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本發明可能在各種實施例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於…之下（beneath）」、「位於…下方（below）」、「下部的（lower）」、「位於…上方（above）」、「上部的（upper）」等空間相對性用語來闡述圖中所例示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或運算中的不同定向。設備可具有其他定向（旋轉90度或處於其他定向），且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
本發明還可包括其他特徵及製程。舉例來說，可包括測試結構以説明對三維（three-dimensional，3D）封裝或三維積體電路（three-dimensional integrated circuit，3DIC）元件進行驗證測試。所述測試結構可例如包括形成在重佈線層中或在基板上的測試接點，以使得能夠對三維封裝或三維積體電路進行測試、使用探針和/或探針卡（probe card）等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可與包括對已知良好晶片（known good die）進行中間驗證的測試方法結合使用以提高良率並降低成本。
圖1A到圖1C是示意性地說明根據本公開的一些實施例的半導體晶片的製作製程的剖視圖。
參考圖1A，提供半導體晶圓W1。半導體晶圓W1可包括通過半導體晶圓W1的前段製程（front end of line，FEOL）製作流程形成的各種摻雜區（例如，p型摻雜區或n型摻雜區）。摻雜區可摻雜有p型摻雜劑和/或n型摻雜劑。摻雜區可摻雜有例如硼或BF 2等p型摻雜劑、例如磷或砷等n型摻雜劑和/或其組合。摻雜區可被配置成n型鰭式場效電晶體（Fin Field Effect Transistor，FinFET）、p型FinFET或其組合。在一些其他實施例中，摻雜區可被配置成n型金屬氧化物半導體場效電晶體（Metal Oxide Semiconductor Field Effect Transistor，MOSFET）、p型MOSFET或其組合。半導體晶圓W1可包括半導體基板110及內連結構120，其中內連結構120設置在半導體基板110上。在一些實施例中，半導體基板110包括晶體矽基板。在一些替代實施例中，半導體基板110由以下材料製成：一些其他適合的元素半導體，例如金剛石或鍺；適合的化合物半導體，例如砷化鎵、碳化矽、砷化銦或磷化銦；或適合的合金半導體，例如碳化矽鍺、磷化鎵砷或鎵磷化銦。
內連結構120可包括交替堆疊的內連配線（例如，銅內連配線）及介電層，其中內連結構120的內連配線電連接到半導體基板110中的主動元件和/或被動元件。內連結構120是通過半導體晶圓W1的後段製程（back end of line，BEOL）製作流程形成。內連結構120的最頂部內連配線可包括導電接點122，且導電接點122可以是鋁接點、銅接點或其他適合的金屬接點。內連結構120還可包括鈍化層（未示出），所述鈍化層設置在半導體晶圓W1的前表面或主動表面上，其中導電接點122被鈍化層部分地覆蓋。換句話說，導電接點122從定義在鈍化層中的開口部分地露出。鈍化層可以是通過其他適合的無機介電材料形成的氧化矽層、氮化矽層、氮氧化矽層或介電層。內連結構120還可包括形成在鈍化層之上的後鈍化層（未示出），其中所述後鈍化層覆蓋鈍化層及導電接點122，所述後鈍化層包括接觸開口，且導電接點122從定義在鈍化後層中的接觸開口部分地露出。後鈍化層可以是通過其他適合的有機介電材料形成的聚醯亞胺（polyimide，PI）層、聚苯並噁唑（polybenzoxazole，PBO）層或介電層。在一些替代實施例中，省略後鈍化層。
在一些實施例中，對半導體晶圓W1的內連結構120執行晶圓級凸塊連接（wafer level bumping process）製程，以使得在導電接點122上形成導電端子124。內連結構120的導電接點122可以是凸塊接點，且導電端子124可以是搭接在導電接點122上的微凸塊。晶圓級凸塊連接製程可包括：在半導體晶圓W1的前表面或主動表面之上形成圖案化的光阻，其中所述圖案化的光阻包括顯露出導電接點122的開口；將導電材料沉積（例如，鍍覆）在導電接點122上以在定義在圖案化的光阻中的開口中形成導電端子124；及移除圖案化的光阻。在一些實施例中，導電端子124可包括Cu/Ni/Au凸塊、Cu/Ni凸塊、Cu/Ni/Au/SnAg凸塊、Cu/Ni/SnAg凸塊等。
如圖1A中所說明，在形成導電端子124之後，執行斜切製程以在半導體晶圓W1的前表面上形成V形凹口G。可通過沿著半導體晶圓W1的切割道執行晶圓切割製程來形成V形凹口G。V形凹口G可通過V形切割刀片B1形成。在一些實施例中，V形凹口G的深度小於內連結構120的厚度，其中V形凹口G的深度介於約5微米到約20微米的範圍內，且V形凹口G的寬度介於約10微米到約100微米的範圍內。在一些替代實施例中，V形凹口G的深度大於內連結構120的厚度，其中V形凹口G的深度介於約20微米到約700微米的範圍內，且V形凹口G的寬度介於約100微米到約1000微米的範圍內。
參考圖1B及圖1C，在執行斜切製程之後，沿著半導體晶圓W1的前表面上的V形凹口G執行全切製程，以使得獲得單體化的半導體晶片100。在一些實施例中，每一單體化的半導體晶片100包括半導體基板110a、設置在半導體基板110a上的內連結構120a、導電接點122及導電端子124。在一些實施例中，每一單體化的半導體晶片100包括倒角的邊緣CE，且倒角的邊緣CE分佈在每一半導體晶片100的前表面的周邊區處。在一些替代實施例中，倒角的邊緣CE分佈在面向支撐基板的半導體晶片100的側壁處。可通過切割刀片B2沿著形成在半導體晶圓W1上的第一V形凹口G1執行全切製程。切割刀片B2的寬度小於V形凹口G的寬度。在一些實施例中，在執行全切製程之前將半導體晶圓W1貼合到切割條帶（未示出）上。
在半導體晶片100的俯視圖中，如圖7A到圖7E中所說明，至少一個倒角的邊緣CE分佈在半導體晶片100的一個或多個側壁處。如圖7A中所說明，僅一個倒角的邊緣CE沿著半導體晶片100的一個側壁分佈。如圖7B中所說明，兩個毗連的倒角的邊緣CE沿著半導體晶片100的兩個鄰近的側壁分佈。如圖7C中所說明，兩個倒角的邊緣CE沿著半導體晶片100的兩個相對的側壁分佈。如圖7D中所說明，三個毗連的倒角的邊緣CE沿著半導體晶片100的三個鄰近的側壁分佈。如圖7E中所說明，四個毗連的倒角的邊緣CE沿著半導體晶片100的四個側壁分佈。
圖2A到圖2D是示意性地說明根據本公開的一些替代實施例的半導體晶片的製作流程的剖視圖。
參考圖2A到圖2D以及圖1A到圖1C，圖2A到圖2D中所說明的製作流程類似於圖1A到圖1C中所說明的製作流程，但在全切製程之前執行兩次斜切製程。如圖2A及圖2B中所說明，執行第一斜切製程以在半導體晶圓W1的前表面上形成第一V形凹口G1。在形成第一V形凹口之後，沿著第一V形凹口G1執行第二斜切製程以在半導體晶圓W1的前表面上形成第二V形凹口G2。可通過沿著半導體晶圓W1的切割道執行兩次晶圓切割製程來形成第一V形凹口G1及第二V形凹口G2。第一V形凹口G1可通過V形切割刀片B1形成，且第二V形凹口G2可通過另一V形切割刀片B1’形成。第二V形凹口G2的深度大於第一V形凹口G1的深度，且第一V形凹口G1的寬度大於第二V形凹口G2的寬度。在一些實施例中，第一V形凹口G1的深度介於約5微米到約700微米的範圍內，第一V形凹口G1的寬度介於約10微米到約1000微米的範圍內，第二V形凹口G2的深度介於約5微米到約700微米的範圍內，且第二V形凹口G2的寬度介於約10微米到約900微米的範圍內。
參考圖2C及圖2D，在執行第一斜切製程及第二斜切製程之後，沿著分佈在半導體晶圓W1的前表面上的第一V形凹口G1及第二V形凹口G2執行全切製程，以使得獲得單體化的半導體晶片100a。在一些實施例中，每一單體化的半導體晶片100a包括半導體基板110a、設置在半導體基板110a上的內連結構120a、導電接點122及導電端子124。在一些實施例中，每一單體化的半導體晶片100a包括倒角的邊緣CE’，且倒角的邊緣CE’分佈在每一半導體晶片100a的前表面的周邊區域處。可通過切割刀片B2沿著形成在半導體晶圓W1上的第一V形凹口G1及第二V形凹口G2執行全切製程。切割刀片B2的寬度小於第一V形凹口G1的寬度及第二V形凹口G2的寬度。在一些實施例中，在執行全切製程之前將半導體晶圓W1貼合到切割條帶（未示出）上。
圖3A到圖3G是示意性地說明根據本公開的一些實施例的晶圓級封裝（CoWoS）結構的製作製程的剖視圖。
參考圖3A到圖3C，提供載體C且在載體C之上形成有機中介層基板210。在一些實施例中，在晶圓式載體C（例如，矽晶圓）之上形成晶圓式有機中介層基板210。有機中介層基板210可包括堆疊的有機介電層212及位於堆疊的有機介電層212之間的導線214。堆疊的有機介電層212堆疊在載體C之上。導線214嵌置在由載體C承載的堆疊的有機介電層212中。在一些實施例中，堆疊的有機介電層212的熱膨脹係數大於半導體晶片100的半導體基板110的熱膨脹係數。
如圖3A中所說明，在載體C之上形成第一有機介電層212a。第一有機介電層212a可包括開口，且載體C的一些部分通過定義在第一有機介電層212a中的開口而露出。在一些實施例中，第一有機介電層212a的材料包括聚苯並噁唑（polybenzoxazole，PBO）、聚醯亞胺（polyimide，PI）或其他適合的聚合物介電材料。在一些替代實施例中，第一有機介電層212a的材料包括混合有填充物的樹脂。可通過光可圖案化材料形成第一有機介電層212a並通過光刻製程將第一有機介電層212a圖案化。
如圖3B中所說明，在載體C之上形成晶種層S以覆蓋第一有機介電層212a及載體C當中通過定義在第一有機介電層212a中的開口所顯露出的部分。晶種層S可以是完全覆蓋第一介電層112a的濺鍍Ti/Cu晶種層。在形成晶種層S之後，在晶種層S上形成圖案化的光阻層PR。圖案化的光阻層PR包括溝槽，且定義在圖案化的光阻層PR中的溝槽露出晶種層S的一些部分。在晶種層S上形成圖案化的光阻層PR之後，可使用圖案化的光阻層PR作為光罩來執行鍍覆製程，以使得在溝槽中鍍覆第一導線214a且第一導線214a覆蓋晶種層S的露出部分。
在形成第一導線214a之後，移除圖案化的光阻層PR，以露出晶種層當中的未被第一導線214a覆蓋的部分，且在第一導線214a之下形成圖案化的晶種層S’。可執行蝕刻製程以移除晶種層S’當中的未被第一導線214a覆蓋的部分，直到露出第一有機介電層212a的一些部分為止。如圖3B中所說明，第一導線214a及圖案化的晶種層S’可被視作導線層。
如圖3C中所說明，在形成第一有機介電層212a及第一導線214a之後，可在載體C之上形成第二有機介電層212b、第二導線214b、第三有機介電層212c、第三導線214c及第四有機介電層212d，以使得形成有機中介層基板210。第二有機介電層212b、第三有機介電層212c及第四有機介電層212d的製作製程可類似於第一有機介電層212a的製作流程。第二導線214b及第三導線214c的製作流程可類似於第一導線214a的製作流程。可根據產品的設計規則修改有機中介層基板210中的堆疊的有機介電層212及導線214的數目。導線214可包括導線214及電連接在所述導線214之間的導通孔，其中所述導線可在水平方向上傳輸訊號，且所述導通孔可在垂直方向上傳輸訊號。導線214的材料可包含銅或其他適合的金屬材料。
參考圖3D，在於載體C之上形成有機中介層基板210之後，提供至少一個半導體晶片100（圖1C中所示）及至少一個半導體元件220，並通過例如晶圓上覆晶片（chip-on-wafer，CoW）接合製程將至少一個半導體晶片100及至少一個半導體元件220安裝到有機中介層基板210上。至少一個半導體晶片100及至少一個半導體元件220經由凸塊接點電連接到有機中介層基板210。半導體晶片100的導電端子124及至少一個半導體元件220的導電端子222可電連接到有機中介層基板210的第三導線214c。在一些實施例中，導電端子124包括Cu/Ni/Au凸塊、Cu/Ni凸塊、Cu/Ni/Au/SnAg凸塊、Cu/Ni/SnAg凸塊等，且導電端子222包括Cu/Ni/Au凸塊、Cu/Ni凸塊、Cu/Ni/Au/SnAg凸塊、Cu/Ni/SnAg凸塊等。導電端子124的結構可與導電端子222的結構相同或不同。所述至少一個半導體晶片100可包括邏輯晶片，且所述至少一個半導體元件220可包括記憶體元件。在一些替代實施例中，所述至少一個半導體晶片100包括系統單晶片（system-on-chip，SOC）邏輯晶片，且所述至少一個半導體元件220包括高頻寬記憶體（high bandwidth memory，HBM）立方體，其中HBM立方體至少包括堆疊的記憶體晶片。在一些替代實施例中，半導體晶片100可包括系統整合晶片（system-on-integrated-chip，SoIC）結構或專用積體電路（application specific integrated circuit，ASIC）晶片。
參考圖3E，在有機中介層基板210之上形成底部填充膠230。底部填充膠230填充有機中介層基板210與半導體晶片100之間的空間以及有機中介層基板210與半導體元件220之間的空間，以使得底部填充膠230在側向上將導電端子124及導電端子222封裝。底部填充膠230可用作應力緩衝件以提高導電端子124及222的可靠性。因此，可確保有機中介層基板210與半導體晶片100之間的電連接以及有機中介層基板210與半導體元件220之間的電連接。
如圖3E中所說明，在有機中介層基板210上形成絕緣封裝體240以覆蓋半導體晶片100、半導體元件220及底部填充膠230。可通過包覆模塑製程或膜沉積製程形成絕緣封裝體240。在執行用於形成絕緣封裝體240的包覆模塑製程或膜沉積製程之後，如圖3E中所說明，可執行研磨製程以部分地移除絕緣封裝體240。在執行研磨製程之後，絕緣封裝體240的厚度會減少。在執行研磨製程之後，半導體晶片100、半導體元件220及底部填充膠230會顯露出來。在一些實施例中，研磨製程包括機械研磨製程、化學機械研磨（Chemical Mechanical Polishing，CMP）製程或其組合。舉例來說，絕緣封裝體240的材料包括環氧樹脂模塑化合物或其他適合的介電材料。
參考圖3E及圖3F，執行移除製程以從有機中介層基板210移除載體C，以使得露出有機中介層基板210的後表面。在一些實施例中，載體C的移除製程包括機械研磨製程、CMP製程、蝕刻製程、其組合或其他適合的移除製程。在對載體C執行移除製程之後，對有機中介層基板210執行晶圓級凸塊連接製程，以使得在有機中介層基板210的第一導線214a上形成導電端子250。上述晶圓級凸塊連接製程可包括：在有機中介層基板210的後表面之上形成圖案化的光阻，其中所述圖案化的光阻包括用於顯露出第一導線214a的開口；在第一導線214a上沉積（例如，鍍覆）導電材料以在定義在圖案化的光阻中的開口中形成導電端子250；及移除圖案化的光阻。在一些實施例中，導電端子250可包括覆晶接合（controlled collapse chip connection，C4）凸塊等。
如圖3E及圖3F中所說明，沿著切割道SL執行單體化製程以將圖3E中所說明的結構單體化。在上述單體化製程期間，沿著切割道SL切斷有機中介層基板210及絕緣封裝體240。
參考圖3F及圖3G，在執行單體化製程之後，獲得單體化的結構並將所述單體化的結構倒置到電路基板270（例如，印刷電路板）的上表面上，所述單體化的結構包括有機中介層基板210、具有倒角的邊緣CE的半導體晶片100、半導體元件220、導電端子（例如，凸塊）124及導電端子（例如，凸塊）222、底部填充膠230、絕緣封裝體240a及導電端子250。單體化的結構的有機中介層基板210經由導電端子250電連接到電路基板270。可執行回焊製程以對導電端子250進行回焊，並將單體化結構的有機中介層基板210與電路基板270接合。然後，在電路基板270之上形成底部填充膠260。底部填充膠260填充有機中介層基板210與電路基板270之間的空間，以使得底部填充膠260在側向上將導電端子250封裝。底部填充膠260可作為應力緩衝件以提升導電端子250的可靠性。因此，可確保有機中介層基板210與電路基板270之間的電性連接。
絕緣封裝體240a覆蓋有機中介層基板210且在側向上將半導體晶片100及底部填充膠230封裝。在一些實施例中，絕緣封裝體240a的側壁與有機中介層基板210的側壁實質上對齊。絕緣封裝體240a的頂表面可與半導體晶片100的後表面及半導體元件220的後表面實質上切齊。在一些實施例中，電路基板270還包括分佈在其底表面上的導電端子272。導電端子272可以是球柵陣列（ball grid array，BGA）球。導電端子272的材料可包括焊料材料等。
如圖3G中所說明，底部填充膠230在側向上將導電端子124及導電端子222封裝，且底部填充膠230與半導體晶片100的倒角的邊緣CE直接接觸。由於半導體晶片100包括倒角的邊緣CE（例如，斜表面），因此可改善底部填充膠230與半導體晶片100之間的應力問題。下麵參照圖4A到圖4D、圖5A到圖5D及圖6A到圖6C闡述倒角的邊緣CE的細節。
圖4A到圖4D是示意性地說明根據本公開的一些實施例的各種倒角的邊緣或被修圓的邊緣的剖視圖。
參考圖4A，倒角的邊緣CE的寬度D可介於約5微米到約500微米的範圍內，且倒角的邊緣CE的高度H可介於約5微米到約700微米的範圍內。在一些實施例中，倒角的邊緣CE中的至少一個倒角的邊緣包括在半導體晶片100的根表面RS（半導體晶片100的側壁）與半導體晶片100的前表面FS之間延伸的傾斜表面（例如，斜表面）SS。底部填充膠230與半導體晶片100的根表面RS的一部分、半導體晶片100的傾斜表面SS及半導體晶片100的前表面FS直接接觸。倒角的邊緣CE的傾斜表面SS通過底部填充膠230與絕緣封裝體240a（圖3G中所示）而被間隔開。換句話說，倒角的邊緣CE的傾斜表面SS與絕緣封裝體240a（圖3G中所示）不會接觸。倒角的邊緣CE的傾斜表面SS與半導體晶片100的前表面FS之間的外角θ1可介於約5度到約80度的範圍以內。
參考圖4B，倒角的邊緣CE的寬度D可介於約5微米到約500微米的範圍以內，且倒角的邊緣CE的高度H可介於約5微米到約700微米的範圍以內。在一些實施例中，倒角的邊緣CE中的至少一個倒角的邊緣包括兩個連接的傾斜表面（例如，斜表面）SS1及SS2，所述兩個連接的傾斜表面SS1及SS2在半導體晶片100的根表面RS（半導體晶片100的側壁）與半導體晶片100的前表面FS之間延伸。底部填充膠230與半導體晶片100的根表面RS的一部分、半導體晶片100的倒角的邊緣CE的傾斜表面SS1及SS2及半導體晶片100的前表面FS直接接觸。倒角的邊緣CE的傾斜表面SS1及SS2通過底部填充膠230與絕緣封裝體240a（圖3G中所示）而被間隔開。換句話說，倒角的邊緣CE的傾斜表面SS1及SS2與絕緣封裝體240a（圖3G中所示）不會接觸。倒角的邊緣CE的傾斜表面SS1與半導體晶片100的前表面FS之間的外角θ1可介於約5度到約85度的範圍內，且半導體晶片100的倒角的邊緣CE的傾斜表面SS2與和半導體晶片100的前表面FS平行的虛擬平面VP1之間的外角θ2可介於約5度到約85度的範圍以內。外角θ2大於外角θ1。
參考圖4C，倒角的邊緣CE的寬度D可介於約5微米到約500微米的範圍以內，且倒角的邊緣CE的高度H可介於約5微米到約700微米的範圍以內。在一些實施例中，倒角的邊緣CE中的至少一個倒角的邊緣包括三個連接的傾斜表面（例如，斜表面）SS1、SS2及SS3，所述三個連接的傾斜表面SS1、SS2及SS3在半導體晶片100的根表面RS（半導體晶片100的側壁）與半導體晶片100的前表面FS之間延伸。底部填充膠230與半導體晶片100的根表面RS的一部分、半導體晶片100的倒角的邊緣CE的傾斜表面SS1、SS2及SS3及半導體晶片100的前表面FS直接接觸。倒角的邊緣CE的傾斜表面SS1、SS2及SS3通過底部填充膠230與絕緣封裝體240a（圖3G中所示）而被間隔開。換句話說，倒角的邊緣CE的傾斜表面SS1、SS2及SS3與絕緣封裝體240a（圖3G中所示）不會接觸。倒角的邊緣CE的傾斜表面SS1與半導體晶片100的前表面FS之間的外角θ1可介於約5度到約85度的範圍以內，半導體晶片100的倒角的邊緣CE的傾斜表面SS2與和半導體晶片100的前表面FS平行的虛擬平面VP1之間的外角θ2可介於約5度到約85度的範圍以內，且半導體晶片100的倒角的邊緣CE的傾斜表面SS3與和半導體晶片100的前表面FS平行的虛擬平面VP2之間的外角θ3可介於約5度到約85度的範圍以內。外角θ3大於外角θ2，且外角θ2大於外角θ1。
參考圖4D，半導體晶片100包括被修圓的邊緣RE。被修圓的邊緣RE的寬度D可介於約5微米到約500微米的範圍以內，且被修圓的邊緣RE的高度H可介於約5微米到約700微米的範圍以內。在一些實施例中，被修圓的邊緣RE中的每一者在半導體晶片100的根表面RS（半導體晶片100的側表面）與半導體晶片100的前表面FS之間延伸。底部填充膠230與半導體晶片100的根表面RS的一部分、半導體晶片100的被修圓的邊緣RE及半導體晶片100的前表面FS直接接觸。被修圓的邊緣RE通過底部填充膠230與絕緣封裝體240a（圖3G中所示）而被間隔開。換句話說，被修圓的邊緣RE與絕緣封裝體240a（圖3G中所示）不接觸。由於半導體晶片100包括被修圓的邊緣RE，因此可改善底部填充膠230與半導體晶片100之間的應力問題。
圖5A到圖5D是示意性地說明根據本公開的一些替代實施例的各種倒角的邊緣或被修圓的邊緣的剖視圖。
參考圖5A，倒角的邊緣CE的寬度D可介於約5微米到約500微米的範圍以內，且倒角的邊緣CE的高度H可介於約5微米到約700微米的範圍以內。在一些實施例中，倒角的邊緣CE中的至少一個倒角的邊緣包括在半導體晶片100的根表面RS（半導體晶片100的側壁）與半導體晶片100的前表面FS之間延伸的傾斜表面SS。底部填充膠230與半導體晶片100的傾斜表面SS的下部部分及半導體晶片100的前表面FS會直接接觸。絕緣封裝體240a與半導體晶片100的傾斜表面SS的上部部分及半導體晶片100的根表面RS會直接接觸。傾斜表面SS與底部填充膠230及絕緣封裝體240a兩者會直接接觸。半導體晶片100的倒角的邊緣CE的傾斜表面SS與半導體晶片100的前表面FS之間的外角θ1可介於約5度到約85度的範圍以內。
參考圖5B，倒角的邊緣CE的寬度D可介於約5微米到約500微米的範圍以內，且倒角的邊緣CE的高度H可介於約5微米到約700微米的範圍以內。在一些實施例中，倒角的邊緣CE中的至少一個倒角的邊緣包括兩個連接的傾斜表面SS1及SS2，所述兩個連接的傾斜表面SS1及SS2在半導體晶片100的根表面RS（半導體晶片100的側壁）與半導體晶片100的前表面FS之間延伸。底部填充膠230與半導體晶片100的前表面FS、傾斜表面SS1、及傾斜表面SS2的下部部分會直接接觸。絕緣封裝體240a與半導體晶片100的傾斜表面SS2的上部部分及根表面RS會直接接觸。傾斜表面SS2與底部填充膠230及絕緣封裝體240a兩者會直接接觸。倒角的邊緣CE的傾斜表面SS1與半導體晶片100的前表面FS之間的外角θ1可介於約5度到約85度的範圍以內，且半導體晶片100的倒角的邊緣CE的傾斜表面SS2與和半導體晶片100的前表面FS平行的虛擬平面VP1之間的外角θ2可介於約5度到約85度的範圍以內。外角θ2大於外角θ1。
參考圖5C，倒角的邊緣CE的寬度D可介於約5微米到約500微米的範圍以內，且倒角的邊緣CE的高度H可介於約5微米到約700微米的範圍以內。在一些實施例中，倒角的邊緣CE中的至少一個倒角的邊緣包括兩個連接的傾斜表面SS1及SS2，所述兩個連接的傾斜表面SS1及SS2在半導體晶片100的根表面RS（半導體晶片100的側壁）與半導體晶片100的前表面FS之間延伸。底部填充膠230與半導體晶片100的前表面FS及半導體晶片100的傾斜表面SS1的下部部分直接接觸。絕緣封裝體240a與半導體晶片100的傾斜表面SS1的上部部分、半導體晶片100的傾斜表面SS2及半導體晶片100的根表面RS直接接觸。傾斜表面SS1與底部填充膠230及絕緣封裝體240a兩者直接接觸。半導體晶片100的倒角的邊緣CE的傾斜表面SS1與半導體晶片100的前表面FS之間的外角θ1可介於約5度到約85度的範圍以內，且半導體晶片100的倒角的邊緣CE的傾斜表面SS2與和半導體晶片100的前表面FS平行的虛擬平面VP1之間的外角θ2可介於約5度到約85度的範圍內。外角θ2大於外角θ1。
參考圖5D，半導體晶片100包括被修圓的邊緣RE。被修圓的邊緣RE的寬度D可介於約5微米到約500微米的範圍以內，且被修圓的邊緣RE的高度H可介於約5微米到約700微米的範圍以內。在一些實施例中，被修圓的邊緣RE中的每一者在半導體晶片100的根表面RS（半導體晶片100的側表面）與半導體晶片100的前表面FS之間延伸。底部填充膠230與半導體晶片100的被修圓的邊緣RE的下部部分及半導體晶片100的前表面FS會直接接觸。絕緣封裝體240a與半導體晶片100的被修圓的邊緣RE的上部部分及半導體晶片100的根表面RS會直接接觸。被修圓的邊緣RE與底部填充膠230及絕緣封裝體240a兩者會直接接觸。
圖6A到圖6C是示意性地說明根據本公開的一些其他實施例的各種倒角的邊緣的剖視圖。
參考圖6A，倒角的邊緣CE的寬度D可介於約5微米到約500微米的範圍以內，且倒角的邊緣CE的高度H可介於約5微米到約700微米的範圍以內。在一些實施例中，倒角的邊緣CE中的至少一個倒角的邊緣包括三個連接的傾斜表面SS1、SS2及SS3，所述三個連接的傾斜表面SS1、SS2及SS3在半導體晶片100的根表面RS（半導體晶片100的側壁）與半導體晶片100的前表面FS之間延伸。底部填充膠230與半導體晶片100的前表面FS及半導體晶片100的傾斜表面SS1的下部部分會直接接觸。絕緣封裝體240a與半導體晶片100的傾斜表面SS1的上部部分、半導體晶片100的傾斜表面SS2、半導體晶片100的傾斜表面SS3及半導體晶片100的根表面RS會直接接觸。絕緣封裝體240a完全覆蓋傾斜表面SS2及SS3。傾斜表面SS1與底部填充膠230及絕緣封裝體240a兩者會直接接觸。倒角的邊緣CE的傾斜表面SS1與半導體晶片100的前表面FS之間的外角θ1可介於約5度到約85度的範圍以內，半導體晶片100的倒角的邊緣CE的傾斜表面SS2與和半導體晶片100的前表面FS平行的虛擬平面VP1之間的外角θ2可介於約5度到約85度的範圍內，且半導體晶片100的倒角的邊緣CE的傾斜表面SS3與和半導體晶片100的前表面FS平行的虛擬平面VP2之間的外角θ3可介於約5度到約85度的範圍以內。外角θ3大於外角θ2，且外角θ2大於外角θ1。
參考圖6B，倒角的邊緣CE的寬度D可介於約5微米到約500微米的範圍以內，且倒角的邊緣CE的高度H可介於約5微米到約700微米的範圍以內。在一些實施例中，倒角的邊緣CE中的至少一個倒角的邊緣包括三個連接的傾斜表面SS1、SS2及SS3，所述三個連接的傾斜表面SS1、SS2及SS3在半導體晶片100的根表面RS（半導體晶片100的側壁）與半導體晶片100的前表面FS之間延伸。底部填充膠230與半導體晶片100的前表面FS、傾斜表面SS1及傾斜表面SS2的下部部分會直接接觸。絕緣封裝體240a與半導體晶片100的傾斜表面SS2的上部部分、半導體晶片100的傾斜表面SS3及半導體晶片100的根表面RS會直接接觸。底部填充膠230可完全覆蓋傾斜表面SS1。傾斜表面SS2與底部填充膠230及絕緣封裝體240a兩者會直接接觸。半導體晶片100的倒角的邊緣CE的傾斜表面SS1與半導體晶片100的前表面FS之間的外角θ1可介於約5度到約85度的範圍以內，半導體晶片100的倒角的邊緣CE的傾斜表面SS2與和半導體晶片100的前表面FS平行的虛擬平面VP1之間的外角θ2可介於約5度到約85度的範圍以內，且半導體晶片100的倒角的邊緣CE的傾斜表面SS3與和半導體晶片100的前表面FS平行的虛擬平面VP2之間的外角θ3可介於約5度到約85度的範圍以內。外角θ3大於外角θ2，且外角θ2大於外角θ1。
參考圖6C，倒角的邊緣CE的寬度D可介於約5微米到約500微米的範圍以內，且倒角的邊緣CE的高度H可介於約5微米到約700微米的範圍以內。在一些實施例中，倒角的邊緣CE中的至少一個倒角的邊緣包括三個連接的傾斜表面SS1、SS2及SS3，所述三個連接的傾斜表面SS1、SS2及SS3在半導體晶片100的根表面RS（半導體晶片100的側壁）與半導體晶片100的前表面FS之間延伸。底部填充膠230與半導體晶片100的前表面FS、傾斜表面SS1、傾斜表面SS2及傾斜表面SS3的下部部分會直接接觸。底部填充膠230可完全覆蓋傾斜表面SS1及SS2。絕緣封裝體240a與半導體晶片100的傾斜表面SS3的上部部分及半導體晶片100的根表面RS會直接接觸。傾斜表面SS3與底部填充膠230及絕緣封裝體240a兩者會直接接觸。半導體晶片100的倒角的邊緣CE的傾斜表面SS1與半導體晶片100的前表面FS之間的外角θ1可介於約5度到約85度的範圍以內，半導體晶片100的倒角的邊緣CE的傾斜表面SS2與和半導體晶片100的前表面FS平行的虛擬平面VP1之間的外角θ2可介於約5度到約85度的範圍以內，且半導體晶片100的倒角的邊緣CE的傾斜表面SS3與和半導體晶片100的前表面FS平行的虛擬平面VP2之間的外角θ3可介於約5度到約85度的範圍以內。外角θ3大於外角θ2，且外角θ2大於外角θ1。
根據本公開的一些實施例，提供一種包括有機中介層基板、半導體晶片、導電凸塊、第一底部填充膠及絕緣封裝體的封裝結構。所述有機中介層基板包括堆疊的有機介電層及嵌置在所述堆疊的有機介電層中的導線。所述半導體晶片設置在所述有機中介層基板的所述導線之上且電連接到所述有機中介層基板的所述導線，且所述半導體晶片包括倒角的邊緣。所述導電凸塊設置在所述半導體晶片與所述有機中介層基板之間，且所述半導體晶片經由所述導電凸塊電連接到所述有機中介層基板。所述第一底部填充膠設置在所述半導體晶片與所述有機中介層基板之間，其中所述第一底部填充膠將所述導電凸塊封裝且接觸所述至少一個半導體晶片的所述倒角的邊緣。所述絕緣封裝體覆蓋所述有機中介層基板且在側向上將至少一個半導體晶片及所述第一底部填充膠封裝。在一些實施例中，所述倒角的邊緣的寬度介於約5微米到約500微米的範圍以內，且所述倒角的邊緣的高度介於約5微米到約700微米的範圍以內。在一些實施例中，所述倒角的邊緣中的至少一個倒角的邊緣包括在所述半導體晶片的根表面與所述半導體晶片的前表面之間延伸的至少一個傾斜表面，且所述第一底部填充膠會接觸所述倒角的邊緣的所述傾斜表面。在一些實施例中，所述第一底部填充膠進一步接觸所述根表面的第一部分，且所述絕緣封裝體接觸所述根表面的第二部分。在一些實施例中，所述倒角的邊緣中的至少一個倒角的邊緣包括在所述半導體晶片的根表面與所述半導體晶片的前表面之間延伸的至少一個傾斜表面，所述第一底部填充膠接觸所述倒角的邊緣的所述傾斜表面的第一部分，且所述絕緣封裝體接觸所述倒角的邊緣的所述傾斜表面的第二部分。在一些實施例中，所述倒角的邊緣中的至少一個倒角的邊緣包括第一傾斜表面及第二傾斜表面，所述第一傾斜表面在所述半導體晶片的前表面與所述第二傾斜表面之間延伸，所述第二傾斜表面在所述第一傾斜表面與根表面之間延伸，所述第一傾斜表面被所述第一底部填充膠完全覆蓋，所述第二傾斜表面接觸所述第一底部填充膠及所述絕緣封裝體。在一些實施例中，所述絕緣封裝體的側壁與所述有機中介層基板的側壁實質上對齊。在一些實施例中，所述堆疊的有機介電層的熱膨脹係數大於所述半導體晶片的半導體基板的熱膨脹係數。在一些實施例中，所述封裝結構還包括：電路基板；第一導電端子，設置在所述電路基板上且電連接到所述電路基板；第二導電端子，設置在所述電路基板上且電連接到所述電路基板；以及第二底部填充膠，設置在所述有機中介層基板與所述電路基板之間。所述有機中介層基板經由所述第一導電端子電連接到所述電路基板，且所述第一導電端子及所述第二導電端子設置在所述電路基板的相對的側上。所述第二底部填充膠將所述第一導電端子封裝。
根據本公開的一些其他實施例，提供一種包括中介層基板、半導體晶片、導電凸塊及底部填充膠的封裝結構。所述中介層基板包括堆疊的介電層及嵌置在堆疊的介電層中的導線。所述半導體晶片設置在所述中介層基板之上且電連接到所述中介層基板，且所述堆疊的介電層的熱膨脹係數大於半導體晶片的半導體基板的熱膨脹係數。半導體晶片包括倒角的邊緣，且所述倒角的邊緣中的至少一個倒角的邊緣包括斜表面。導電凸塊設置在半導體晶片與所述中介層基板之間，且所述半導體晶片經由所述導電凸塊電連接到所述中介層基板。所述底部填充膠設置在所述半導體晶片與所述中介層基板之間。在一些實施例中，所述倒角的邊緣的寬度介於約5微米到約500微米的範圍內，且倒角的邊緣的高度介於約5微米到約700微米的範圍內。在一些實施例中，所述底部填充膠接觸倒角的邊緣的斜表面、及根表面。在一些實施例中，絕緣封裝體的側壁與所述中介層基板的側壁實質上對齊。在一些實施例中，所述封裝結構還包括電路基板，其中所述中介層基板電連接到所述電路基板。
根據本公開的一些其他實施例，提供一種包括有機中介層基板、半導體晶片、導電凸塊及第一底部填充膠的封裝結構。有機中介層基板包括堆疊的有機介電層及嵌置在堆疊的有機介電層中的導線。半導體晶片設置在有機中介層基板的導線之上且電連接到所述有機中介層基板的導線，且所述半導體晶片包括被修圓的邊緣。所述導電凸塊設置在半導體晶片與有機中介層基板之間，且所述半導體晶片經由所述導電凸塊電連接到所述有機中介層基板。所述第一底部填充膠設置在所述半導體晶片與所述有機中介層基板之間。在一些實施例中，所述被修圓的邊緣中的每一者在所述半導體晶片的前表面與所述半導體晶片的側表面之間延伸，且所述第一底部填充膠接觸所述被修圓的邊緣。在一些實施例中，所述封裝結構還包括絕緣封裝體，所述絕緣封裝體覆蓋所述有機中介層基板且在側向上將至少一個半導體晶片及所述第一底部填充膠封裝，其中所述半導體晶片的所述被修圓的邊緣通過所述第一底部填充膠與所述絕緣封裝體而被間隔開。在一些實施例中，所述第一底部填充膠進一步接觸所述半導體晶片的所述側表面的第一部分，且所述絕緣封裝體接觸所述半導體晶片的所述側表面的第二部分。在一些實施例中，所述絕緣封裝體的側壁與所述有機中介層基板的側壁實質上對齊。在一些實施例中，所述封裝結構還包括電路基板、第一導電端子、第二導電端子及第二底部填充膠。所述第一導電端子設置在所述電路基板上且電連接到所述電路基板。所述第二導電端子設置在所述電路基板上且電連接到所述電路基板，其中所述有機中介層基板經由所述第一導電端子電連接到所述電路基板，且所述第一導電端子與所述第二導電端子設置在所述電路基板的相對的側上。所述第二底部填充膠設置在所述有機中介層基板與所述電路基板之間，其中所述第二底部填充膠將所述第一導電端子封裝。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應理解，他們可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效結構並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對本文作出各種改變、代替及更改。
100、100a:單體化的半導體晶片/半導體晶片 110、110a:半導體基板 120、120a:內連結構 122:導電接點 124、222、250、272:導電端子 210:有機中介層基板/晶圓式有機中介層基板 212:堆疊的有機介電層 212a:第一有機介電層 212b:第二有機介電層 212c:第三有機介電層 212d:第四有機介電層 214:導線 214a:第一導線 214b:第二導線 214c:第三導線 220:半導體元件 230、260:底部填充膠 240、240a:絕緣封裝體 270:電路基板 B1、B1’:V形切割刀片 B2:切割刀片 C:載體/晶圓式載體 CE、CE’:倒角的邊緣 D:寬度 FS:前表面 G:V形凹口 G1:第一V形凹口 G2:第二V形凹口 H:高度 PR:圖案化的光阻層 RS:根表面 S、S’:晶種層 SS、SS1、SS2、SS3:傾斜表面 SL:切割道 VP1、VP2:虛擬平面 W1:半導體晶圓 θ1、θ2、θ3:外角
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增加或減小各種特徵的尺寸。 圖1A到圖1C是示意性地說明根據本公開的一些實施例的半導體晶片的製作流程的剖視圖。 圖2A到圖2D是示意性地說明根據本公開的一些替代實施例的半導體晶片的製作流程的剖視圖。 圖3A到圖3G是示意性地說明根據本公開的一些實施例的晶圓級封裝（CoWoS）結構的製作流程的剖視圖。 圖4A到圖4D是示意性地說明根據本公開的一些實施例的各種倒角的邊緣或被修圓的邊緣的剖視圖。 圖5A到圖5D是示意性地說明根據本公開的一些替代實施例的各種倒角的邊緣或被修圓的邊緣的剖視圖。 圖6A到圖6C是示意性地說明根據本公開的一些其他實施例的各種倒角的邊緣的剖視圖。 圖7A到圖7E是示意性地說明根據本公開的一些其他實施例的各種倒角的邊緣的 底視圖。
100:單體化的半導體晶片
124、222、250:導電端子
210:有機中介層基板/晶圓式有機中介層基板
220:半導體元件
230、260:底部填充膠
240a:絕緣封裝體
270:電路基板
272:導電端子
CE:倒角的邊緣

Claims (20)

  1. 一種封裝結構，包括： 中介層基板，包括堆疊的介電層及嵌置在所述堆疊的介電層中的導線； 半導體晶片，設置在所述中介層基板的所述導線之上且電連接到所述中介層基板的所述導線，且所述半導體晶片包括倒角的邊緣； 導電凸塊，設置在所述半導體晶片與所述中介層基板之間，其中所述半導體晶片經由所述導電凸塊電連接到所述中介層基板； 第一底部填充膠，設置在所述半導體晶片與所述中介層基板之間，其中所述第一底部填充膠將所述導電凸塊封裝且覆蓋所述半導體晶片的所述倒角的邊緣；以及 絕緣封裝體，覆蓋所述中介層基板且在側向上將所述半導體晶片及所述第一底部填充膠封裝。
  2. 根據請求項1所述的封裝結構，其中所述倒角的邊緣的寬度介於約5微米到約500微米的範圍內，且所述倒角的邊緣的高度介於約5微米到約700微米的範圍內。
  3. 根據請求項1所述的封裝結構，其中所述倒角的邊緣中的至少一個倒角的邊緣包括在所述半導體晶片的根表面與所述半導體晶片的前表面之間延伸的至少一個傾斜表面，且所述第一底部填充膠接觸所述至少一個倒角的邊緣的所述至少一個傾斜表面。
  4. 根據請求項3所述的封裝結構，其中所述第一底部填充膠還接觸所述根表面的第一部分，且所述絕緣封裝體接觸所述根表面的第二部分。
  5. 根據請求項1所述的封裝結構，其中所述倒角的邊緣中的至少一個倒角的邊緣包括在所述半導體晶片的根表面與所述半導體晶片的前表面之間延伸的至少一個傾斜表面，所述第一底部填充膠接觸所述至少一個倒角的邊緣的所述至少一個傾斜表面的第一部分，且所述絕緣封裝體接觸所述至少一個倒角的邊緣的所述至少一個傾斜表面的第二部分。
  6. 根據請求項1所述的封裝結構，其中所述倒角的邊緣中的至少一個倒角的邊緣包括第一傾斜表面及第二傾斜表面，所述第一傾斜表面在所述半導體晶片的前表面與所述第二傾斜表面之間延伸，所述第二傾斜表面在所述半導體晶片的根表面與所述第一傾斜表面之間延伸，所述第一傾斜表面被所述第一底部填充膠完全覆蓋，所述第二傾斜表面接觸所述第一底部填充膠及所述絕緣封裝體。
  7. 根據請求項1所述的封裝結構，其中所述絕緣封裝體的側壁與所述中介層基板的側壁實質上對齊。
  8. 根據請求項1所述的封裝結構，其中所述堆疊的介電層包括堆疊的有機介電層，且所述堆疊的介電層的熱膨脹係數大於所述半導體晶片的半導體基板的熱膨脹係數。
  9. 根據請求項1所述的封裝結構，還包括： 電路基板； 第一導電端子，設置在所述電路基板上且電連接到所述電路基板； 第二導電端子，設置在所述電路基板上且電連接到所述電路基板，其中所述中介層基板經由所述第一導電端子電連接到所述電路基板，且所述第一導電端子與所述第二導電端子設置在所述電路基板的相對的側上；以及 第二底部填充膠，設置在所述中介層基板與所述電路基板之間，其中所述第二底部填充膠將所述第一導電端子封裝。
  10. 一種封裝結構，包括： 中介層基板，包括堆疊的介電層及嵌置在所述堆疊的介電層中的導線； 半導體晶片，設置在所述中介層基板之上且電連接到所述中介層基板，所述堆疊的介電層的熱膨脹係數大於所述半導體晶片的半導體基板的熱膨脹係數，其中所述半導體晶片包括倒角的邊緣，所述倒角的邊緣中的至少一個倒角的邊緣包括斜表面； 導電凸塊，設置在所述半導體晶片與所述中介層基板之間，其中所述半導體晶片經由所述導電凸塊電連接到所述中介層基板；以及 底部填充膠，設置在所述半導體晶片與所述中介層基板之間。
  11. 根據請求項10所述的封裝結構，其中所述倒角的邊緣的寬度介於約5微米到約500微米的範圍內，且所述倒角的邊緣的高度介於約5微米到約700微米的範圍內。
  12. 根據請求項10所述的封裝結構，其中所述底部填充膠接觸所述至少一個倒角的邊緣的所述斜表面及所述半導體晶片的根表面。
  13. 根據請求項10所述的封裝結構，其中絕緣封裝體的側壁與所述中介層基板的側壁實質上對齊。
  14. 根據請求項10所述的封裝結構，還包括電路基板，其中所述中介層基板電連接到所述電路基板。
  15. 一種封裝結構，包括： 中介層基板，包括堆疊的介電層及嵌置在所述堆疊的介電層中的導線； 半導體晶片，設置在所述中介層基板的所述導線之上且電連接到所述中介層基板的所述導線，且所述半導體晶片包括被修圓的邊緣； 導電凸塊，設置在所述半導體晶片與所述中介層基板之間，其中所述半導體晶片經由所述導電凸塊電連接到所述中介層基板；以及 第一底部填充膠，設置在所述半導體晶片與所述中介層基板之間。
  16. 根據請求項15所述的封裝結構，其中所述被修圓的邊緣中的每一者在所述半導體晶片的前表面與所述半導體晶片的側表面之間延伸，且所述第一底部填充膠接觸所述被修圓的邊緣。
  17. 根據請求項15所述的封裝結構，還包括： 絕緣封裝體，覆蓋所述中介層基板且在側向上將所述半導體晶片及所述第一底部填充膠封裝，其中所述半導體晶片的所述被修圓的邊緣通過所述第一底部填充膠而與所述絕緣封裝體而被間隔開。
  18. 根據請求項17所述的封裝結構，其中所述底部填充膠還接觸所述半導體晶片的側表面的第一部分，且所述絕緣封裝體接觸所述半導體晶片的所述側表面的第二部分。
  19. 根據請求項17所述的封裝結構，其中所述絕緣封裝體的側壁與所述中介層基板的側壁實質上對齊。
  20. 根據請求項15所述的封裝結構，還包括： 電路基板； 第一導電端子，設置在所述電路基板上且電連接到所述電路基板； 第二導電端子，設置在所述電路基板上且電連接到所述電路基板，其中所述中介層基板經由所述第一導電端子電連接到所述電路基板，且所述第一導電端子與所述第二導電端子設置在所述電路基板的相對的側上；以及 第二底部填充膠，設置在所述中介層基板與所述電路基板之間，其中所述第二底部填充膠封裝所述第一導電端子。
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