WO2023206976A1 - 半导体结构及半导体结构的制作方法 - Google Patents

半导体结构及半导体结构的制作方法 Download PDF

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Publication number
WO2023206976A1
WO2023206976A1 PCT/CN2022/124201 CN2022124201W WO2023206976A1 WO 2023206976 A1 WO2023206976 A1 WO 2023206976A1 CN 2022124201 W CN2022124201 W CN 2022124201W WO 2023206976 A1 WO2023206976 A1 WO 2023206976A1
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Prior art keywords
layer
semiconductor structure
opening
recess
test pad
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PCT/CN2022/124201
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English (en)
French (fr)
Inventor
吴奇龙
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长鑫存储技术有限公司
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Priority to US18/197,240 priority Critical patent/US20230343656A1/en
Publication of WO2023206976A1 publication Critical patent/WO2023206976A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure.
  • Re-distribution Layer is to change the contact position (I/O pad) of the originally designed integrated circuit (IC, Integrated Circuit) through the wafer-level metal wiring process and bonding pad process. Make the IC suitable for different packaging forms.
  • the redistribution layer may include test pads and connection pads. In the absence of an optical identification layer between the test pad and the connection pad, the test equipment may fail to recognize the test pad and report an error when performing automated testing.
  • the present disclosure provides a semiconductor structure and a manufacturing method of the semiconductor structure to improve the testing performance of the semiconductor structure.
  • a semiconductor structure including:
  • the rewiring layer is located on the base body.
  • the rewiring layer includes connection pads and test pads.
  • the connection pads and test pads are adjacent to each other.
  • the rewiring layer is formed with a depression. The depression is located on the connection pad and the test pad. between.
  • the opening widths of the recesses are all uniform.
  • At least part of the opening width of the recess is tapered.
  • the opening width of the recess gradually decreases from two opposite edge areas to the middle area.
  • the depressions extend along a first direction, and the plurality of depressions are spaced apart along a second direction perpendicular to the first direction;
  • the first direction is substantially parallel to the edge line of the test pad toward the connection pad.
  • the plurality of recesses are spaced apart along a first direction, and the first direction is substantially parallel to an edge line of the test pad toward the connection pad.
  • the plurality of depressions are in at least two rows along a second direction perpendicular to the first direction.
  • the substrate includes:
  • a conductive layer is located on the substrate, and the redistribution layer is connected to the conductive layer;
  • the dielectric layer is located on the substrate, the dielectric layer is provided with a first opening, and the first orthographic projection of the depression on the substrate is located within the second orthographic projection of the first opening on the substrate.
  • the redistribution layer fills a portion of the first opening.
  • an air gap is formed on a side of the redistribution layer facing the first opening.
  • the first opening exposes the conductive layer.
  • the width of the first opening is no greater than 3um.
  • the width of the first opening is 1um-3um.
  • the semiconductor structure further includes:
  • the optical identification layer is located on the rewiring layer
  • a second opening is provided on the optical identification layer to expose the connection pad, the test pad and the recess.
  • a method for manufacturing a semiconductor structure including:
  • the first orthographic projection of the recess on the base is located within the second orthographic projection of the first opening on the base.
  • a first opening is formed in the base to form a recess on the redistribution layer
  • a plurality of first openings are formed in the base to form a plurality of recesses on the redistribution layer.
  • the base body includes a substrate and a conductive layer and a dielectric layer formed sequentially on the substrate, the first opening is formed on the dielectric layer, and the redistribution layer is formed on the dielectric layer.
  • the method for manufacturing a semiconductor structure further includes:
  • a second opening is formed on the optical identification layer to expose the connection pad, the test pad and the recess.
  • the semiconductor structure of the embodiment of the present disclosure includes a base body and a redistribution layer.
  • the redistribution layer is located on the base body, and the redistribution layer includes adjacent connection pads and test pads.
  • a recess is formed on the redistribution layer, and the redistribution layer is located on the redistribution layer.
  • FIG. 1 is a schematic flowchart of a method of manufacturing a semiconductor structure according to an exemplary embodiment
  • Figure 2 is a schematic cross-sectional structural diagram of a semiconductor structure according to an exemplary embodiment
  • FIG. 3 is a schematic structural diagram of a semiconductor structure according to a first exemplary embodiment
  • FIG. 4 is a schematic structural diagram of a semiconductor structure according to a second exemplary embodiment
  • FIG. 5 is a schematic structural diagram of a semiconductor structure according to a third exemplary embodiment
  • FIG. 6 is a schematic structural diagram of a semiconductor structure according to a fourth exemplary embodiment.
  • FIG. 7 is a schematic structural diagram of a semiconductor structure according to a fifth exemplary embodiment.
  • FIG. 8 is a schematic structural diagram of a semiconductor structure according to a sixth exemplary embodiment.
  • Base body 11. Substrate; 12. Conductive layer; 13. Dielectric layer; 131. First opening; 20. Rewiring layer; 21. Connection pad; 22. Test pad; 23. Recess; 231. Edge area; 232, middle area; 24, air gap; 30, optical identification layer; 31, second opening.
  • At least one embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. Please refer to FIGS. 1 to 8 .
  • the method for manufacturing a semiconductor structure includes:
  • the first orthographic projection of the recess 23 on the base 10 is located within the second orthographic projection of the first opening 131 on the base 10 .
  • the manufacturing method of a semiconductor structure forms a first opening 131 in the base 10, so that in the process of forming the rewiring layer 20 on the base 10, the connection pads 21 and the test solder of the rewiring layer 20 can be A recess 23 is formed between the pads 22.
  • the recess 23 can serve as an optical identification pattern on one side of the test pad 22. Therefore, it is possible to avoid the failure of the test equipment due to the absence of an optical identification pattern between the connection pad 21 and the test pad 22. During automated testing, the test pad 22 cannot be recognized and an error occurs, so as to improve the testing performance of the semiconductor structure.
  • the first opening 131 is formed in the base 10 , during the process of depositing metal material on the base 10 to form the redistribution layer 20 , part of the metal material will sink into the first opening 131 , and thus the rewiring will occur.
  • a depression 23 is formed on the upper surface of the layer 20 , and the depression 23 can serve as an optical identification pattern on one side of the test pad 22 .
  • the material of the redistribution layer 20 including aluminum (Al) as an example, since the width of the first opening 131 is relatively small, during the process of depositing Al to form the redistribution layer 20, the bottom and bottom edge of the first opening 131 will not be deposited. Al, the thickness of Al deposition will increase from bottom to top, thereby forming a depression 23 and an air gap 24 located below the depression, as shown in Figure 2 .
  • the width of the first opening 131 is not greater than 3um.
  • a large amount of metal material will not be deposited into the first opening during the formation of the redistribution layer 20. 131, thereby forming a larger-sized depression 23 on the redistribution layer 20, thereby affecting the structural performance of the redistribution layer 20.
  • the width of the first opening 131 is 1um-3um, which not only ensures that the redistribution layer 20 can form the recess 23 , but also prevents the recess 23 from being too small, so that the recess 23 can reliably serve as the test pad 22 optical recognition graphics.
  • the width of the first opening 131 may be 1um, 1.1um, 1.2um, 1.3um, 1.5um, 1.6um, 1.8um, 2um, 2.1um, 2.2um, 2.3um, 2.5um, 2.6um , 2.7um, 2.8um, 2.9um or 3um, etc.
  • a first opening 131 is formed in the base 10 to form a recess 23 on the redistribution layer 20.
  • the opposite sides of the recess 23 are connection pads 21 respectively. and the test pad 22, so that the depression 23 can be used as an optical identification pattern around the test pad 22, thereby ensuring that the test pad 22 can implement electrical performance testing of the semiconductor structure.
  • a plurality of first openings 131 are formed in the base 10 to form a plurality of recesses 23 on the redistribution layer 20. As shown in FIGS. 5 to 7, opposite sides of the plurality of recesses 23 are respectively formed.
  • multiple depressions 23 can be used together as optical identification patterns around the test pad 22, thereby ensuring that the test pad 22 can implement electrical performance testing of the semiconductor structure.
  • the structural form of the first opening 131 may be substantially consistent with the recess 23 .
  • one recess 23 may be formed on the redistribution layer 20 .
  • there may be multiple first openings 131 and in this case, multiple recesses 23 may be formed on the redistribution layer 20 .
  • the opening widths of the first openings 131 may be uniform. The opening width of the first opening 131 may change gradually.
  • first opening 131 there may be one first opening 131 , and the opening widths of the first openings 131 may be uniform, so that the opening widths of the formed depressions 23 may be uniform, as shown in FIG. 3 .
  • first openings 131 there may be multiple first openings 131 , for example, there may be two first openings 131 , and the two first openings 131 may be spaced apart, so that the two recesses 23 formed may be spaced apart, as shown in FIG. 5 shown.
  • first openings 131 there may be a plurality of first openings 131 , and the plurality of first openings 131 may be in at least two rows along the second direction perpendicular to the first direction, so that at least two rows of depressions 23 may be formed, for example, a first The openings 131 may be in two rows, thereby forming two rows of recesses 23, as shown in Figure 7.
  • an air gap 24 is formed on the side of the redistribution layer 20 facing the first opening 131 , so that air isolation can be formed below the recess 23 , thus ensuring that the redistribution layer 20 is redistributed during the formation of the redistribution layer 20 .
  • a recess 23 is formed on the upper surface of the wiring layer 20 as shown in FIG. 2 .
  • the base 10 includes a substrate 11 and a conductive layer 12 and a dielectric layer 13 sequentially formed on the substrate 11 .
  • a first opening 131 is formed on the dielectric layer 13 , and rewiring is performed on the substrate 11 .
  • Layer 20 is formed on dielectric layer 13 , and redistribution layer 20 is connected to conductive layer 12 .
  • the first opening 131 is formed on the dielectric layer 13, so that during the process of forming the rewiring layer 20 on the dielectric layer 13, the recess 23 can be formed on the rewiring layer 20, thereby simplifying the manufacturing difficulty of the semiconductor structure and improving the quality of the semiconductor structure. Production efficiency.
  • multiple conductive layers 12 may be formed on the substrate 11, and the redistribution layer 20 may be connected to one conductive layer 12.
  • a through hole may be formed on the dielectric layer 13, and the through hole may expose a conductive layer 12.
  • Layer 12 realizes the electrical connection between the redistribution layer 20 and the conductive layer 12 in the process of forming the redistribution layer 20 by depositing metal materials in the through holes.
  • the first opening 131 exposes the conductive layer 12 , that is, the first opening 131 may be a through hole, thereby increasing the depth of the first opening 131 , thereby ensuring that a reliable depression 23 can be formed on the redistribution layer 20 .
  • the first opening 131 may not expose the conductive layer 12 , that is, the bottom wall of the first opening 131 may be located within the dielectric layer 13 , thereby reducing the manufacturing time for forming the first opening 131 .
  • substrate 11 may include portions formed of silicon-containing material.
  • the substrate 11 may be formed of any suitable material, including, for example, at least one of silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, and carbon-doped silicon.
  • the dielectric layer 13 may be an insulating layer.
  • the material of the dielectric layer 13 may include but is not limited to one or more of insulating materials such as silicon oxide, silicon nitride, and tetraethyl orthosilicate (TEOS).
  • insulating materials such as silicon oxide, silicon nitride, and tetraethyl orthosilicate (TEOS).
  • the conductive layer 12 is made of a conductive material, and the conductive layer 12 can be made of a metal material.
  • the conductive layer 12 can be made of an aluminum material, or the conductive layer 12 can be made of a copper material.
  • the redistribution layer 20 is made of a conductive material.
  • the redistribution layer 20 can be made of a metal material.
  • the redistribution layer 20 can be made of an aluminum material.
  • the redistribution layer 20 can be made of a copper material. .
  • the conductive layer 12 can be made of aluminum material, and the redistribution layer 20 can be made of aluminum material, thereby improving the connection ability between the conductive layer 12 and the redistribution layer 20 and ensuring that the conductive layer 12 is connected to the redistribution layer 20 .
  • the wiring layer 20 forms reliable electrical connections.
  • the method of manufacturing a semiconductor structure further includes: forming an optical identification layer 30 on the redistribution layer 20; forming a second opening 31 on the optical identification layer 30 to expose the connection pad 21 and the test pad 22. and depression 23.
  • the optical identification layer 30 can protect the redistribution layer 20 .
  • the reflectivity of the optical identification layer 30 is lower than that of the test pad 22, and the reflectivity of the recess 23 is also lower than that of the test pad 22. Therefore, the optical identification layer 30 and the recess 23 can be combined as a test solder.
  • the optical identification layer 30 may be a photoresist layer, and the optical identification layer 30 may be a polymer layer.
  • the material of the polymer layer may include but is not limited to polyimide or polybenzoxazole.
  • the optical identification layer 30 is processed using a photolithography process to form a second opening 31 , and the second opening 31 exposes the connection pad 21 , the test pad 22 and the recess 23 .
  • a plurality of second openings 31 may be formed on the optical identification layer 30 .
  • the plurality of second openings 31 may be arranged at intervals.
  • Each second opening 31 may simultaneously expose the connection pad 21 , the test pad 22 and the For the recess 23, for example, there may be three second openings 31, and the three second openings 31 may simultaneously expose the corresponding connection pads 21, the test pads 22 and the recess 23, as shown in FIG. 8 .
  • At least one embodiment of the present disclosure also provides a semiconductor structure.
  • the semiconductor structure includes: a base 10; a redistribution layer 20, the redistribution layer 20 is located on the base 10, and the redistribution layer 20 includes connections The bonding pad 21 and the test pad 22, the connection pad 21 and the test pad 22 are arranged adjacently, and the rewiring layer 20 is formed with a recess 23, and the recess 23 is located between the connection pad 21 and the test pad 22.
  • the semiconductor structure of an embodiment of the present disclosure includes a base 10 and a rewiring layer 20.
  • the rewiring layer 20 is located on the base 10, and the rewiring layer 20 includes adjacently arranged connection pads 21 and test pads 22.
  • a recess 23 is formed on the layer 20, and the recess 23 is located between the connection pad 21 and the test pad 22, so that the recess 23 can be used as an optical identification pattern on one side of the test pad 22, so that the connection pad 21 and the test pad 22 can be avoided. There is no optical identification pattern between the test pads 22, which causes the test equipment to be unable to identify the test pads 22 and report an error when performing automated testing, thereby improving the test performance of the semiconductor structure.
  • test equipment for example, the test equipment includes probes
  • the test equipment is in contact with the test pad 22.
  • the test pad needs to be identified through optical equipment. 22 circumferential area, if there is no optical identification pattern between the connection pad 21 and the test pad 22, for example, the connection pad 21 and the test pad 22 are directly connected, at this time, the optical device cannot accurately identify the test
  • the position area of the pad 22 will cause errors to occur, thereby affecting the electrical performance test of the semiconductor structure.
  • the recess 23 is located between the connection pad 21 and the test pad 22. Therefore, the recess 23 can serve as a gap between the connection pad 21 and the test pad 22.
  • the pattern is optically recognized, so that the location area of the test pad 22 can be identified, thereby achieving electrical performance testing of the semiconductor structure.
  • an optical identification layer 30 is disposed on the rewiring layer 20 .
  • the optical identification layer 30 protects the rewiring layer 20 , and the optical identification layer 30 needs to expose the connection pad 21 , the test pad 22 and the recess 23 , so that the connection pad 21 can be used for connecting to external devices, and the test pad 22 can be used for electrical performance testing of the semiconductor structure.
  • a recess 23 can be directly provided between the connection pad 21 and the test pad 22, that is, the two edges of the opening of the recess 23 are connected to the connection pad 21 and the test pad 22 respectively. At this time, the edges around the test pad 22
  • the optical identification layer 30 and the recess 23 may be combined to serve as an optical identification pattern around the test pad 22 .
  • the base 10 is provided with a first opening 131 , the first opening 131 faces the redistribution layer 20 , and the first orthographic projection of the recess 23 on the base 10 is located at the second orthogonal projection of the first opening 131 on the base 10 .
  • an optical identification layer 30 is provided on the redistribution layer 20
  • a second opening 31 is provided on the optical identification layer 30 to expose the connection pad 21 , the test pad 22 and the recess 23 .
  • the arrangement of the first opening 131 can form the recess 23 on the redistribution layer 20 during the process of forming the redistribution layer 20, and the second opening 31 realizes the exposure of the connection pad 21, the test pad 22 and the recess 23, so as to This allows the connection pad 21 to be used for connecting to external devices, the test pad 22 to be used for electrical performance testing of the semiconductor structure, and the depression 23 to be used as an optical identification pattern around the test pad 22 .
  • Bonding pad 22 enables electrical performance testing of the semiconductor structure.
  • the opening of the recess 23 includes a first edge and a second edge, and the first edge and the second edge intersect with the edges of the connection pad 21 and the test pad 22 respectively.
  • the recess 23 can serve as an optical identification pattern around the test pad 22, and Together with the optical identification layer 30 around the test pad 22, the circumferential surrounding of the test pad 22 is achieved.
  • the opening widths of the recesses 23 are all the same. Not only is the structure simple, but the production of the recesses 23 is also more convenient, thereby simplifying the production efficiency of the semiconductor structure, and the recesses have the same opening width. 23 can be used as an optical identification pattern around the test pad 22.
  • At least part of the opening width of the recess 23 changes in a tapered manner, so that the pattern formed by the recess 23 is easier to identify, thereby improving the identification efficiency of the pattern.
  • the opening width of the recess 23 gradually decreases from the two opposite edge areas 231 to the middle area 232 , which not only makes the pattern formed by the recess 23 easier to identify, but also ensures that the recess 23 does not It will occupy too much area of the test pad 22 and the connection pad 21, thereby improving the structural utilization of the rewiring layer 20.
  • a part of the opening width of the middle region 232 of the recess 23 can be uniform, while the opening widths of the two outer regions of the recess 23 have a variable size structure. In some embodiments, it is not excluded that the recess 23 is entirely composed of two tapered parts.
  • the multiple recesses 23 there are multiple recesses 23 , and the opposite sides formed by the multiple recesses 23 are respectively the connection pad 21 and the test pad 22 , so that the multiple recesses 23 can jointly serve as optical identification around the test pad 22 pattern to ensure that the test pad 22 can implement electrical performance testing of the semiconductor structure.
  • the recesses 23 extend along a first direction, and the plurality of recesses 23 are spaced apart along a second direction perpendicular to the first direction; wherein the first direction is substantially parallel to the edge of the test pad 22 toward the connection pad 21 There may be at least two spaced apart depressions 23 between the lines, that is, the test pads 22 and the connection pads 21 .
  • the shape of the test pad 22 and the connection pad 21 is roughly rectangular, and the edge lines directly opposite to the test pad 22 and the connection pad 21 are basically parallel. At this time, the edge lines directly opposite to the test pad 22 and the connection pad 21
  • the extension direction may be the first direction, and the direction perpendicular to the edge line directly opposite the test pad 22 and the connection pad 21 may be the second direction.
  • the recess 23 extends along the first direction, and the two recesses 23 are spaced apart along the second direction.
  • the opening widths of the recesses 23 extending along the first direction may be uniform, as shown in FIG. 5 .
  • at least part of the opening width of the recess 23 extending along the first direction changes in a tapered manner.
  • the recess 23 shown in FIG. 5 can be replaced by the recess 23 shown in FIG. 4 .
  • the specific structure of the recess 23 extending along the first direction is not limited here.
  • a plurality of depressions 23 are spaced apart along a first direction, and the first direction is substantially parallel to the edge line of the test pad 22 toward the connection pad 21 , so that multiple independent depressions can be formed. 23 together form the optical identification pattern of the test pad 22 .
  • the plurality of recesses 23 are arranged in at least two rows along the second direction perpendicular to the first direction, so that the plurality of recesses 23 in an array jointly form the optical structure of the test pad 22 . Identify graphics.
  • the number and specific structural form of the recesses 23 are not limited, as long as it can be ensured that the recesses 23 can serve as the optical identification pattern of the test pad 22 .
  • the redistribution layer 20 is made of conductive material.
  • the redistribution layer 20 can be made of a metal material.
  • the redistribution layer 20 can be made of aluminum material.
  • the redistribution layer 20 can be made of aluminum material. It is made of copper material.
  • the material of the rewiring layer 20 is not limited here and can be selected according to actual needs.
  • the base 10 includes: a substrate 11; a conductive layer 12, the conductive layer 12 is located on the substrate 11, the redistribution layer 20 is connected to the conductive layer 12; a dielectric layer 13, 13 is located on the substrate 11.
  • a first opening 131 is provided on the dielectric layer 13.
  • the first orthographic projection of the recess 23 on the substrate 11 is located within the second orthographic projection of the first opening 131 on the substrate 11.
  • the arrangement of 131 can form recesses 23 on the redistribution layer 20 during the process of forming the redistribution layer 20, thereby simplifying the manufacturing difficulty of the semiconductor structure and improving the manufacturing efficiency of the semiconductor structure.
  • the first opening 131 on the dielectric layer 13 may be a hole segment, and the hole segment may have only one open end, and this open end faces the redistribution layer 20, so that during the process of forming the redistribution layer 20, the redistribution layer 20 can be formed on the redistribution layer 20.
  • a depression 23 is formed.
  • the first opening 131 on the dielectric layer 13 may be a through hole, with one open end of the through hole facing the redistribution layer 20, so that the recess 23 can be formed on the redistribution layer 20 during the formation of the redistribution layer 20, and the dielectric layer
  • the other open end of 13 may face the conductive layer 12 .
  • the base 10 may include a plurality of conductive layers 12, and the redistribution layer 20 may be connected to one conductive layer 12.
  • a through hole may be formed on the dielectric layer 13, and the through hole may expose one conductive layer 12.
  • the conductive layer 12 is made of a conductive material, and the conductive layer 12 can be made of a metal material.
  • the conductive layer 12 can be made of an aluminum material, or the conductive layer 12 can be made of a copper material. Therefore, the material of the conductive layer 12 is not limited here and can be selected according to actual needs.
  • the conductive layer 12 may be a metal wire.
  • the conductive layer 12 can be made of aluminum material, and the redistribution layer 20 can be made of aluminum material, thereby improving the connection ability between the conductive layer 12 and the redistribution layer 20 and ensuring that the conductive layer 12 is connected to the redistribution layer 20 .
  • the wiring layer 20 forms reliable electrical connections.
  • substrate 11 may include portions formed of silicon-containing material.
  • the substrate 11 may be formed of any suitable material, including, for example, at least one of silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, and carbon-doped silicon.
  • the dielectric layer 13 may be a polymer layer.
  • the dielectric layer 13 may include but is not limited to a polyimide layer or a polybenzoxazole layer.
  • the dielectric layer 13 may also be a tetraethylorthosilicate (TEOS) layer.
  • TEOS tetraethylorthosilicate
  • the redistribution layer 20 fills a part of the first opening 131 , that is, during the process of forming the redistribution layer 20 , a part of the redistribution layer 20 will sink into the first opening 131 , so that the redistribution layer 20 can be redistributed.
  • Recesses 23 are formed in layer 20 .
  • the structural form of the first opening 131 may be substantially consistent with the recess 23.
  • the recess 23 may be one, and in this case, the first opening 131 may be divided into one.
  • the number of recesses 23 may be multiple, and in this case, the first opening 131 may be divided into multiple recesses.
  • the opening widths of the recesses 23 are all the same. In this case, the opening widths of the first openings 131 can be all the same. At least part of the opening width of the recess 23 changes in a tapering manner. At this time, the opening width of the first opening 131 may change in a tapering manner.
  • the structural form of the first opening 131 may be substantially consistent with the recess 23 , but it does not mean that the opening width of the recess 23 and the opening width of the first opening 131 must be consistent.
  • an air gap 24 is formed on the side of the redistribution layer 20 facing the first opening 131 , so that air isolation can be formed below the recess 23 , thus ensuring that the redistribution layer is formed before the redistribution layer 20 is formed.
  • a depression 23 is formed on the upper surface of the redistribution layer 20.
  • the first opening 131 exposes the conductive layer 12 , that is, the first opening 131 may be a through hole, thereby increasing the depth of the first opening 131 to ensure that the redistribution layer 20 can be formed Reliable depression23.
  • the first opening 131 may not expose the conductive layer 12 , that is, the bottom wall of the first opening 131 may be located within the dielectric layer 13 , thereby reducing the manufacturing time for forming the first opening 131 .
  • the width of the first opening 131 is not greater than 3um.
  • a large amount of metal material will not be deposited into the first opening during the formation of the redistribution layer 20. 131, thereby forming a larger-sized depression 23 on the redistribution layer 20, thereby affecting the structural performance of the redistribution layer 20.
  • the width of the first opening 131 is 1um-3um, which not only ensures that the redistribution layer 20 can form the recess 23 , but also prevents the recess 23 from being too small, so that the recess 23 can reliably serve as the test pad 22 optical recognition graphics.
  • the width of the first opening 131 may be 1um, 1.1um, 1.2um, 1.3um, 1.5um, 1.6um, 1.8um, 2um, 2.1um, 2.2um, 2.3um, 2.5um, 2.6um , 2.7um, 2.8um, 2.9um or 3um, etc.
  • the semiconductor structure further includes: an optical identification layer 30 located on the redistribution layer 20 ; wherein a second opening 31 is provided on the optical identification layer 30 to expose the connections. Pad 21, test pad 22 and recess 23.
  • the optical identification layer 30 can realize protection of the rewiring layer 20 , and the optical identification layer 30 and the recess 23 can be combined to serve as an optical identification pattern around the test pad 22 .
  • the optical identification layer 30 may be a photoresist layer, and the optical identification layer 30 may be a polymer layer, and the polymer layer may include but is not limited to a polyimide layer or a polybenzoxazole layer.
  • a second opening 31 may simultaneously expose the connection pad 21, the test pad 22, and the recess 23.
  • connection pads 21 there may be a plurality of connection pads 21 , test pads 22 and recesses 23 , and a plurality of second openings 31 may be provided on the optical identification layer 30 , each second opening 31
  • the corresponding connection pads 21, test pads 22 and recesses 23 can be exposed simultaneously.
  • the semiconductor structure is formed by the above-mentioned method of manufacturing a semiconductor structure.

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Abstract

本公开涉及半导体技术领域，提出了一种半导体结构及半导体结构的制作方法。半导体结构包括：基体；重布线层，重布线层位于基体上，重布线层包括连接焊盘和测试焊盘，连接焊盘和测试焊盘相邻设置，重布线层形成有凹陷，凹陷位于连接焊盘和测试焊盘之间。 (图2)

Description

半导体结构及半导体结构的制作方法
交叉引用
本公开要求于2022年04月25日提交的申请号为202210464674.1、名称为“半导体结构及半导体结构的制作方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及半导体结构的制作方法。
背景技术
重布线层(RDL，Re-distribution Layer)是将原来设计的集成电路(IC，Integrated Circuit)线路接点位置(I/O pad)，通过晶圆级金属布线制程和焊垫制程改变其接点位置，使IC能适用于不同的封装形式。
重布线层可以包括测试焊盘和连接焊盘。在测试焊盘和连接焊盘之间不存在光学识别层的情况下，测试设备在进行自动化测试时可能会存在无法识别测试焊盘而出现报错的问题。
发明内容
本公开提供一种半导体结构及半导体结构的制作方法，以改善半导体结构的测试性能。
根据本公开的第一个方面，提供了一种半导体结构，包括：
基体；
重布线层，重布线层位于基体上，重布线层包括连接焊盘和测试焊盘，连接焊盘和测试焊盘相邻设置，重布线层形成有凹陷，凹陷位于连接焊盘和测试焊盘之间。
在本公开的一个实施例中，凹陷为一个，凹陷的相对两侧分别为连接焊盘和测试焊盘。
在本公开的一个实施例中，凹陷的开口宽度均相一致。
在本公开的一个实施例中，凹陷的开口宽度的至少部分呈渐缩式变化。
在本公开的一个实施例中，凹陷的开口宽度由相对的两个边缘区域向中间区域逐渐缩小。
在本公开的一个实施例中，凹陷为多个，多个凹陷形成的相对两侧分别为连接焊盘和测试焊盘。
在本公开的一个实施例中，凹陷沿第一方向延伸，多个凹陷沿垂直于第一方向的第二方向间隔设置；
其中，第一方向基本平行于测试焊盘朝向连接焊盘的边缘线。
在本公开的一个实施例中，多个凹陷沿第一方向间隔设置，第一方向基本平行于测试焊盘朝向连接焊盘的边缘线。
在本公开的一个实施例中，沿垂直于第一方向的第二方向多个凹陷为至少两行。
在本公开的一个实施例中，基体包括：
衬底；
导电层，导电层位于衬底上，重布线层与导电层相连接；
介质层，介质层位于衬底上，介质层上设置有第一开口，凹陷在衬底上的第一正投影位于第一开口在衬底上的第二正投影内。
在本公开的一个实施例中，重布线层填充第一开口的一部分。
在本公开的一个实施例中，重布线层朝向第一开口的一侧形成有气隙。
在本公开的一个实施例中，第一开口暴露导电层。
在本公开的一个实施例中，第一开口的宽度不大于3um。
在本公开的一个实施例中，第一开口的宽度为1um-3um。
在本公开的一个实施例中，半导体结构还包括：
光学识别层，光学识别层位于重布线层上；
其中，光学识别层上设置有第二开口，以暴露连接焊盘、测试焊盘以及凹陷。
根据本公开的第二个方面，提供了一种半导体结构的制作方法，包括：
提供基体；
在基体内形成第一开口；
在基体上形成重布线层，以使得重布线层的连接焊盘和测试焊盘之间形成有凹陷；
其中，凹陷在基体上的第一正投影位于第一开口在基体上的第二正投影内。
在本公开的一个实施例中，在基体内形成一个第一开口，以在重布线层上形成一个凹陷；
或，在基体内形成多个第一开口，以在重布线层上形成多个凹陷。
在本公开的一个实施例中，基体包括在衬底、以及在衬底上依次形成的导电层和介质 层，第一开口形成于介质层上，重布线层形成于介质层上。
在本公开的一个实施例中，半导体结构的制作方法，还包括：
在重布线层上形成光学识别层；
在光学识别层上形成第二开口，以暴露连接焊盘、测试焊盘以及凹陷。
本公开实施例的半导体结构包括基体和重布线层，重布线层位于基体上，而重布线层包括相邻设置的连接焊盘和测试焊盘，通过在重布线层上形成凹陷，且凹陷位于连接焊盘和测试焊盘之间，从而可以使得凹陷能够作为测试焊盘一侧的光学识别图形，因此可以避免由于连接焊盘和测试焊盘之间不存在光学识别图形而导致测试设备在进行自动化测试时无法识别测试焊盘而出现报错的问题，以此改善半导体结构的测试性能。
附图说明
通过结合附图考虑以下对本公开的优选实施方式的详细说明，本公开的各种目标，特征和优点将变得更加显而易见。附图仅为本公开的示范性图解，并非一定是按比例绘制。在附图中，同样的附图标记始终表示相同或类似的部件。其中：
图1是根据一示例性实施方式示出的一种半导体结构的制作方法的流程示意图；
图2是根据一示例性实施方式示出的一种半导体结构的剖面结构示意图；
图3是根据第一个示例性实施方式示出的一种半导体结构的结构示意图；
图4是根据第二个示例性实施方式示出的一种半导体结构的结构示意图；
图5是根据第三个示例性实施方式示出的一种半导体结构的结构示意图；
图6是根据第四个示例性实施方式示出的一种半导体结构的结构示意图；
图7是根据第五个示例性实施方式示出的一种半导体结构的结构示意图；
图8是根据第六个示例性实施方式示出的一种半导体结构的结构示意图。
附图标记说明如下：
10、基体；11、衬底；12、导电层；13、介质层；131、第一开口；20、重布线层；21、连接焊盘；22、测试焊盘；23、凹陷；231、边缘区域；232、中间区域；24、气隙；30、光学识别层；31、第二开口。
具体实施方式
体现本公开特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是本公开能够在不同的实施例上具有各种的变化，其皆不脱离本公开的范围，且其中的说明及附图 在本质上是作说明之用，而非用以限制本公开。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构、系统和步骤。应理解的是，可以使用部件、结构、示例性装置、系统和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”、“之间”、“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。
本公开的至少一个实施例提供了一种半导体结构的制作方法，请参考图1至图8，该半导体结构的制作方法包括：
S101，提供基体10；
S103，在基体10内形成第一开口131；
S105，在基体10上形成重布线层20，以使得重布线层20的连接焊盘21和测试焊盘22之间形成有凹陷23；
其中，凹陷23在基体10上的第一正投影位于第一开口131在基体10上的第二正投影内。
本公开一个实施例的半导体结构的制作方法通过在基体10内形成第一开口131，从而在基体10上形成重布线层20的过程中，可以在重布线层20的连接焊盘21和测试焊盘22之间形成有凹陷23，凹陷23能够作为测试焊盘22一侧的光学识别图形，因此可以避免由于连接焊盘21和测试焊盘22之间不存在光学识别图形而导致测试设备在进行自动化测试时无法识别测试焊盘22而出现报错的问题，以此改善半导体结构的测试性能。
需要说明的是，由于基体10内形成第一开口131，从而在基体10上沉积金属材料形成重布线层20的过程中，部分金属材料会下沉至第一开口131内，因此会在重布线层20的上表面形成一个凹陷23，凹陷23可以作为测试焊盘22一侧的光学识别图形。以重布线层20的材料包括铝(Al)为例，由于第一开口131的宽度偏小，在沉积Al以形成重布线层20的过程中，第一开口131的底部和底部边缘不会沉积Al，自下而上Al沉积的厚度会越来越多，从而形成凹陷23及位于凹陷下方的气隙24，如图2所示。
在一个实施例中，第一开口131的宽度不大于3um，在保证重布线层20能够形成凹陷23的基础上，不会使得形成重布线层20的过程中，大量金属材料沉积到第一开口131内，从而在重布线层20上形成一个较大尺寸的凹陷23，以此影响重布线层20的结构性能。
在一个实施例中，第一开口131的宽度为1um-3um，不仅可以保证重布线层20能够形成凹陷23，也可以避免凹陷23的尺寸过小，从而使得凹陷23能够可靠作为测试焊盘22的光学识别图形。
在一些实施例中，第一开口131的宽度可以为1um、1.1um、1.2um、1.3um、1.5um、1.6um、1.8um、2um、2.1um、2.2um、2.3um、2.5um、2.6um、2.7um、2.8um、2.9um或者3um等等。
在一个实施例中，在基体10内形成一个第一开口131，以在重布线层20上形成一个凹陷23，如图3和图4所示，凹陷23的相对两侧分别为连接焊盘21和测试焊盘22，从而可以使得凹陷23能够作为测试焊盘22周围的光学识别图形，以此保证测试焊盘22能够实现半导体结构的电性能测试。
在一个实施例中，在基体10内形成多个第一开口131，以在重布线层20上形成多个凹陷23，如图5至图7所示，多个凹陷23形成的相对两侧分别为连接焊盘21和测试焊盘22，从而可以使得多个凹陷23共同作为测试焊盘22周围的光学识别图形，以此保证测试焊盘22能够实现半导体结构的电性能测试。
需要说明的是，对于凹陷23的数量以及具体结构形式可以不作限定，只要能够保证凹陷23可以作为测试焊盘22的光学识别图形即可。第一开口131的结构形式可以大致与凹陷23相一致，例如，第一开口131可以为一个，此时，在重布线层20上可以形成一个凹陷23。或者，第一开口131可以为多个，此时，在重布线层20上可以形成多个凹陷23。第一开口131的开口宽度可以均相一致。第一开口131的开口宽度可以呈渐缩式变化。
在一些实施例中，第一开口131可以为一个，第一开口131的开口宽度可以均相一致，从而可以使得形成的凹陷23的开口宽度均相一致，如图3所示。
在一些实施例中，第一开口131可以为一个，第一开口131的开口宽度的至少部分呈渐缩式变化，从而可以使得形成的凹陷23的开口宽度的至少部分呈渐缩式变化，如图4所示。
在一些实施例中，第一开口131可以为多个，例如，第一开口131可以为两个，两个第一开口131可以间隔设置，从而可以使得形成的两个凹陷23间隔设置，如图5所示。
在一些实施例中，第一开口131可以为多个，多个第一开口131可以沿第一方向间隔设置，第一方向基本平行于测试焊盘22朝向连接焊盘21的边缘线，从而可以使得形成的多个凹陷23沿第一方向间隔设置，如图6所示。
在一些实施例中，第一开口131可以为多个，沿垂直于第一方向的第二方向多个第一 开口131可以为至少两行，从而可以形成至少两行凹陷23，例如，第一开口131可以为两行，从而形成了两行凹陷23，如图7所示。在一个实施例中，重布线层20朝向第一开口131的一侧形成有气隙24，从而可以使得凹陷23的下方形成空气隔离，因此也可以保证在形成重布线层20的过程中在重布线层20的上表面形成有凹陷23，如图2所示。
在一个实施例中，如图2所示，基体10包括在衬底11、以及在衬底11上依次形成的导电层12和介质层13，第一开口131形成于介质层13上，重布线层20形成于介质层13上，并且重布线层20与导电层12相连接。介质层13上形成有第一开口131，从而可以在介质层13上形成重布线层20的过程中，在重布线层20上形成凹陷23，以此简化半导体结构的制作难度，提高半导体结构的制作效率。
在一个实施例中，衬底11上可以形成有多个导电层12，重布线层20可以与一个导电层12相连接，例如，在介质层13上形成一个通孔，通孔可以暴露一个导电层12，通过在通孔内沉积金属材料，以此在形成重布线层20的过程中实现重布线层20与导电层12的电连接。
在一个实施例中，第一开口131暴露导电层12，即第一开口131可以是通孔，以此增加第一开口131的深度，从而保证重布线层20上能够形成可靠的凹陷23。
在某些实施例中，第一开口131可以不暴露导电层12，即第一开口131的底壁可以位于介质层13内，以此减少第一开口131形成的制作时间。
在一个实施例中，衬底11可以包括由含硅材料形成的部分。衬底11可以由任何合适的材料形成，例如，包括硅、单晶硅、多晶硅、非晶硅、硅锗、单晶硅锗、多晶硅锗以及碳掺杂硅中的至少一种。
介质层13可以为绝缘层，例如，介质层13的材料可以包括但不限于氧化硅、氮化硅和正硅酸乙酯(TEOS)等绝缘材料中的一种或多种。
导电层12由导电材料制备而成，导电层12可以由金属材料制备而成，例如，导电层12可以由铝材料制备而成，或者，导电层12可以由铜材料制备而成。重布线层20由导电材料制备而成，重布线层20可以由金属材料制备而成，例如，重布线层20可以由铝材料制备而成，或者，重布线层20可以由铜材料制备而成。
在一个实施例中，导电层12可以由铝材料制备而成，重布线层20可以由铝材料制备而成，从而可以提高导电层12与重布线层20的连接能力，保证导电层12与重布线层20形成可靠的电连接。
在一个实施例中，半导体结构的制作方法，还包括：在重布线层20上形成光学识别 层30；在光学识别层30上形成第二开口31，以暴露连接焊盘21、测试焊盘22以及凹陷23。光学识别层30可以实现对重布线层20的保护。例如，光学识别层30的反射率低于测试焊盘22的反射率，凹陷23的反射率也低于测试焊盘22的反射率，从而，光学识别层30和凹陷23可以组合以作为测试焊盘22周围的光学识别图形。
光学识别层30可以是光阻层，光学识别层30可以是聚合物层，聚合物层的材料可以包括但不限于聚酰亚胺或聚苯并噁唑等。采用光刻工艺对光学识别层30进行处理，从而形成第二开口31，第二开口31暴露连接焊盘21、测试焊盘22以及凹陷23。
在一个实施例中，光学识别层30上可以形成有多个第二开口31，多个第二开口31可以间隔设置，每个第二开口31可以同时暴露连接焊盘21、测试焊盘22以及凹陷23，例如，第二开口31可以为3个，三个第二开口31可以同时暴露相应的连接焊盘21、测试焊盘22以及凹陷23，如图8所示。
本公开的至少一个实施例还提供了一种半导体结构，请参考图2至图8，半导体结构包括：基体10；重布线层20，重布线层20位于基体10上，重布线层20包括连接焊盘21和测试焊盘22，连接焊盘21和测试焊盘22相邻设置，重布线层20形成有凹陷23，凹陷23位于连接焊盘21和测试焊盘22之间。
本公开一个实施例的半导体结构包括基体10和重布线层20，重布线层20位于基体10上，而重布线层20包括相邻设置的连接焊盘21和测试焊盘22，通过在重布线层20上形成凹陷23，且凹陷23位于连接焊盘21和测试焊盘22之间，从而可以使得凹陷23能够作为测试焊盘22一侧的光学识别图形，因此可以避免由于连接焊盘21和测试焊盘22之间不存在光学识别图形而导致测试设备在进行自动化测试时无法识别测试焊盘22而出现报错的问题，以此改善半导体结构的测试性能。
需要说明的是，在使用测试设备(例如，测试设备包括探针)对半导体结构进行电性能测试时，测试设备与测试焊盘22相接触，在此过程中，需要通过光学设备识别测试焊盘22的周向区域，如果，连接焊盘21和测试焊盘22之间不存在光学识别图形，例如，连接焊盘21和测试焊盘22直接相连通，此时，光学设备无法准确识别到测试焊盘22的位置区域，从而会出现报错，以此影响半导体结构的电性能测试。而本实施例中，通过在重布线层20上形成凹陷23，凹陷23位于连接焊盘21和测试焊盘22之间，因此，凹陷23可以作为连接焊盘21和测试焊盘22之间的光学识别图形，从而可以准备识别到测试焊盘22的位置区域，以此实现对半导体结构的电性能测试。
在一个实施例中，重布线层20上设置有光学识别层30，光学识别层30实现对重布线 层20的保护，而光学识别层30需要暴露连接焊盘21、测试焊盘22以及凹陷23，从而可以使得连接焊盘21用于与外部器件相连接，而测试焊盘22可以用于半导体结构的电性能测试。
连接焊盘21和测试焊盘22之间可以直接设置有凹陷23，即凹陷23的开口的两侧边缘分别与连接焊盘21和测试焊盘22相连接，此时，测试焊盘22周围的光学识别层30和凹陷23可以组合以作为测试焊盘22周围的光学识别图形。
在一个实施例中，基体10上设置有第一开口131，第一开口131朝向重布线层20，凹陷23在基体10上的第一正投影位于第一开口131在基体10上的第二正投影内，重布线层20上设置有光学识别层30，光学识别层30上设置有第二开口31，以暴露连接焊盘21、测试焊盘22以及凹陷23。
第一开口131的设置可以在形成重布线层20的过程中，在重布线层20上形成凹陷23，而第二开口31实现对连接焊盘21、测试焊盘22以及凹陷23的暴露，以此使得连接焊盘21用于与外部器件相连接，而测试焊盘22可以用于半导体结构的电性能测试，而凹陷23可以作为测试焊盘22周围的光学识别图形。
在一个实施例中，凹陷23为一个，凹陷23的相对两侧分别为连接焊盘21和测试焊盘22，从而可以使得凹陷23能够作为测试焊盘22周围的光学识别图形，以此保证测试焊盘22能够实现半导体结构的电性能测试。
凹陷23的开口包括第一边缘和第二边缘，第一边缘和第二边缘分别与连接焊盘21和测试焊盘22的边缘相交，凹陷23可以作为测试焊盘22周围的光学识别图形，并与测试焊盘22周围的光学识别层30共同实现对测试焊盘22的周向环绕。
在一个实施例中，如图3所示，凹陷23的开口宽度均相一致，不仅结构简单，且凹陷23的制作也较为方便，以此简化半导体结构的制作效率，并且开口宽度相一致的凹陷23可以作为测试焊盘22周围的光学识别图形。
在一个实施例中，凹陷23的开口宽度的至少部分呈渐缩式变化，以此使得凹陷23形成的图形更加方便识别，从而提高图形的识别效率。
在一个实施例中，如图4所示，凹陷23的开口宽度由相对的两个边缘区域231向中间区域232逐渐缩小，不仅可以使得凹陷23形成的图形更加方便识别，且能够保证凹陷23不会占用测试焊盘22以及连接焊盘21过多的面积，以此提高重布线层20的结构利用率。
结合图4所示，凹陷23的中间区域232的一部分开口宽度可以均相一致，而凹陷23 的两个外侧区域部分的开口宽度为变尺寸结构。在某些实施例中，不排除凹陷23整体由两个渐缩式部分组成。
在一个实施例中，凹陷23为多个，多个凹陷23形成的相对两侧分别为连接焊盘21和测试焊盘22，从而可以使得多个凹陷23共同作为测试焊盘22周围的光学识别图形，以此保证测试焊盘22能够实现半导体结构的电性能测试。
在一个实施例中，凹陷23沿第一方向延伸，多个凹陷23沿垂直于第一方向的第二方向间隔设置；其中，第一方向基本平行于测试焊盘22朝向连接焊盘21的边缘线，即测试焊盘22和连接焊盘21之间可以具有至少两个间隔设置的凹陷23。
测试焊盘22和连接焊盘21的形状大致为矩形，而测试焊盘22和连接焊盘21直接相对的边缘线基本平行，此时，测试焊盘22和连接焊盘21直接相对的边缘线的延伸方向可以为第一方向，而垂直于测试焊盘22和连接焊盘21直接相对的边缘线的方向可以为第二方向。结合图5所示，测试焊盘22和连接焊盘21之间可以具有两个间隔设置的凹陷23，凹陷23沿第一方向延伸，并且两个凹陷23沿第二方向间隔设置。
沿第一方向延伸的凹陷23的开口宽度可以均相一致，如图5所示。或者，沿第一方向延伸的凹陷23的开口宽度的至少部分呈渐缩式变化，例如，可以将图5所示的凹陷23利用图4所示的凹陷23替换。对于沿第一方向延伸的凹陷23的具体结构此处不作限定。
在一个实施例中，如图6所示，多个凹陷23沿第一方向间隔设置，第一方向基本平行于测试焊盘22朝向连接焊盘21的边缘线，从而可以使得多个独立的凹陷23共同形成了测试焊盘22的光学识别图形。
在一个实施例中，如图7所示，沿垂直于第一方向的第二方向多个凹陷23为至少两行，以此使得呈阵列的多个凹陷23共同形成了测试焊盘22的光学识别图形。
需要说明的是，对于凹陷23的数量以及具体结构形式可以不作限定，只要能够保证凹陷23可以作为测试焊盘22的光学识别图形即可。
在一个实施例中，重布线层20由导电材料制备而成，重布线层20可以由金属材料制备而成，例如，重布线层20可以由铝材料制备而成，或者，重布线层20可以由铜材料制备而成，对于重布线层20的材料此处不作限定，可以根据实际需求进行选择。
在一个实施例中，如图2所示，基体10包括：衬底11；导电层12，导电层12位于衬底11上，重布线层20与导电层12相连接；介质层13，介质层13位于衬底11上，介质层13上设置有第一开口131，凹陷23在衬底11上的第一正投影位于第一开口131在衬底11上的第二正投影内，第一开口131的设置可以在形成重布线层20的过程中，在重布 线层20上形成凹陷23，以此简化半导体结构的制作难度，提高半导体结构的制作效率。
介质层13上的第一开口131可以是孔段，孔段可以仅具有一个开口端，此开口端朝向重布线层20，从而可以在形成重布线层20的过程中，在重布线层20上形成凹陷23。介质层13上的第一开口131可以是通孔，通孔的一个开口端朝向重布线层20，从而可以在形成重布线层20的过程中，在重布线层20上形成凹陷23，介质层13的另一个开口端可以朝向导电层12。
基体10可以包括多个导电层12，重布线层20可以与一个导电层12相连接，例如，在介质层13上形成一个通孔，通孔可以暴露一个导电层12，通过在通孔内沉积金属材料，以此在形成重布线层20的过程中实现重布线层20与导电层12的电连接(图中未示出)。
在一个实施例中，导电层12由导电材料制备而成，导电层12可以由金属材料制备而成，例如，导电层12可以由铝材料制备而成，或者，导电层12可以由铜材料制备而成，对于导电层12的材料此处不作限定，可以根据实际需求进行选择。导电层12可以是金属导线。
在一个实施例中，导电层12可以由铝材料制备而成，重布线层20可以由铝材料制备而成，从而可以提高导电层12与重布线层20的连接能力，保证导电层12与重布线层20形成可靠的电连接。
在一个实施例中，衬底11可以包括由含硅材料形成的部分。衬底11可以由任何合适的材料形成，例如，包括硅、单晶硅、多晶硅、非晶硅、硅锗、单晶硅锗、多晶硅锗以及碳掺杂硅中的至少一种。
介质层13可以为聚合物层，例如，介质层13可以包括但不限于聚酰亚胺层或聚苯并恶唑层。介质层13也可以为正硅酸乙酯层(TEOS)。
在一个实施例中，重布线层20填充第一开口131的一部分，即在形成重布线层20的过程中，重布线层20的一部分会下沉至第一开口131内，从而可以在重布线层20上形成凹陷23。
需要说明的是，第一开口131的结构形式可以大致与凹陷23相一致，例如，凹陷23可以为一个，此时，第一开口131可以分为一个。或者，凹陷23可以为多个，此时，第一开口131可以分为多个。凹陷23的开口宽度均相一致，此时，第一开口131的开口宽度可以均相一致。凹陷23的开口宽度的至少部分呈渐缩式变化，此时，第一开口131的开口宽度可以呈渐缩式变化。第一开口131的结构形式可以大致与凹陷23相一致，但是并不代表凹陷23的开口宽度和第一开口131的开口宽度必须相一致。
在一个实施例中，如图2所示，重布线层20朝向第一开口131的一侧形成有气隙24，从而可以使得凹陷23的下方形成空气隔离，因此也可以保证在形成重布线层20的过程中在重布线层20的上表面形成有凹陷23。
在一个实施例中，如图2所示，第一开口131暴露导电层12，即第一开口131可以是通孔，以此增加第一开口131的深度，从而保证重布线层20上能够形成可靠的凹陷23。
在某些实施例中，第一开口131可以不暴露导电层12，即第一开口131的底壁可以位于介质层13内，以此减少第一开口131形成的制作时间。
在一个实施例中，第一开口131的宽度不大于3um，在保证重布线层20能够形成凹陷23的基础上，不会使得形成重布线层20的过程中，大量金属材料沉积到第一开口131内，从而在重布线层20上形成一个较大尺寸的凹陷23，以此影响重布线层20的结构性能。
在一个实施例中，第一开口131的宽度为1um-3um，不仅可以保证重布线层20能够形成凹陷23，也可以避免凹陷23的尺寸过小，从而使得凹陷23能够可靠作为测试焊盘22的光学识别图形。
在一些实施例中，第一开口131的宽度可以为1um、1.1um、1.2um、1.3um、1.5um、1.6um、1.8um、2um、2.1um、2.2um、2.3um、2.5um、2.6um、2.7um、2.8um、2.9um或者3um等等。
在一个实施例中，如图2所示，半导体结构还包括：光学识别层30，光学识别层30位于重布线层20上；其中，光学识别层30上设置有第二开口31，以暴露连接焊盘21、测试焊盘22以及凹陷23。光学识别层30可以实现对重布线层20的保护，并且光学识别层30和凹陷23可以组合以作为测试焊盘22周围的光学识别图形。
光学识别层30可以是光阻层，光学识别层30可以是聚合物层，聚合物层可以包括但不限于聚酰亚胺层或聚苯并噁唑层。
在一个实施例中，一个第二开口31可以同时暴露连接焊盘21、测试焊盘22以及凹陷23。
在一个实施例中，结合图8所示，连接焊盘21、测试焊盘22以及凹陷23可以是多个，光学识别层30上可以设置有多个第二开口31，每个第二开口31可以同时暴露相应的连接焊盘21、测试焊盘22以及凹陷23。
在一个实施例中，半导体结构由上述的半导体结构的制作方法形成。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者 适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和示例实施方式仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (20)

  1. 一种半导体结构，包括：
    基体；
    重布线层，所述重布线层位于所述基体上，所述重布线层包括连接焊盘和测试焊盘，所述连接焊盘和所述测试焊盘相邻设置，所述重布线层形成有凹陷，所述凹陷位于所述连接焊盘和所述测试焊盘之间。
  2. 根据权利要求1所述的半导体结构，其中，所述凹陷为一个，所述凹陷的相对两侧分别为所述连接焊盘和所述测试焊盘。
  3. 根据权利要求2所述的半导体结构，其中，所述凹陷的开口宽度均相一致。
  4. 根据权利要求2所述的半导体结构，其中，所述凹陷的开口宽度的至少部分呈渐缩式变化。
  5. 根据权利要求4所述的半导体结构，其中，所述凹陷的开口宽度由相对的两个边缘区域向中间区域逐渐缩小。
  6. 根据权利要求1所述的半导体结构，其中，所述凹陷为多个，多个所述凹陷形成的相对两侧分别为所述连接焊盘和所述测试焊盘。
  7. 根据权利要求6所述的半导体结构，其中，所述凹陷沿第一方向延伸，多个所述凹陷沿垂直于所述第一方向的第二方向间隔设置；
    其中，所述第一方向基本平行于所述测试焊盘朝向所述连接焊盘的边缘线。
  8. 根据权利要求6所述的半导体结构，其中，多个所述凹陷沿第一方向间隔设置，所述第一方向基本平行于所述测试焊盘朝向所述连接焊盘的边缘线。
  9. 根据权利要求8所述的半导体结构，其中，沿垂直于所述第一方向的第二方向多个所述凹陷为至少两行。
  10. 根据权利要求1至9中任一项所述的半导体结构，其中，所述基体包括：
    衬底；
    导电层，所述导电层位于所述衬底上，所述重布线层与所述导电层相连接；
    介质层，所述介质层位于所述衬底上，所述介质层上设置有第一开口，所述凹陷在所述衬底上的第一正投影位于所述第一开口在所述衬底上的第二正投影内。
  11. 根据权利要求10所述的半导体结构，其中，所述重布线层填充所述第一开口的一部分。
  12. 根据权利要求11所述的半导体结构，其中，所述重布线层朝向所述第一开口的一侧形成有气隙。
  13. 根据权利要求10所述的半导体结构，其中，所述第一开口暴露所述导电层。
  14. 根据权利要求10所述的半导体结构，其中，所述第一开口的宽度不大于3um。
  15. 根据权利要求10所述的半导体结构，其中，所述第一开口的宽度为1um-3um。
  16. 根据权利要求10所述的半导体结构，其中，所述半导体结构还包括：
    光学识别层，所述光学识别层位于所述重布线层上；
    其中，所述光学识别层上设置有第二开口，以暴露所述连接焊盘、所述测试焊盘以及所述凹陷。
  17. 一种半导体结构的制作方法，包括：
    提供基体；
    在所述基体内形成第一开口；
    在所述基体上形成重布线层，以使得所述重布线层的连接焊盘和测试焊盘之间形成有凹陷；
    其中，所述凹陷在所述基体上的第一正投影位于所述第一开口在所述基体上的第二正投影内。
  18. 根据权利要求17所述的半导体结构的制作方法，其中，在所述基体内形成一个所述第一开口，以在所述重布线层上形成一个所述凹陷；
    或，在所述基体内形成多个所述第一开口，以在所述重布线层上形成多个所述凹陷。
  19. 根据权利要求17所述的半导体结构的制作方法，其中，所述基体包括在衬底、以及在所述衬底上依次形成的导电层和介质层，所述第一开口形成于所述介质层上，所述重布线层形成于所述介质层上。
  20. 根据权利要求17至19中任一项所述的半导体结构的制作方法，其中，还包括：
    在所述重布线层上形成光学识别层；
    在所述光学识别层上形成第二开口，以暴露所述连接焊盘、所述测试焊盘以及所述凹陷。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101110402A (zh) * 2006-07-21 2008-01-23 东部高科股份有限公司 半导体芯片
US20200075435A1 (en) * 2018-08-29 2020-03-05 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method of the same
CN111834317A (zh) * 2019-04-18 2020-10-27 长鑫存储技术有限公司 半导体器件及其制造方法
CN111834316A (zh) * 2019-04-18 2020-10-27 长鑫存储技术有限公司 半导体器件及其制造方法
CN112582364A (zh) * 2019-09-30 2021-03-30 长鑫存储技术有限公司 焊盘结构及其形成方法、半导体器件及其形成方法
CN112582363A (zh) * 2019-09-30 2021-03-30 长鑫存储技术有限公司 焊盘结构及其形成方法、半导体器件及其形成方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101110402A (zh) * 2006-07-21 2008-01-23 东部高科股份有限公司 半导体芯片
US20200075435A1 (en) * 2018-08-29 2020-03-05 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method of the same
CN111834317A (zh) * 2019-04-18 2020-10-27 长鑫存储技术有限公司 半导体器件及其制造方法
CN111834316A (zh) * 2019-04-18 2020-10-27 长鑫存储技术有限公司 半导体器件及其制造方法
CN112582364A (zh) * 2019-09-30 2021-03-30 长鑫存储技术有限公司 焊盘结构及其形成方法、半导体器件及其形成方法
CN112582363A (zh) * 2019-09-30 2021-03-30 长鑫存储技术有限公司 焊盘结构及其形成方法、半导体器件及其形成方法

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