WO2024055685A1 - 铁电存储器、三维集成电路、电子设备 - Google Patents

铁电存储器、三维集成电路、电子设备 Download PDF

Info

Publication number
WO2024055685A1
WO2024055685A1 PCT/CN2023/103240 CN2023103240W WO2024055685A1 WO 2024055685 A1 WO2024055685 A1 WO 2024055685A1 CN 2023103240 W CN2023103240 W CN 2023103240W WO 2024055685 A1 WO2024055685 A1 WO 2024055685A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive
layer
interconnection
capacitor
ferroelectric
Prior art date
Application number
PCT/CN2023/103240
Other languages
English (en)
French (fr)
Inventor
黄凯亮
景蔚亮
殷士辉
王正波
廖恒
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2024055685A1 publication Critical patent/WO2024055685A1/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/10—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Definitions

  • the present application relates to the field of semiconductor chip technology, and in particular to a ferroelectric memory, three-dimensional integrated circuit, and electronic equipment.
  • planar integrated circuits (2D Integrated Circuit, 2D IC) are used as system-on-chip (SOC), which can no longer meet people's needs for chip function, size, and energy consumption.
  • three-dimensional stacking of multiple chips (3D Stacking) to form a three-dimensional integrated circuit (3D Integrated Circuit, 3D IC) can improve the bandwidth and energy efficiency of the interconnection between multiple chips. Therefore, three-dimensional integrated circuits are gradually receiving attention in the field. focus on.
  • Decoupling Capacitor Decap
  • PDN Power Distribution Network
  • Embodiments of the present application provide a ferroelectric memory, a three-dimensional integrated circuit, and an electronic device, aiming to improve the anti-interference ability of the decoupling capacitor in the chip.
  • a ferroelectric memory is provided.
  • the ferroelectric memory can be a ferroelectric random access memory (Ferroelectric Random Access Memory, FeRAM) or a ferroelectric field effect transistor (Ferroelectric Field Effect Transistor, FeFET) memory. Data can be read and written.
  • the above-mentioned ferroelectric memory includes an array area and a wiring area.
  • the ferroelectric memory includes a memory array arranged in the array area, and a capacitor arranged in the wiring area.
  • the capacitor includes a first stacked layer, a first conductive pillar, a second conductive pillar, a first ferroelectric layer and a second ferroelectric layer.
  • the first stacked layer includes a plurality of conductive layers and a plurality of first dielectric layers that are alternately stacked.
  • the plurality of conductive layers includes connected first conductive parts and second conductive parts.
  • the first conductive pillar penetrates the first conductive part, and the second conductive pillar penetrates the second conductive part.
  • the first ferroelectric layer and the second ferroelectric layer have a cylindrical structure.
  • the first ferroelectric layer penetrates the first conductive part and is arranged around the first conductive pillar.
  • the second ferroelectric layer penetrates the second conductive part and surrounds the second conductive pillar.
  • the capacitor includes a first capacitor and a second capacitor arranged in series.
  • the first capacitor includes a first conductive pillar, a first ferroelectric layer and a first conductive part.
  • the second capacitor includes a second conductive pillar, a second ferroelectric layer and a first conductive part. 2.
  • Conductive part
  • the ferroelectric memory uses a first conductive pillar to penetrate the first conductive part of the conductive layer, and uses a first ferroelectric layer to surround the first conductive pillar to connect the first conductive pillar and the first conductive pillar.
  • the conductive parts are separated, the first conductive pillar, the first ferroelectric layer and the first conductive part form a first capacitor, and the first conductive pillar and the first conductive part serve as two poles of the first capacitor.
  • a second conductive pillar is used to penetrate the second conductive part of the conductive layer, and a second ferroelectric layer is used to surround the second conductive pillar to separate the second conductive pillar from the second conductive part.
  • the second conductive pillar and the second conductive part are The two ferroelectric layers and the second conductive part form a second capacitor, and the second conductive pillar and the second conductive part serve as two poles of the second capacitor.
  • one pole of the first capacitor is electrically connected to one pole of the second capacitor, so that the first capacitor and the second capacitor are arranged in series.
  • the potential difference between the two ends of each capacitor can be reduced, thereby reducing the probability of polarization flipping of the ferroelectric layer in the capacitor, ensuring the capacitance of the capacitor is stable, and improving the anti-interference ability of the capacitor.
  • each conductive layer includes at least one first conductive part and at least one second conductive part, and the connected first conductive part and the second conductive part are in the same conductive layer, so that the first conductive part and the second conductive part Conductive connection.
  • each conductive layer includes a first conductive portion and a second conductive portion, and the first conductive portion and the second conductive portion
  • the electrical parts are connected, the first conductive part and the second conductive part are arranged along a first direction, and the first direction is parallel to the bottom surface of the first stacked layer.
  • the plurality of first conductive pillars penetrate the first conductive part, which is equivalent to a plurality of first capacitors arranged in parallel.
  • the plurality of second conductive pillars penetrate the second conductive part, which is equivalent to a plurality of second capacitors arranged in parallel.
  • the first conductive part and the second conductive part of the same conductive layer are connected, so that a plurality of parallel first capacitors and a plurality of parallel second capacitors are connected in series to form a third capacitor.
  • the total capacitance value of multiple first capacitors connected in parallel is greater than the capacitance value of one first capacitor
  • the total capacitance value of multiple second capacitors connected in parallel is greater than the capacitance value of one second capacitor.
  • a third capacitor can be added. capacitance value, thus increasing the total capacitance value of the capacitor.
  • a plurality of first capacitors connected in parallel and a plurality of second capacitors connected in parallel are connected in series to form a third capacitor, which can reduce the potential difference between the two ends of the multiple capacitors (first capacitors or second capacitors) connected in parallel and reduce the voltage of each capacitor.
  • the potential difference between the two ends of the capacitor can reduce the probability of polarization flipping of the ferroelectric layer in the capacitor, ensure the stability of the capacitance value, and improve the anti-interference ability of the capacitor.
  • the capacitor further includes a first interconnection electrode and a second interconnection electrode, the first interconnection electrode and the second interconnection electrode are planar structures, and the first interconnection electrode and the second interconnection electrode are arranged along the first direction.
  • the first interconnection electrode is electrically connected to the ends of the plurality of first conductive pillars to transmit electrical signals to the plurality of first conductive pillars through the first interconnection electrode.
  • the second interconnection electrode is electrically connected to ends of the plurality of second conductive pillars to transmit electrical signals to the plurality of second conductive pillars through the second interconnection electrode.
  • a plurality of first conductive pillars are arranged in an array, and/or a plurality of second conductive pillars are arranged in an array, which can improve the performance of the plurality of first conductive pillars and the plurality of second conductive pillars.
  • the uniformity of the cloth is helpful to improve the signal interference between multiple capacitors.
  • the capacitor further includes a first interconnection electrode and a second interconnection electrode.
  • the first interconnection electrode and the second interconnection electrode are in a comb-like structure.
  • the first interconnection electrode and the second interconnection electrode are arranged along the first direction.
  • the first interconnection electrode and the second interconnection electrode are arranged in a first direction.
  • the interconnection electrode includes a plurality of first interconnection lines
  • the second interconnection electrode includes a plurality of second interconnection lines.
  • the first interconnection lines and the second interconnection lines extend along the first direction, the plurality of first interconnection lines are electrically connected to the ends of the plurality of first conductive pillars, and the plurality of first interconnection lines are along the first stacked layer. Connect on one side of the direction.
  • the plurality of second interconnection lines are electrically connected to ends of the plurality of second conductive pillars, and the plurality of second interconnection lines are connected on the other side of the first stacked layer along the first direction.
  • first interconnection lines and the second interconnection lines extend along the second direction
  • the plurality of first interconnection lines are electrically connected to ends of the plurality of first conductive pillars
  • the plurality of first interconnection lines are along the edge of the first stack layer.
  • One side of the second direction is connected.
  • the plurality of second interconnection lines are electrically connected to ends of the plurality of second conductive pillars
  • the plurality of second interconnection lines are connected on one side of the first stacked layer along the second direction, and the second direction is parallel to the first stacked layer.
  • the bottom surface of and intersects with the first direction.
  • each conductive layer includes a plurality of first conductive parts and a plurality of second conductive parts, the plurality of first conductive parts are connected to a plurality of second conductive parts, and the first conductive parts and the second conductive parts are arranged along the The first directions are alternately arranged, and the first direction is parallel to the bottom surface of the first stacked layer.
  • a plurality of first conductive pillars penetrates the first conductive part, and a plurality of second conductive pillars penetrates the second conductive part.
  • a plurality of first conductive pillars penetrate the first conductive part, which is equivalent to a plurality of first capacitors arranged in parallel.
  • the plurality of second conductive pillars penetrate the second conductive part, which is equivalent to a plurality of second capacitors arranged in parallel.
  • a plurality of first conductive parts on the same conductive layer are connected to a plurality of second conductive parts, so that a plurality of parallel-connected first capacitors and a plurality of parallel-connected second capacitors are connected in series to form a third capacitor.
  • each capacitor By connecting capacitors in series, the potential difference between the two ends of each capacitor can be reduced, thereby reducing the probability of polarization flipping of the ferroelectric layer in the capacitor, ensuring the capacitance of the capacitor is stable, and improving the anti-interference ability of the capacitor.
  • the capacitor further includes a first interconnection electrode and a second interconnection electrode, and the first interconnection electrode and the second interconnection electrode are in a comb-shaped structure.
  • the first interconnection electrode includes a plurality of first interconnection lines
  • the second interconnection electrode includes a plurality of second interconnection lines
  • the plurality of first interconnection lines and the plurality of second interconnection lines are arranged along the first direction
  • the first interconnection lines and the second interconnection lines The interconnection lines extend in the second direction.
  • the plurality of first interconnection lines are electrically connected to the ends of the plurality of first conductive pillars, and the plurality of first interconnection lines are connected on one side of the first stacked layer along the second direction, through the plurality of first interconnection electrodes.
  • An interconnection wire transmits electrical signals to a plurality of first conductive pillars.
  • the plurality of second interconnection lines are electrically connected to ends of the plurality of second conductive pillars, and the plurality of second interconnection lines are connected on the other side of the first stacked layer along the second direction, through the plurality of second interconnection electrodes.
  • the second interconnection wire transmits electrical signals to the plurality of second conductive pillars.
  • the plurality of first interconnection lines and the plurality of second interconnection lines are alternately arranged along the first direction.
  • the first interconnection line is not limited to, but not limited to, but not limited to, but not limited to, but not limited to, but not limited to two adjacent first interconnection lines, or there are multiple second interconnection lines.
  • the plurality of first conductive pillars include multiple rows, and a first interconnection line is electrically connected to a row of first conductive pillars, so as to Electrical signals are transmitted to a row of first conductive pillars through a first interconnection line.
  • the plurality of second conductive pillars include multiple rows, and a second interconnection line is electrically connected to a row of second conductive pillars to transmit electrical signals to a row of second conductive pillars through the second interconnection line.
  • the first conductive part and the second conductive part on the same conductive layer are integrally provided to realize the connection between the first conductive part and the second conductive part.
  • each conductive layer includes a plurality of conductive blocks arranged separately, one conductive block includes a first conductive part and a second conductive part connected, and a plurality of first conductive pillars penetrate the first conductive part of the conductive block. part, which is equivalent to a plurality of first capacitors arranged in parallel.
  • the plurality of second conductive pillars penetrate the second conductive portion of the conductive block, which is equivalent to a plurality of second capacitors arranged in parallel.
  • the first conductive part and the second conductive part of the same conductive block are connected, so that a plurality of parallel first capacitors and a plurality of parallel second capacitors are connected in series to form a third capacitor.
  • a plurality of second conductive pillars penetrating one conductive block are electrically connected to a plurality of first conductive pillars penetrating the other conductive block, so that the third capacitors of the adjacent conductive blocks are connected in series to form a third capacitor.
  • the total capacitance value of multiple first capacitors connected in parallel is greater than the capacitance value of one first capacitor
  • the total capacitance value of multiple second capacitors connected in parallel is greater than the capacitance value of one second capacitor.
  • a third capacitor can be added. The capacitance value of the fourth capacitor is increased, thereby increasing the total capacitance value of the capacitor.
  • a plurality of first capacitors connected in parallel and a plurality of second capacitors connected in parallel are connected in series to form a third capacitor, and the third capacitors of adjacent conductive blocks are connected in series to form a fourth capacitor, so as to increase the number of capacitors connected in series, thereby enabling It further reduces the potential difference between the two ends of each capacitor, reduces the probability of polarization flipping of the ferroelectric layer in the capacitor, ensures the stability of the capacitance value, and improves the anti-interference ability of the capacitor.
  • the capacitor further includes a second dielectric layer that penetrates the first stacked layer and separates two adjacent conductive blocks. That is, the second dielectric layer divides the conductive layer into multiple conductive blocks.
  • each conductive layer includes a first conductive block to an nth conductive block arranged in sequence, n ⁇ 2, and n is a positive integer.
  • the capacitor also includes a first interconnection electrode, at least a second interconnection electrode and a third interconnection electrode, and the first interconnection electrode is electrically connected to the first conductive pillar penetrating the first conductive block.
  • the third interconnection electrode is electrically connected to the second conductive pillar penetrating the nth conductive block.
  • the first interconnection electrode and the third interconnection electrode receive external electrical signals and transmit the electrical signals to the fourth capacitor.
  • the plurality of conductive layers include a plurality of first conductive portions and a plurality of second conductive portions, and the plurality of second conductive portions are located on a side of the plurality of first conductive portions away from the bottom surface of the first stacked layer.
  • the plurality of first conductive pillars penetrate the plurality of first conductive parts, which is equivalent to a plurality of first capacitors arranged in parallel.
  • the plurality of second conductive pillars penetrate the plurality of second conductive parts, which is equivalent to a plurality of second capacitors arranged in parallel.
  • the capacitor also includes a third conductive pillar penetrating the first stacked layer.
  • the third conductive pillar is electrically connected to the plurality of first conductive parts and the plurality of second conductive parts, so that the plurality of parallel-connected first capacitors are connected to the plurality of parallel-connected second conductive parts.
  • Capacitors in series.
  • the total capacitance value of multiple first capacitors connected in parallel is greater than the capacitance value of one first capacitor
  • the total capacitance value of multiple second capacitors connected in parallel is greater than the capacitance value of one second capacitor, which can increase the total capacitance value of the capacitors. capacitance value.
  • multiple first capacitors connected in parallel and multiple second capacitors connected in parallel in series can reduce the potential difference between the two ends of the multiple capacitors in parallel (the first capacitor or the second capacitor), and reduce the potential difference between the two ends of each capacitor. This can reduce the probability of polarization flipping of the ferroelectric layer in the capacitor, ensure the stability of the capacitance value, and improve the anti-interference ability of the capacitor.
  • the capacitor further includes a first interconnection electrode and a second interconnection electrode.
  • the first interconnection electrode is disposed on a side of the bottom surface of the first stack layer away from the plurality of first conductive portions and is connected to the plurality of first conductive portions.
  • the ends of the pillars are electrically connected, and electrical signals are transmitted to the plurality of first conductive pillars through the first interconnection electrodes.
  • the second interconnection electrode is disposed on a side of the plurality of second conductive portions away from the bottom surface of the first stacked layer and is electrically connected to the ends of the plurality of second conductive pillars.
  • the second interconnection electrode is connected to the plurality of second conductive pillars. Transmit electrical signals.
  • the conductive layer, the first conductive pillar and the second conductive pillar are made of materials including at least one of Ti, Au, W, Mo, Al, Cu, Ru, Ag, TiN, and ITO.
  • the material of the first ferroelectric layer and/or the second ferroelectric layer includes at least one of ZrO 2 , HfO 2 , HfAlO, HfSiO, HfZrO, HfLaO, and HfYO.
  • the first dielectric layer has a single-layer structure or a stacked structure, and the materials of the first dielectric layer include SiO 2 , Al 2 O 3 , At least one of HfO 2 , ZrO 2 , TiO 2 , Y 2 O 3 , and Si 3 N 4 .
  • the memory array includes a second stacked layer including a plurality of memory cells arranged in an array.
  • the second stacked layer includes alternately arranged third dielectric layers and gate electrode layers.
  • the plurality of first dielectric layers of the first stacked layer correspond to the plurality of third dielectric layers of the second stacked layer.
  • the corresponding first dielectric layers The material of the layer and the third dielectric layer are the same and are arranged on the same layer.
  • the plurality of conductive layers of the first stacked layer correspond to the plurality of gate electrode layers of the second stacked layer.
  • the corresponding conductive layers and the gate electrode layers are made of the same material, are arranged in the same layer, and are insulated from each other.
  • a method for preparing a ferroelectric memory includes: forming a first stacked layer.
  • the first stacked layer includes a plurality of conductive layers and a plurality of first dielectric layers that are alternately stacked.
  • the plurality of conductive layers are The layer includes connected first conductive portions and second conductive portions.
  • a first contact hole penetrating the first conductive part and a second contact hole penetrating the second conductive part are formed.
  • a first ferroelectric layer is formed on the side wall of the first contact hole, and a second ferroelectric layer is formed on the side wall of the second contact hole.
  • a first conductive pillar is formed inside the first ferroelectric layer, and a second conductive pillar is formed inside the second ferroelectric layer.
  • the preparation method provided by the above embodiments of the present application first forms a first stacked layer.
  • the first stacked layer includes a plurality of conductive layers and a plurality of first dielectric layers that are alternately stacked.
  • One conductive layer includes connected first conductive parts. and a second conductive portion. Then, a first contact hole penetrating the first conductive part and a second contact hole penetrating the second conductive part are formed, a first ferroelectric layer and a first conductive pillar are formed on the side wall of the first contact hole, and a first ferroelectric layer and a first conductive pillar are formed on the side wall of the first contact hole.
  • a second ferroelectric layer and a second conductive pillar are formed on the sidewall of the contact hole.
  • the first conductive pillar, the first ferroelectric layer and the first conductive part form a first capacitor, and the first conductive pillar and the first conductive part serve as two poles of the first capacitor.
  • the second conductive pillar, the second ferroelectric layer and the second conductive part form a second capacitor, and the second conductive pillar and the second conductive part serve as two poles of the second capacitor.
  • the method further includes: forming first interconnection electrodes and second interconnection electrodes, the first interconnection electrodes being electrically connected to ends of the plurality of first conductive pillars, to Electrical signals are transmitted to the plurality of first conductive pillars.
  • the second interconnection electrode is electrically connected to the ends of the plurality of second conductive pillars to transmit electrical signals to the plurality of second conductive pillars.
  • the method further includes: forming at least one isolation trench penetrating the first stacked layer.
  • the at least one isolation trench separates the conductive layer into a plurality of conductive blocks, and each conductive block includes a first conductive block.
  • a conductive part and a second conductive part, the first conductive part is connected to the second conductive part.
  • a second dielectric layer is formed within the isolation trench.
  • the first stacked layer is etched to form an isolation trench penetrating the first stacked layer, and a second dielectric layer is formed in the isolation trench to divide the conductive layer into multiple conductive blocks to increase series connection.
  • the number of capacitors can further reduce the potential difference between the two ends of each capacitor, reduce the probability of polarization flipping of the ferroelectric layer in the capacitor, ensure the stability of the capacitance of the capacitor, and improve the anti-interference ability of the capacitor.
  • each conductive layer includes a first conductive block to an nth conductive block arranged in sequence, n ⁇ 2, and n is a positive integer.
  • first conductive pillar and the second conductive pillar After forming the first conductive pillar and the second conductive pillar, it also includes: forming a first interconnection electrode, at least one second interconnection electrode and a third interconnection electrode, the first interconnection electrode and the first conductive electrode penetrating the first conductive block.
  • the third interconnection electrode is electrically connected to the second conductive pillar penetrating the nth conductive block.
  • the ferroelectric memory includes an array area and a wiring area. During the formation of the first stacked layer in the wiring area, a second stacked layer is simultaneously formed in the array area.
  • a method for manufacturing a ferroelectric memory includes: forming a first sub-stacked layer.
  • the first sub-stacked layer includes a plurality of first conductive parts and a plurality of first media arranged in an alternating stack. layer.
  • First contact holes are formed penetrating the plurality of first conductive parts.
  • a first ferroelectric layer is formed on the sidewall of the first contact hole.
  • a first conductive pillar is formed inside the first ferroelectric layer.
  • An insulating layer is formed, covering the first sub-stacked layer, the first ferroelectric layer and the first conductive pillar.
  • a second sub-stacked layer is formed on a side of the insulating layer away from the first sub-stacked layer.
  • the second sub-stacked layer includes a plurality of second conductive portions and a plurality of first dielectric layers that are alternately stacked. Second contact holes are formed penetrating the plurality of second conductive portions. A second ferroelectric layer is formed on the sidewall of the second contact hole. A second conductive pillar is formed inside the second ferroelectric layer. A third conductive pillar is formed, which penetrates the second sub-stacked layer, the insulating layer and the first sub-stacked layer, and is electrically connected to the plurality of first conductive parts and the plurality of second conductive parts.
  • a first sub-stacked layer is first formed.
  • the first sub-stacked layer includes a plurality of first conductive parts and a plurality of first dielectric layers that are alternately stacked.
  • a first contact hole is formed that penetrates the plurality of first conductive parts, and a first ferroelectric layer and a first conductive pillar are formed on the side walls of the first contact hole.
  • a second sub-stacked layer is formed above the first sub-stacked layer, the second sub-stacked layer comprising a plurality of second conductive portions and a plurality of first dielectric layers alternately stacked.
  • a second contact hole is formed penetrating through the plurality of second conductive portions, and a second ferroelectric layer and a second conductive column are formed on the sidewall of the second contact hole.
  • a third conductive pillar is formed that penetrates the second sub-stacked layer and the first sub-stacked layer.
  • the third conductive pillar is electrically connected to the plurality of first conductive parts and the plurality of second conductive parts, so that the multiple first capacitors in parallel are Being connected in series with multiple second capacitors connected in parallel can reduce the potential difference between the two ends of each capacitor, thereby reducing the probability of polarization flipping of the ferroelectric layer in the capacitor, ensuring the capacitance of the capacitor is stable, and improving the anti-interference ability of the capacitor.
  • a three-dimensional integrated circuit in a fourth aspect, includes the ferroelectric memory and a processor chip described in any of the above embodiments.
  • the processor chip is stacked on the ferroelectric memory and is electrically connected to the ferroelectric memory. .
  • an electronic device is provided.
  • the electronic device is, for example, a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product.
  • the electronic device includes a circuit board and the ferroelectric memory or three-dimensional integrated circuit described in any of the above embodiments.
  • the ferroelectric memory or three-dimensional integrated circuit is disposed on the circuit board and is electrically connected to the circuit.
  • Figure 1 is an architectural diagram of an electronic device according to some embodiments.
  • Figure 2 is an exploded view of an electronic device according to some embodiments.
  • Figure 3 is a structural diagram of a three-dimensional integrated circuit according to some embodiments.
  • Figure 4 is a top view of a ferroelectric memory according to some embodiments.
  • Figure 5 is an architectural diagram of a memory array of a ferroelectric memory according to some embodiments.
  • Figure 6 is a structural diagram of a decoupling capacitor in the related art
  • Figure 7 shows the hysteresis loop diagram of ferroelectric materials in ferroelectric capacitors
  • Figure 8 is a graph showing the relationship between the capacitance value of a ferroelectric capacitor and the potential difference between its two poles before and after polarization flip;
  • Figure 9 is a structural diagram of a capacitor according to some embodiments.
  • Figure 10 is a top view of the capacitor in Figure 9;
  • Figure 11 is a cross-sectional view of the capacitor in Figure 10 along section line A-A';
  • Figure 12 is an equivalent circuit diagram of the capacitor in Figure 11;
  • Figure 13 is a partial enlarged view of the capacitor in Figure 11 at M;
  • Figure 14 is an equivalent circuit diagram of the capacitor in Figure 13;
  • Figure 15 is a top view of another capacitor according to some embodiments.
  • Figures 16 and 17 are top views of another capacitor according to some embodiments.
  • Figure 18 is a top view of another capacitor according to some embodiments.
  • Figure 19 is an equivalent circuit diagram of the capacitor in Figure 18;
  • Figure 20 is a top view of yet another capacitor according to some embodiments.
  • Figure 21 is an equivalent circuit diagram of the capacitor in Figure 20;
  • Figures 22A to 22E are diagrams of steps for preparing a capacitor according to some embodiments.
  • Figure 23 is a top view of yet another capacitor according to some embodiments.
  • Figure 24 is a cross-sectional view of the capacitor in Figure 23 along section line B-B';
  • Figure 25 is an equivalent circuit diagram of the capacitor in Figure 24;
  • Figures 26A to 26G are diagrams of steps for preparing another capacitor according to some embodiments.
  • Figure 27 is a cross-sectional view of yet another capacitor according to some embodiments.
  • Figure 28 is an equivalent circuit diagram of the capacitor in Figure 27;
  • 29A to 29K are diagrams of steps for preparing yet another capacitor according to some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of this application, unless otherwise specified, "plurality” means two or more.
  • connection and its derivatives may be used.
  • some embodiments may be described using the term “connected” to indicate that two or more components are in direct physical or electrical contact with each other.
  • At least one of A, B, C includes the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and A , combination of B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • “same layer” refers to a layer structure formed by using the same film formation process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • Some embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (Personal Digital Assistant, PDA), a television, or a smart wearable product (for example, a smart watch, a smart bracelet) , Virtual Reality (VR) terminal equipment, Augmented Reality (AR) terminal equipment, charging Different types of user equipment or terminal equipment such as small household appliances (such as soymilk machines, sweeping robots), drones, radars, aerospace equipment, and vehicle-mounted equipment; the electronic equipment can also be network equipment such as base stations.
  • PDA Personal Digital Assistant
  • PDA Personal Digital Assistant
  • TV Personal Digital Assistant
  • a smart wearable product for example, a smart watch, a smart bracelet
  • VR Virtual Reality
  • AR Augmented Reality
  • charging Different types of user equipment or terminal equipment such as small household appliances (such as soymilk machines, sweeping robots), drones, radars, aerospace equipment, and vehicle-mounted equipment
  • the electronic equipment can also be network equipment such as base stations.
  • Figure 1 is an architectural diagram of an electronic device according to some embodiments.
  • the electronic device 1 includes: a storage device 11 , a processor 12 , an input device 13 , an output device 14 and other components.
  • a storage device 11 a processor 12 , an input device 13 , an output device 14 and other components.
  • the architecture of the electronic device 1 shown in Figure 1 does not constitute a limitation on the electronic device 1, and the electronic device 1 may include more or less components than those shown in Figure 1 , or some of the components shown in Figure 1 may be combined, or may be arranged differently from the components shown in Figure 1 .
  • the storage device 11 is used to store software programs and modules.
  • the storage device 11 mainly includes a storage program area and a storage data area, wherein the storage program area can store and back up an operating system, at least one application program required for a function (such as a sound playback function, an image playback function, etc.), etc.; the storage data area can store Data created according to the use of the electronic device 1 (such as audio data, image data, phone book, etc.) and the like are stored.
  • the storage device 11 includes an external memory 111 and an internal memory 112 . Data stored in the external memory 111 and the internal memory 112 can be transferred to each other.
  • the external memory 111 may include, for example, a hard disk, a USB disk, a floppy disk, etc.
  • the internal memory 112 may include, for example, random access memory (Random Access Memory, RAM), read-only memory (Read-Only Memory, ROM), etc.
  • the processor 12 is the control center of the electronic device 1, using various interfaces and lines to connect various parts of the entire electronic device 1, by running or executing software programs and/or modules stored in the storage device 11, and by calling the software programs and/or modules stored in the storage device 11.
  • the data in the device 11 executes various functions of the electronic device 1 and processes data, thereby overall monitoring the electronic device 1 .
  • the processor 12 may include one or more processing units.
  • the processor 12 may include an application processor (Application Processor, AP), a modem processor, a graphics processor (Graphics Processing Unit, GPU), etc. Among them, different processing units can be independent devices or integrated in one or more processors.
  • the processor 12 can integrate an application processor and a modem processor, where the application processor mainly processes operating systems, user interfaces, application programs, etc., and the modem processor mainly processes wireless communications. It can be understood that the above-mentioned modem processor may not be integrated into the processor 12 .
  • the above-mentioned application processor may be, for example, a central processing unit (Central Processing Unit, CPU).
  • the processor 12 is a CPU as an example.
  • the CPU may include a calculator 121 and a controller 122 .
  • the arithmetic unit 121 obtains the data stored in the internal memory 112 and processes the data stored in the internal memory 112. The processed result is usually sent back to the internal memory 112.
  • the controller 122 can control the arithmetic unit 121 to process data, and the controller 122 can also control the external memory 111 and the internal memory 112 to read or write data.
  • the input device 13 is used to receive input numeric or character information and generate key signal input related to user settings and function control of the electronic device.
  • the input device 13 may include a touch screen and other input devices.
  • the touch screen also known as the touch panel, can collect the user's touch operations on or near the touch screen (such as the user's operations on or near the touch screen using fingers, stylus, or any suitable objects or accessories), and perform operations based on preset settings.
  • the program drives the corresponding connection device.
  • the controller 122 in the above-mentioned processor 12 can also control the input device 13 to receive the input signal or not to receive the input signal.
  • the input numeric or character information received by the input device 13 and the key signal input generated related to user settings and function control of the electronic device may be stored in the internal memory 112 .
  • the output device 14 is used to output the input of the input device 13 and store signals corresponding to the data in the internal memory 112 .
  • the output device 14 outputs a sound signal or a video signal.
  • the controller 122 in the above-mentioned processor 12 can also control the output device 14 to output a signal or not to output a signal.
  • the thick arrows in Figure 1 are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission.
  • a single arrow between the input device 13 and the internal memory 112 indicates that data received by the input device 13 is transmitted to the internal memory 112 .
  • the double arrow between the operator 121 and the internal memory 112 indicates that the data stored in the internal memory 112 can be transferred to the operator 121 , and the data processed by the operator 121 can be transferred to the internal memory 112 .
  • the thin arrows in Figure 1 indicate components that controller 122 can control.
  • the controller 122 can control the external memory 111, the internal memory 112, the operator 121, the input device 13, the output device 14, and the like.
  • the following is an exemplary introduction taking the electronic device 1 as a mobile phone.
  • Figure 2 is an exploded view of an electronic device according to some embodiments.
  • the electronic device 1 may also include a middle frame 15 , a rear case 16 and a display screen 17 .
  • 16 points for the back shell and 17 points for the display They are respectively located on opposite sides of the middle frame 15 , and the middle frame 15 and the display screen 17 are arranged in the rear shell 16 .
  • the middle frame 15 includes a bearing plate 150 for bearing the display screen 17 and a frame 151 surrounding the bearing plate 150 .
  • the electronic device 1 may further include a circuit board 18 disposed on a side of the carrier plate 150 close to the rear case 16 .
  • the electronic device 1 also includes a chip 19 disposed on the circuit board 18 , and the chip 19 is electrically connected to the circuit board 18 .
  • the above-mentioned chip 19 may be a ferroelectric memory.
  • the internal memory 112 in the electronic device 1 is a ferroelectric memory, which has a high storage density.
  • the ferroelectric memory may be a ferroelectric random access memory or a ferroelectric field effect transistor memory.
  • the above-mentioned chip 19 can also be a three-dimensional integrated circuit.
  • the three-dimensional integrated circuit includes a homogeneous three-dimensional integrated circuit and a heterogeneous three-dimensional integrated circuit.
  • the homogeneous three-dimensional integrated circuit includes multi-layer active devices integrated along its thickness direction, and has the advantages of low cost, Features include high dimensional accuracy.
  • Heterogeneous three-dimensional integrated circuits include integrated multiple chips with different process architectures, different instruction sets or different functions. That is, heterogeneous three-dimensional integrated circuits incorporate different semiconductor materials, semiconductor processes, semiconductor structures or semiconductor devices. .
  • Figure 3 is a structural diagram of a three-dimensional integrated circuit according to some embodiments.
  • the three-dimensional integrated circuit 2 includes two chips of three-dimensional stacking (3D stacking).
  • One chip can be a ferroelectric memory 21, for example, and the other chip can be a processor chip 22, for example, and the two are electrically connected.
  • the processor chip 22 may be composed of multiple logic chips.
  • the multiple logic chips are stacked on the ferroelectric memory 21 and are electrically connected to the ferroelectric memory 21 .
  • the processor chip 22 may also adopt a system-on-chip (SOC) structural design.
  • SOC system-on-chip
  • the system-on-chip is stacked on the ferroelectric memory 21 and is electrically connected to the ferroelectric memory 21 .
  • the above-mentioned three-dimensional integrated circuit 2 is a heterogeneous three-dimensional integrated circuit, which has a large memory access bandwidth (Memory Bandwidth). Therefore, the three-dimensional integrated circuit 2 is suitable for application scenarios with large bandwidth requirements, such as artificial intelligence or data processing. Application scenarios.
  • the decoupling capacitor may be provided in the processor chip 22 of the three-dimensional integrated circuit 2 or in the ferroelectric memory 21 .
  • FIG. 4 is a top view of a ferroelectric memory according to some embodiments
  • FIG. 5 is an architectural diagram of a memory array of a ferroelectric memory according to some embodiments.
  • the ferroelectric memory 21 includes an array area A1 and a wiring area A2.
  • the ferroelectric memory 21 may include a memory array disposed in the array area A1.
  • the memory array includes a second stacked layer D, and the second stacked layer D includes a plurality of memory cells U arranged in an array.
  • multiple memory cells U form a memory cell string 100.
  • the multiple memory cell strings 100 may form a memory array, and the source layer SL may be electrically connected to the sources of the multiple memory cell strings 100.
  • the memory unit U may include one transistor T. Along the direction Z, multiple transistors T are connected together to form the memory cell string 100 .
  • the transistor T is a ferroelectric field effect transistor.
  • the control electrode of the ferroelectric field effect transistor is electrically connected to the word line (WL1, WL2...WLm-1, WLm), and the source electrode is connected to the source layer.
  • SL is electrically connected, the drain is electrically connected to the bit lines (BL1, BL2...BLn-1, BLn), and the material of the gate dielectric layer of the ferroelectric field effect transistor is ferroelectric material.
  • the ferroelectric field effect transistor stores data by changing the polarity of the ferroelectric layer through voltage pulses, and obtains the stored data by reading the current of the transistor. Its reading mechanism is non-destructive and has a high density.
  • the number of transistors T in the memory cell string 100 in FIG. 5 is only illustrative.
  • the memory cell string 100 of the ferroelectric memory 21 provided in the embodiment of the present application may also include other numbers of transistors T, such as 8, 16, 32, 64.
  • the ferroelectric memory 21 further includes a capacitor disposed in the wiring area A2 , and the capacitor includes the first stacked layer 30 .
  • the capacitor can be used, for example, as a decoupling capacitor. A decoupling capacitor in the related art is introduced below.
  • FIG. 6 is a structural diagram of a decoupling capacitor in the related art.
  • the decoupling capacitor 3' includes a first conductive layer 31' and a second conductive layer 32', and a dielectric layer 33' disposed between them.
  • the material of the dielectric layer 33' can be a ferroelectric material, such as iron.
  • the dielectric constant of the electrical material is relatively large, which is beneficial to increasing the capacitance value of the decoupling capacitor 3'.
  • the decoupling capacitor 3' is a ferroelectric capacitor.
  • Ferroelectric capacitors have a coercive electric field.
  • the ferroelectric domains in the ferroelectric material undergo polarization flipping, and the ferroelectric capacitor changes from one polarization state to another.
  • Figure 7 is a hysteresis loop diagram of the ferroelectric material in the ferroelectric capacitor.
  • the abscissa "V” represents the potential difference between the two poles of the ferroelectric capacitor; the ordinate “P” represents the polarization intensity of the ferroelectric material.
  • the ferroelectric domain in the ferroelectric material undergoes polarization flipping, and the polarization intensity of the ferroelectric material changes. That is, the polarization state of the ferroelectric capacitor changes. For example, the ferroelectric capacitor changes from the "0" state to the "1" state.
  • Figure 8 is a graph showing the relationship between the capacitance value of a ferroelectric capacitor and the potential difference between its two poles before and after polarization flipping.
  • the abscissa “V” represents: the potential difference between the two poles of the ferroelectric capacitor; the ordinate “C” represents: the potential difference between the two poles of the ferroelectric capacitor.
  • Capacitance value; Curve “1” is: the relationship curve between the capacitance value of the ferroelectric capacitor and the potential difference between its two poles before the polarization flip; curve “2” is: the relationship curve between the capacitance value of the ferroelectric capacitor and the potential difference between its two poles after the polarization flip. .
  • the capacitance value of the ferroelectric capacitor before the polarization flip is greater than the capacitance value of the ferroelectric capacitor after the polarization flip.
  • Figure 9 is a structural diagram of a capacitor according to some embodiments;
  • Figure 10 is a top view of the capacitor in Figure 9;
  • Figure 11 is an edge view of the capacitor in Figure 10 The cross-sectional view of the section line A-A';
  • Figure 12 is the equivalent circuit diagram of the capacitor in Figure 11;
  • Figure 13 is the partial enlarged view of the capacitor in Figure 11 at M;
  • Figure 14 is the equivalent circuit diagram of the capacitor in Figure 13.
  • the capacitor 3 includes a first stacked layer 30 .
  • the first stacked layer 30 includes a plurality of conductive layers 31 and a plurality of first dielectric layers 32 that are alternately stacked. That is, two adjacent conductive layers 31 are separated by a first dielectric layer. separated by 32 layers.
  • the number of the conductive layer 31 and the first dielectric layer 32 in FIG. 9 is only for illustration, and the embodiments of the present application do not limit this.
  • the aforementioned second stacked layer D provided in the array area A1 includes alternately arranged dielectric layers and gate layers.
  • the plurality of first dielectric layers 32 of the first stacked layer 30 and the second stacked layer D are The multiple dielectric layers of layer D correspond one to one, and the corresponding first dielectric layer and the dielectric layer of the second stacked layer D are made of the same material and are arranged in the same layer.
  • the plurality of conductive layers 31 of the first stacked layer 30 correspond to the plurality of gate electrode layers of the second stacked layer D.
  • the corresponding conductive layers 31 and the gate electrode layers are made of the same material and are arranged in the same layer.
  • the conductive layer 31 of the first stacked layer 30 is insulated from the gate layer of the second stacked layer D.
  • the first stacked layer 30 is provided in the routing area A2, and the second stacked layer D is provided in the array area A1.
  • the first stacked layer 30 and the second stacked layer D are disposed in different areas and are discontinuous, that is, the conductive layer 31 of the first stacked layer 30 and the gate layer of the second stacked layer D are disconnected.
  • the plurality of conductive layers 31 include connected first conductive parts 31 a and second conductive parts 31 b.
  • a conductive layer 31 includes a first conductive part 31a and a second conductive part 31b, and the first conductive part 31a and the second conductive part 31b of the same conductive layer 31 are in the same conductive layer, And the two are connected.
  • the capacitor 3 also includes a first conductive pillar 33 and a second conductive pillar 34.
  • the first conductive pillar 33 penetrates the first conductive part 31a, and the second conductive pillar 34 penetrates the second conductive part 31b.
  • each first conductive pillar 33 penetrates the first conductive portions 31 a of the plurality of conductive layers 31
  • each second conductive pillar 34 penetrates the second conductive portions 31 b of the plurality of conductive layers 31 .
  • the capacitor 3 also includes a first ferroelectric layer 35 and a second ferroelectric layer 36 . Both the first ferroelectric layer 35 and the second ferroelectric layer 36 are cylindrical structures.
  • the first ferroelectric layer 35 penetrates the first conductive part 31a and is arranged around the first conductive pillar 33.
  • the first ferroelectric layer 35 is located between the first conductive pillar 33 and the first conductive part 31a to achieve the first electrical conductivity.
  • the pillar 33 is insulated from the first conductive portion 31a.
  • the second ferroelectric layer 36 penetrates the second conductive part 31b and is provided around the second conductive pillar 34.
  • the second ferroelectric layer 36 is located between the second conductive pillar 34 and the second conductive part 31b to realize the second conductive pillar 34. Insulation from the second conductive part 31b.
  • each first ferroelectric layer 35 penetrates the first conductive portions 31 a of the plurality of conductive layers 31 and is disposed around the first conductive pillars 33 to connect the first conductive pillars 33 with the plurality of conductive pillars 33 .
  • the first conductive portions 31a of the conductive layer 31 are spaced apart.
  • Each second ferroelectric layer 36 penetrates the second conductive portions 31b of the plurality of conductive layers 31 and is disposed around the second conductive pillars 34 to isolate the second conductive pillars 34 from the second conductive portions 31b of the plurality of conductive layers 31. open.
  • the first conductive pillar 33 , the first ferroelectric layer 35 and the first conductive portion 31 a are configured to form the first capacitor C1
  • the first conductive pillar 33 and the first conductive portion 31 a Part 31a is the two poles of the first capacitor C1.
  • the second conductive pillar 34, the second ferroelectric layer 36 and the second conductive portion 31b are configured to form a second capacitor C2.
  • the second conductive pillar 34 and the second conductive portion 31b are the two poles of the second capacitor C2, and the first Capacitor C1 and second capacitor C2 are both ferroelectric capacitors.
  • first conductive part 31a is connected to the second conductive part 31b, that is, one pole of the first capacitor C1 is electrically connected to one pole of the second capacitor C2, so that the first capacitor C1 and the second capacitor C2 are arranged in series.
  • the capacitor 3 provided in the above embodiment of the present application uses the first conductive pillar 33 to penetrate the first conductive part 31a of the conductive layer 31, and uses the first ferroelectric layer 35 to surround the first conductive pillar 33 to connect the first conductive pillar 33 to the first conductive pillar 33.
  • the pillar 33 is spaced apart from the first conductive part 31a.
  • the first conductive pillar 33, the first ferroelectric layer 35 and the first conductive part 31a form the first capacitor C1.
  • the first conductive pillar 33 and the first conductive part 31a serve as the first capacitor.
  • the second conductive pillar 34 is used to penetrate the second conductive part 31b of the conductive layer 31, and the second ferroelectric layer 36 is used to surround the second conductive pillar 34 to separate the second conductive pillar 34 from the second conductive part 31b.
  • the second conductive pillar 34, the second ferroelectric layer 36 and the second conductive part 31b form the second capacitor C2
  • the second conductive pillar 34 and the second conductive part 31b serve as the two poles of the second capacitor C2.
  • the first capacitor C1 and the second capacitor C2 form a series circuit.
  • the potential difference between the two ends of the series circuit is V1-V2.
  • the potential difference between the first capacitor C1 and the second capacitor C1 is less than V1-V2.
  • the potential difference between the two ends of the capacitor C2 should be less than V1-V2.
  • the potential difference between the two ends of each capacitor can be reduced, thereby reducing the probability of polarization reversal of the ferroelectric layer in the capacitor, ensuring the capacitance of the capacitor is stable, and improving The anti-interference ability of the capacitor.
  • the series connection of the capacitors is realized by connecting the first conductive part 31a and the second conductive part 31b in the conductive layer 31.
  • the following embodiments of the present application provide a variety of first conductive parts 31a and second conductive parts.
  • the arrangement of the portion 31b is introduced based on the way capacitors are connected in series.
  • a conductive layer 31 includes at least one first conductive part 31a and at least one second conductive part 31b, and the connected first conductive part 31a and the second conductive part 31b are in the same conductive layer, so that the second conductive part 31a and the second conductive part 31b are connected to each other.
  • a conductive part 31a is connected to the second conductive part 31b.
  • a conductive layer 31 includes a first conductive part 31a and a second conductive part 31b.
  • the first conductive part 31a is connected to the second conductive part 31b, and they are in the same conductive layer. .
  • the first conductive part 31 a and the second conductive part 31 b on the same conductive layer are integrally provided.
  • the first conductive portion 31 a and the second conductive portion 31 b are arranged along a first direction, and the first direction is parallel to the bottom surface P of the first stacked layer 30 .
  • the first direction may be the X direction or the Y direction.
  • the first direction in FIG. 10 is the X direction.
  • a plurality of first conductive pillars 33 penetrate the first conductive portion 31 a of a conductive layer 31 , which is equivalent to a plurality of first capacitors C1 arranged in parallel.
  • the plurality of second conductive pillars 34 penetrate the second conductive portion 31b of one conductive layer 31, which is equivalent to a plurality of second capacitors C2 arranged in parallel.
  • the first conductive part 31a and the second conductive part 31b of the same conductive layer 31 are connected, so that the plurality of parallel first capacitors C1 and the plurality of parallel second capacitors C2 are connected in series to form a third capacitor C3.
  • the total capacitance value of multiple first capacitors C1 connected in parallel is greater than the capacitance value of one first capacitor C1
  • the total capacitance value of multiple second capacitors C2 connected in parallel is greater than the capacitance of one second capacitor C2. value
  • the capacitance value of the third capacitor C3 can be increased, thereby increasing the total capacitance value of the capacitor 3.
  • first capacitors C1 connected in parallel and a plurality of second capacitors C2 connected in parallel are connected in series to form a third capacitor C3, which can reduce the potential difference between the two ends of the multiple capacitors connected in parallel (first capacitor C1 or second capacitor C2). , reducing the potential difference across each capacitor, thereby reducing the probability of polarization flipping of the ferroelectric layer in the capacitor, ensuring the capacitance of the capacitor is stable, and improving the anti-interference ability of the capacitor.
  • a plurality of first conductive pillars 33 penetrate through the first conductive portions 31 a of the plurality of conductive layers 31
  • a plurality of second conductive pillars 34 penetrate through the second conductive portions of the plurality of conductive layers 31 .
  • Part 31b corresponds to a plurality of third capacitors C3 arranged in parallel, and can also increase the total capacitance value of the capacitor 3.
  • the capacitor 3 further includes a first interconnection electrode 37 and a second interconnection electrode 38, Both the first interconnection electrode 37 and the second interconnection electrode 38 have a comb-shaped structure, and the first interconnection electrode 37 and the second interconnection electrode 38 are arranged along the first direction.
  • the first interconnection electrode 37 includes a plurality of first interconnection lines 371 and a first connection portion 372. The same end of the plurality of first interconnection lines 371 is connected to the first connection portion 372 to form a comb-shaped structure.
  • the interconnection lines 371 are the "comb teeth" of the comb-like structure, and the first connecting portion 372 is the "comb back" of the comb-like structure.
  • the second interconnection electrode 38 includes a plurality of second interconnection lines 381 and a second connection portion 382.
  • the same end of the plurality of second interconnection lines 381 is connected to the second connection portion 382 to form a comb-shaped structure.
  • the line 381 is the "comb tooth" of the comb-like structure
  • the second connecting part 382 is the "comb back" of the comb-like structure.
  • both the first interconnection line 371 and the second interconnection line 381 extend along a second direction, which is parallel to the bottom surface P of the first stacked layer 30 and intersects with the first direction, for example, The second direction is perpendicular to the first direction. It can be understood that the extending direction of the first interconnection line 371 and the second interconnection line 381 is different from the arrangement direction of the first interconnection electrode 37 and the second interconnection electrode 38 .
  • the first direction is one of the X direction or the Y direction
  • the second direction is the other.
  • the first direction is the X direction
  • the second direction is the Y direction.
  • the plurality of first interconnection lines 371 are electrically connected to the ends of the plurality of first conductive pillars 33 , and the plurality of first interconnection lines 371 are connected on one side of the first stack layer 30 along the second direction, that is, the first interconnection electrode.
  • the first connection portion 372 of 37 is located on one side of the first stacked layer 30 along the second direction, and transmits electrical signals to the plurality of first conductive pillars 33 through the plurality of first interconnection lines 371 of the first interconnection electrode 37 .
  • the plurality of second interconnection lines 381 are electrically connected to the ends of the plurality of second conductive pillars 34 , and the plurality of second interconnection lines 381 are connected on one side of the first stack layer 30 along the second direction, that is, the second interconnection electrode.
  • the second connection portion 382 of 38 is located on one side of the first stacked layer 30 along the second direction, and transmits electrical signals to the plurality of second conductive pillars 34 through the plurality of second interconnection lines 381 of the second interconnection electrode 38 .
  • first connecting portion 372 and the second connecting portion 382 may be located on the same side of the first stacked layer 30 along the second direction, or may be located on opposite sides of the first stacked layer 30 along the second direction.
  • Figure 15 is a top view of another capacitor in accordance with some embodiments.
  • the first interconnection electrode 37 and the second interconnection electrode 38 are also in a comb-shaped structure, and the first interconnection electrode 37 and the second interconnection electrode 38 are arranged along the first direction.
  • the first direction is the Y direction
  • the second direction is the X direction
  • the first interconnection line 371 of the first interconnection electrode 37 and the second interconnection line 381 of the second interconnection electrode 38 both extend along the first direction, that is, the extension direction of the first interconnection line 371 and the second interconnection line 381, and the first interconnection line 371 and the second interconnection line 381 extend along the first direction.
  • the electrodes 37 and the second interconnection electrodes 38 are arranged in the same direction.
  • the plurality of first interconnection lines 371 are electrically connected to the ends of the plurality of first conductive pillars 33 , and the plurality of first interconnection lines 371 are connected on one side of the first stack layer 30 along the first direction, that is, the first interconnection electrode.
  • the first connection portion 372 of 37 is located on one side of the first stacked layer 30 along the first direction, and transmits electrical signals to the plurality of first conductive pillars 33 through the plurality of first interconnection lines 371 of the first interconnection electrode 37 .
  • the plurality of second interconnection lines 381 are electrically connected to the ends of the plurality of second conductive pillars 34 , and the plurality of second interconnection lines 381 are connected on the other side of the first stack layer 30 along the first direction, that is, the second interconnection
  • the second connection portion 382 of the electrode 38 is located on the other side of the first stacked layer 30 along the first direction, and transmits electrical signals to the plurality of second conductive pillars 34 through the plurality of second interconnection lines 381 of the second interconnection electrode 38 .
  • first connecting portion 372 and the second connecting portion 382 are respectively located on opposite sides of the first stacked layer 30 along the first direction.
  • the plurality of first conductive pillars 33 includes multiple rows.
  • each row of first conductive pillars 33 may extend in the same direction as the first interconnection line 371 .
  • a first interconnection line 371 is electrically connected to a row of first conductive pillars 33 to transmit electrical signals to a row of first conductive pillars 33 through the first interconnection line 371 .
  • the plurality of second conductive pillars 34 includes multiple rows.
  • each row of second conductive pillars 34 may extend in the same direction as the second interconnection line 381 .
  • a second interconnection line 381 is electrically connected to a row of second conductive pillars 34 to transmit electrical signals to a row of second conductive pillars 34 through the second interconnection line 381 .
  • the plurality of first conductive pillars 33 include multiple rows, and a first interconnection line 371 is electrically connected to a row of first conductive pillars 33 .
  • the plurality of second conductive pillars 34 include multiple rows, and one second interconnection line 381 is electrically connected to one row of second conductive pillars 34 .
  • Figures 16 and 17 are top views of another capacitor according to some embodiments.
  • both the first interconnection electrode 37 and the second interconnection electrode 38 are planar structures, and the first interconnection electrode 37 and the second interconnection electrode 38 are arranged along the first direction.
  • the first direction is the X direction
  • the second direction is the Y direction
  • the first direction is the Y direction
  • the second direction is the X direction
  • the planar first interconnection electrode 37 is electrically connected to the ends of the plurality of first conductive pillars 33 to transmit electrical signals to the plurality of first conductive pillars 33 through the first interconnection electrode 37 .
  • the planar second interconnection electrode 38 is electrically connected to the ends of the plurality of second conductive pillars 34 to transmit electrical signals to the plurality of second conductive pillars 34 through the second interconnection electrode 38 .
  • a plurality of first conductive pillars 33 are arranged in an array, or a plurality of second conductive pillars 34 are arranged in an array, or a plurality of first conductive pillars 34 are arranged in an array.
  • 33 and the plurality of second conductive pillars 34 are arranged in an array, which can improve the uniformity of the arrangement of the plurality of first conductive pillars 33 and the plurality of second conductive pillars 34, which is beneficial to improving the signal interference between multiple capacitors. Phenomenon.
  • Figure 18 is a top view of another capacitor according to some embodiments;
  • Figure 19 is an equivalent circuit diagram of the capacitor in Figure 18;
  • Figure 20 is a top view of another capacitor according to some embodiments;
  • Figure 21 is a top view of the capacitor in Figure 20 Equivalent circuit diagram of a capacitor.
  • one conductive layer 31 may include a plurality of first conductive parts 31 a and a plurality of second conductive parts 31 b.
  • the plurality of first conductive parts 31 a and the plurality of second conductive parts 31 b are connected and are on the same conductive layer.
  • a plurality of first conductive portions 31a and a plurality of second conductive portions 31b on the same conductive layer are integrally provided.
  • the first conductive parts 31a and the second conductive parts 31b are alternately arranged along the first direction.
  • the first direction in FIG. 18 and FIG. 20 is both the X direction.
  • a plurality of first conductive pillars 33 penetrate a plurality of first conductive portions 31a, which is equivalent to a plurality of first capacitors C1 arranged in parallel.
  • the plurality of second conductive pillars 34 penetrate the plurality of second conductive portions 31b, equivalent to a plurality of second capacitors C2 arranged in parallel.
  • the plurality of first conductive portions 31a and the plurality of second conductive portions 31b of the same conductive layer 31 are connected in series, so that the plurality of parallel-connected first capacitors C1 and the plurality of parallel-connected second capacitors C2 are connected in series to form a third capacitor C3.
  • the capacitors are connected in series to reduce the potential difference between the two ends of each capacitor, thereby reducing the probability of polarization flipping of the ferroelectric layer in the capacitor, ensuring the capacitance of the capacitor is stable, and improving the anti-interference ability of the capacitor.
  • a plurality of first conductive pillars 33 penetrate through the first conductive portions 31 a of the plurality of conductive layers 31
  • a plurality of second conductive pillars 34 penetrate through the plurality of conductive layers 31
  • the second conductive portion 31 b of the conductive layer 31 corresponds to a plurality of third capacitors C3 arranged in parallel, and can also increase the total capacitance value of the capacitor 3 .
  • the capacitor 3 further includes a first interconnection electrode 37 and a second interconnection electrode 38 , both of which are comb-shaped structures.
  • the first interconnection electrode 37 includes a plurality of first interconnection lines 371 and a first connection portion 372. The same end of the plurality of first interconnection lines 371 is connected to the first connection portion 372 to form a comb-shaped structure.
  • the interconnection lines 371 are the "comb teeth" of the comb-like structure, and the first connecting portion 372 is the "comb back" of the comb-like structure.
  • the second interconnection electrode 38 includes a plurality of second interconnection lines 381 and a second connection portion 382.
  • the same end of the plurality of second interconnection lines 381 is connected to the second connection portion 382 to form a comb-shaped structure.
  • the line 381 is the "comb tooth" of the comb-like structure
  • the second connecting part 382 is the "comb back" of the comb-like structure.
  • a plurality of first interconnection lines 371 and a plurality of second interconnection lines 381 are arranged along the first direction, and both the first interconnection lines 371 and the second interconnection lines 381 extend along the second direction.
  • the first direction is the X direction
  • the second direction is the Y direction
  • the plurality of first interconnection lines 371 and the plurality of second interconnection lines 381 are alternately arranged along the first direction.
  • the first direction is the X direction
  • the second direction is the Y direction
  • no second interconnection line 381 is provided between two adjacent first interconnection lines 371, or multiple second interconnection lines 381 are provided.
  • No first interconnection line 371 is provided between two adjacent second interconnection lines 381, or multiple first interconnection lines 371 are provided.
  • the plurality of first interconnection lines 371 are electrically connected to the ends of the plurality of first conductive pillars 33 , and the plurality of first interconnection lines 371 are connected on one side of the first stack layer 30 along the second direction, that is, the first interconnection electrode.
  • the first connection portion 372 of 37 is located on one side of the first stacked layer 30 along the second direction, and transmits electrical signals to the plurality of first conductive pillars 33 through the plurality of first interconnection lines 371 of the first interconnection electrode 37 .
  • the plurality of second interconnection lines 381 are electrically connected to the ends of the plurality of second conductive pillars 34 , and the plurality of second interconnection lines 381 are in the first stack.
  • the other side of the layer 30 is connected along the second direction, that is, the second connection portion 382 of the second interconnection electrode 38 is located on the other side of the first stacked layer 30 along the second direction, through a plurality of strips of the second interconnection electrode 38
  • the second interconnection line 381 transmits electrical signals to the plurality of second conductive pillars 34 .
  • the plurality of first conductive pillars 33 includes multiple rows.
  • each row of the first conductive pillars 33 may extend in the same direction as the first interconnection line 371 .
  • a first interconnection line 371 is electrically connected to a row of first conductive pillars 33 to transmit electrical signals to a row of first conductive pillars 33 through the first interconnection line 371 .
  • the plurality of second conductive pillars 34 includes multiple rows.
  • each row of second conductive pillars 34 may extend in the same direction as the second interconnection line 381 .
  • a second interconnection line 381 is electrically connected to a row of second conductive pillars 34 to transmit electrical signals to a row of second conductive pillars 34 through the second interconnection line 381 .
  • the plurality of first conductive pillars 33 include multiple rows, and a first interconnection line 371 is electrically connected to a row of first conductive pillars 33 .
  • the plurality of second conductive pillars 34 include multiple rows, and one second interconnection line 381 is electrically connected to one row of second conductive pillars 34 .
  • the number of capacitors connected in series can also be increased by dividing the conductive layer 31 into multiple pieces, thereby further reducing the potential difference across each capacitor and reducing the probability of polarization reversal of the ferroelectric layer in the capacitor. Ensure the capacitance of the capacitor is stable and improve the anti-interference ability of the capacitor.
  • FIGS. 22A to 22E are diagrams of steps for preparing a capacitor according to some embodiments.
  • the preparation method includes the following steps:
  • a first stacked layer 30 is formed.
  • the first stacked layer 30 includes a plurality of conductive layers 31 and a plurality of first dielectric layers 32 alternately stacked.
  • One conductive layer 31 includes a first conductive portion 31 a and a second conductive portion 31 b connected to each other.
  • the second stacked layer D is simultaneously formed in the array area A1.
  • the first stacked layer 30 is etched to form a first contact hole H1 penetrating the first conductive part 31 a and a second contact hole H2 penetrating the second conductive part 31 b.
  • the first contact hole H1 penetrates the first conductive portions 31 a of the plurality of conductive layers 31
  • the second contact hole H2 penetrates the second conductive portions 31 b of the plurality of conductive layers 31 .
  • a first ferroelectric layer 35 is formed on the side wall of the first contact hole H1
  • a second ferroelectric layer 36 is formed on the side wall of the second contact hole H2.
  • the first conductive pillar 33 is formed inside the first ferroelectric layer 35
  • the second conductive pillar 34 is formed inside the second ferroelectric layer 36 .
  • a first stacked layer 30 is first formed.
  • the first stacked layer 30 includes a plurality of conductive layers 31 and a plurality of first dielectric layers 32 that are alternately stacked.
  • One conductive layer 31 includes The first conductive part 31a and the second conductive part 31b.
  • the first contact hole H1 penetrating the first conductive part 31a and the second contact hole H2 penetrating the second conductive part 31b are formed, and the first ferroelectric layer 35 and the first ferroelectric layer 35 are formed on the side walls of the first contact hole H1.
  • the conductive pillar 33 forms a second ferroelectric layer 36 and a second conductive pillar 34 on the side wall of the second contact hole H2.
  • the first conductive pillar 33, the first ferroelectric layer 35 and the first conductive portion 31a form the first capacitor C1
  • the first conductive pillar 33 and the first conductive portion 31a serve as two poles of the first capacitor C1
  • the second conductive pillar 34, the second ferroelectric layer 36 and the second conductive part 31b form the second capacitor C2
  • the second conductive pillar 34 and the second conductive part 31b serve as two poles of the second capacitor C2.
  • one pole of the first capacitor C1 is electrically connected to one pole of the second capacitor C2, so that the first capacitor C1 and the second capacitor C2 are arranged in series, which can reduce the The potential difference between the two ends of each capacitor can reduce the probability of polarization flipping of the ferroelectric layer in the capacitor, ensure the stability of the capacitance value, and improve the anti-interference ability of the capacitor.
  • the above preparation method further includes the following steps:
  • a first interconnection electrode 37 and a second interconnection electrode 38 are formed.
  • the first interconnection electrode 37 and the second interconnection electrode 38 are both formed on the top of the first stacked layer 30 .
  • the first interconnection electrode 37 is electrically connected to the ends of the plurality of first conductive pillars 33 to transmit electrical signals to the plurality of first conductive pillars 33 .
  • the second interconnection electrode 38 is electrically connected to the ends of the plurality of second conductive pillars 34 to transmit electrical signals to the plurality of second conductive pillars 34 .
  • Figure 23 is a top view of another capacitor according to some embodiments;
  • Figure 24 is a cross-sectional view of the capacitor in Figure 23 along the section line B-B';
  • Figure 25 is an equivalent circuit diagram of the capacitor in Figure 24.
  • a conductive layer 31 includes a plurality of conductive blocks 310 arranged separately. This is equivalent to a conductive layer 31 being divided into a plurality of conductive blocks 310 , and the plurality of conductive blocks 310 are disconnected. Furthermore, a conductive block 310 includes a connected first A conductive part 31a and a second conductive part 31b.
  • the capacitor 3 further includes a second dielectric layer 40 that penetrates the first stack layer 30 and separates two adjacent conductive blocks 310 . It can be understood that the second dielectric layer 40 divides the conductive layer 31 into a plurality of conductive blocks 310 .
  • a plurality of first conductive pillars 33 penetrate the first conductive portion 31 a of a conductive block 310 , which is equivalent to a plurality of first capacitors C1 arranged in parallel.
  • the plurality of second conductive pillars 34 penetrate the second conductive portion 31b of one conductive block 310, which is equivalent to a plurality of second capacitors C2 arranged in parallel.
  • the first conductive part 31a and the second conductive part 31b of the same conductive block 310 are connected, so that a plurality of parallel first capacitors C1 and a plurality of parallel second capacitors C2 are connected in series to form a third capacitor C3.
  • the plurality of second conductive pillars 34 penetrating one conductive block 310 are electrically connected to the plurality of first conductive pillars 33 penetrating the other conductive block 310 , so that the adjacent conductive blocks 310
  • the third capacitor C3 is connected in series to form a fourth capacitor C4.
  • the total capacitance value of multiple first capacitors C1 connected in parallel is greater than the capacitance value of one first capacitor C1
  • the total capacitance value of multiple second capacitors C2 connected in parallel is greater than the capacitance of one second capacitor C2.
  • the capacitance value of the third capacitor C3 can be increased
  • the capacitance value of the fourth capacitor C4 can be increased, thereby increasing the total capacitance value of the capacitor 3.
  • a plurality of parallel-connected first capacitors C1 and a plurality of parallel-connected second capacitors C2 are connected in series to form a third capacitor C3.
  • the third capacitors C3 of adjacent conductive blocks 310 are connected in series to form a fourth capacitor C4, so as to increase the number of series-connected capacitors.
  • the number of capacitors can further reduce the potential difference between the two ends of each capacitor, reduce the probability of polarization flipping of the ferroelectric layer in the capacitor, ensure the stability of the capacitance value of the capacitor, and improve the anti-interference ability of the capacitor.
  • a conductive layer 31 includes a first conductive block to an nth conductive block arranged in sequence, n ⁇ 2, and n is a positive integer.
  • the capacitor 3 also includes a first interconnection electrode 37, at least a second interconnection electrode 38 and a third interconnection electrode 39.
  • Post 33 is electrically connected.
  • the third interconnection electrode 39 is electrically connected to the second conductive pillar 34 penetrating the nth conductive block.
  • the capacitor 3 includes a second interconnection Electrode 38.
  • the first interconnection electrode 37 is electrically connected to the first conductive pillar 33 penetrating the first conductive block 310a
  • the second interconnection electrode 38 is electrically connected to the second conductive pillar 34 penetrating the first conductive block 310a
  • the first conductive pillar 33 of the conductive block 310b is electrically connected
  • the third interconnection electrode 39 is electrically connected to the second conductive pillar 34 penetrating the second conductive block 310b.
  • the first interconnection electrode 37 and the third interconnection electrode 39 receive external electrical signals and transmit the electrical signals to the fourth capacitor C4.
  • the second interconnection electrode 38 serves as a connection electrode and does not receive external electrical signals.
  • FIGS. 26A to 26G are diagrams of steps for preparing another capacitor according to some embodiments.
  • the preparation method includes the following steps:
  • the first stacked layer 30 includes a plurality of conductive layers 31 and a plurality of first dielectric layers 32 that are alternately stacked.
  • the second stacked layer D is simultaneously formed in the array area A1.
  • the first stacked layer 30 is etched to form a first contact hole H1 penetrating the first stacked layer 30 and a second contact hole H2 penetrating the first stacked layer 30 .
  • the first contact hole H1 penetrates the plurality of conductive layers 31 of the first stack layer 30
  • the second contact hole H2 penetrates the plurality of conductive layers 31 of the first stack layer 30 .
  • a first ferroelectric layer 35 is formed on the side wall of the first contact hole H1
  • a second ferroelectric layer 36 is formed on the side wall of the second contact hole H2.
  • the first conductive pillar 33 is formed inside the first ferroelectric layer 35
  • the second conductive pillar 34 is formed inside the second ferroelectric layer 36 .
  • the preparation method further includes the following steps:
  • At least one isolation trench G is formed through the first stacked layer 30, and the at least one isolation trench G connects the conductive layer to 31 is divided into a plurality of conductive blocks 310.
  • One conductive block 310 includes a first conductive part 31a and a second conductive part 31b. The first conductive part 31a is connected to the second conductive part 31b.
  • Each conductive layer 31 includes the first to nth conductive blocks arranged in sequence, n ⁇ 2, and n is a positive integer.
  • a second dielectric layer 40 is formed within the isolation trench G.
  • the preparation method further includes the following steps:
  • a first interconnection electrode 37, at least one second interconnection electrode 38 and a third interconnection electrode 39 are formed.
  • the first interconnection electrode 37 is electrically connected to the first conductive pillar 33 penetrating the first conductive block.
  • the third interconnection electrode 39 is electrically connected to the second conductive pillar 34 penetrating the nth conductive block.
  • a second interconnection electrode 38 is formed.
  • the first interconnection electrode 37 is electrically connected to the first conductive pillar 33 penetrating the first conductive block 310a
  • the second interconnection electrode 38 is electrically connected to the second conductive pillar 34 penetrating the first conductive block 310a
  • the first conductive pillar 33 of the conductive block 310b is electrically connected
  • the third interconnection electrode 39 is electrically connected to the second conductive pillar 34 penetrating the second conductive block 310b.
  • a first stacked layer 30 is first formed.
  • the first stacked layer 30 includes a plurality of conductive layers 31 and a plurality of first dielectric layers 32 that are alternately stacked. Then, the first contact hole H1 penetrating the first conductive part 31a and the second contact hole H2 penetrating the second conductive part 31b are formed, and the first ferroelectric layer 35 and the first ferroelectric layer 35 are formed on the side walls of the first contact hole H1.
  • the conductive pillar 33 forms a second ferroelectric layer 36 and a second conductive pillar 34 on the side wall of the second contact hole H2.
  • an isolation trench G is formed through the first stacked layer 30, and a second dielectric layer 40 is formed in the isolation trench G to divide the conductive layer 31 into a plurality of conductive blocks 310.
  • Increasing the number of capacitors in series can further reduce the potential difference between the two ends of each capacitor, reduce the probability of polarization flipping of the ferroelectric layer in the capacitor, ensure the stability of the capacitance of the capacitor, and improve the anti-interference ability of the capacitor.
  • Figure 27 is a cross-sectional view of yet another capacitor according to some embodiments;
  • Figure 28 is an equivalent circuit diagram of the capacitor in Figure 27.
  • the plurality of conductive layers 31 includes a plurality of first conductive parts 31 a and a plurality of second conductive parts 31 b , and the plurality of second conductive parts 31 b are located away from the plurality of first conductive parts 31 a.
  • One side of the bottom P of the stacked layer 30 is one side of the bottom P of the stacked layer 30 .
  • first conductive portions 31a and a plurality of first dielectric layers 32 are alternately stacked, and a plurality of second conductive portions 31b and a plurality of first dielectric layers 32 are alternately stacked.
  • a plurality of first conductive pillars 33 penetrate a plurality of first conductive portions 31a, which is equivalent to a plurality of first capacitors C1 arranged in parallel.
  • the plurality of second conductive pillars 34 penetrate the plurality of second conductive portions 31b, equivalent to a plurality of second capacitors C2 arranged in parallel.
  • the capacitor 3 also includes a third conductive pillar 41 penetrating the first stacked layer 30.
  • the third conductive pillar 41 is electrically connected to the plurality of first conductive parts 31a and the plurality of second conductive parts 31b, so that the plurality of parallel conductive parts 31a and 31b are connected in parallel.
  • a first capacitor C1 is connected in series with a plurality of parallel second capacitors C2.
  • the total capacitance value of multiple first capacitors C1 connected in parallel is greater than the capacitance value of one first capacitor C1
  • the total capacitance value of multiple second capacitors C2 connected in parallel is greater than the capacitance of one second capacitor C2. value, which can increase the total capacitance value of capacitor 3.
  • first capacitors C1 connected in parallel and multiple second capacitors C2 connected in parallel can be connected in series, which can reduce the potential difference between the two ends of the multiple capacitors connected in parallel (first capacitor C1 or second capacitor C2) and reduce the voltage of each capacitor.
  • the potential difference between the two ends can reduce the probability of polarization flipping of the ferroelectric layer in the capacitor, ensure the stability of the capacitance value, and improve the anti-interference ability of the capacitor.
  • the capacitor 3 further includes a first interconnection electrode 37 and a second interconnection electrode 38 .
  • the first interconnection electrode 37 is disposed on the bottom surface P of the first stacked layer 30 away from the plurality of first conductive portions 31 a One side, that is, the first interconnection electrode 37 is disposed at the bottom of the first stack layer 30 , and the first interconnection electrode 37 is electrically connected to the ends of the plurality of first conductive pillars 33 , and the first interconnection electrode 37 is connected to the plurality of first conductive pillars 33 through the first interconnection electrode 37 .
  • a conductive post 33 transmits electrical signals.
  • the second interconnection electrode 38 is disposed on a side of the plurality of second conductive portions 31b away from the bottom surface P of the first stacked layer 30 , that is, the second interconnection electrode 38 is disposed on the top of the first stacked layer 30 , and the second interconnection electrode 38 It is electrically connected to the ends of the plurality of second conductive pillars 34 and transmits electrical signals to the plurality of second conductive pillars 34 through the second interconnection electrodes 38 .
  • FIGS. 29A to 29K are diagrams of steps for preparing another capacitor according to some embodiments.
  • the preparation method includes the following steps:
  • the first sub-stacked layer 30a includes a plurality of first conductive portions 31a and a plurality of first dielectric layers 32 that are alternately stacked.
  • the first interconnection electrode 37 is formed and is located at the bottom of the first sub-stacked layer 30a.
  • first contact holes H1 are formed penetrating the plurality of first conductive portions 31a.
  • a first ferroelectric layer 35 is formed on the sidewall of the first contact hole H1.
  • the first conductive pillar 33 is formed inside the first ferroelectric layer 35 .
  • an insulating layer 42 is formed covering the first sub-stacked layer 30a, the first ferroelectric layer 35 and the first conductive pillar 33.
  • a second sub-stacked layer 30b is formed on the side of the insulating layer 42 away from the first sub-stacked layer 30a.
  • the second sub-stacked layer 30b includes a plurality of second conductive portions 31b and a plurality of first media arranged in an alternating stack.
  • Layer 32 is
  • second contact holes H2 are formed penetrating the plurality of second conductive portions 31b.
  • a second ferroelectric layer 36 is formed on the sidewall of the second contact hole H2.
  • a second conductive pillar 34 is formed inside the second ferroelectric layer 36 .
  • a third conductive pillar 41 is formed.
  • the third conductive pillar 41 penetrates the second sub-stacked layer 30b, the insulating layer 42 and the first sub-stacked layer 30a, and the third conductive pillar 41 is connected with the plurality of first conductive parts 31a and The plurality of second conductive parts 31b are electrically connected.
  • a second interconnect electrode 38 is formed on top of the second sub-stacked layer 30b.
  • the preparation method provided by the above embodiments of the present application first forms a first sub-stacked layer 30a.
  • the first sub-stacked layer 30a includes a plurality of first conductive portions 31a and a plurality of first dielectric layers 32 that are alternately stacked. Then, a first contact hole H1 penetrating the plurality of first conductive portions 31 a is formed, and a first ferroelectric layer 35 and a first conductive pillar 33 are formed on the side walls of the first contact hole H1 .
  • a second sub-stacked layer 30b is formed above the first sub-stacked layer 30a.
  • the second sub-stacked layer 30b includes a plurality of second conductive portions 31b and a plurality of first dielectric layers 32 that are alternately stacked.
  • a second contact hole H2 penetrating the plurality of second conductive portions 31b is formed, and a second ferroelectric layer 36 and a second conductive pillar 34 are formed on the side walls of the second contact hole H2.
  • a third conductive pillar 41 is formed that penetrates the second sub-stacked layer 30b and the first sub-stacked layer 30a.
  • the third conductive pillar 41 is electrically connected to the plurality of first conductive parts 31a and the plurality of second conductive parts 31b, so that the parallel connection
  • a plurality of first capacitors C1 and a plurality of parallel second capacitors C2 are connected in series, which can reduce the potential difference between the two ends of each capacitor, thereby reducing the probability of polarization flipping of the ferroelectric layer in the capacitor, ensuring the capacitance of the capacitor is stable, and improving The anti-interference ability of the capacitor.
  • the materials of the conductive layer 31, the first conductive pillar 33 and the second conductive pillar 34 include at least one of Ti, Au, W, Mo, Al, Cu, Ru, Ag, TiN, and ITO.
  • the materials of the conductive layer 31 , the first conductive pillar 33 and the second conductive pillar 34 may include one or more of these materials.
  • the material of the first ferroelectric layer 35 includes at least one of ZrO 2 , HfO 2 , HfAlO, HfSiO, HfZrO, HfLaO, and HfYO. That is, the material of the first ferroelectric layer 35 may include one or more of these materials. .
  • the material of the second ferroelectric layer 36 includes at least one of ZrO 2 , HfO 2 , HfAlO, HfSiO, HfZrO, HfLaO, and HfYO. That is, the material of the second ferroelectric layer 36 may include one or more of these materials. .
  • the first dielectric layer 32 has a single-layer structure or a stacked layer structure.
  • the material of the first dielectric layer 32 includes SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 O 3 , and Si 3 N 4 . At least one, that is, the material of the first dielectric layer 32 may include one or more of these materials.
  • the ferroelectric memories, three-dimensional integrated circuits and electronic devices provided by some embodiments of the present application include the capacitors provided by any of the above embodiments.
  • the beneficial effects they can achieve can be referred to the beneficial effects of the capacitors mentioned above, which are not discussed here. Again.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本申请提供了一种铁电存储器、三维集成电路、电子设备，涉及半导体芯片技术领域，提高了电容器的抗干扰能力。铁电存储器包括电容器，电容器包括第一堆叠层、第一导电柱、第二导电柱、第一铁电层和第二铁电层，第一堆叠层包括相连的第一导电部和第二导电部。第一导电柱贯穿第一导电部，第二导电柱贯穿第二导电部。第一铁电层贯穿第一导电部，且围绕第一导电柱设置，第二铁电层贯穿第二导电部，且围绕第二导电柱设置。该电容器包括串联设置的第一电容器和第二电容器，第一电容器包括第一导电柱、第一铁电层和第一导电部，第二电容器包括第二导电柱、第二铁电层和第二导电部。该铁电存储器可应用于三维集成电路中，以实现对数据的读取和写入。

Description

铁电存储器、三维集成电路、电子设备
本申请要求于2022年09月14日提交国家知识产权局、申请号为202211115561.7、申请名称为“铁电存储器、三维集成电路、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体芯片技术领域，尤其涉及一种铁电存储器、三维集成电路、电子设备。
背景技术
随着半导体芯片技术的发展，平面集成电路(2D Integrated Circuit，2D IC)用作系统级芯片(System On Chip，SOC)，已经无法满足人们对芯片的功能、尺寸、能耗的需求。
目前，将多个芯片进行三维堆叠(3D Stacking)形成三维集成电路(3D Integrated Circuit，3D IC)，可提高多个芯片之间互连的带宽和能效，因此，三维集成电路逐渐受到领域内的关注。
在三维集成电路中，为保证芯片的电源完整性(Power Integrity，PI)，需要在芯片的电源分布网络(Power Distribution Network，PDN)中设置去耦电容器(Decoupling Capacitor，Decap)，以使电源分布网络能提供较稳定的电源。但是，随着工作时间的增长，去耦电容器的抗干扰能力会变差，导致其电容值发生变化，进而导致电源分布网络无法提供稳定的电源。
发明内容
本申请实施例提供一种铁电存储器、三维集成电路、电子设备，旨在提高芯片中去耦电容器的抗干扰能力。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种铁电存储器，该铁电存储器可以是铁电随机存取存储器(Ferroelectric Random Access Memory，FeRAM)、也可以是铁电场效应晶体管(Ferroelectric Field Effect Transistor，FeFET)存储器，可实现对数据的读取和写入。
上述铁电存储器包括阵列区和走线区，该铁电存储器包括设置于阵列区的存储阵列，及设置于走线区的电容器。电容器包括第一堆叠层、第一导电柱、第二导电柱、第一铁电层和第二铁电层，第一堆叠层包括交替层叠设置的多个导电层和多个第一介质层，多个导电层包括相连的第一导电部和第二导电部。第一导电柱贯穿第一导电部，第二导电柱贯穿第二导电部。第一铁电层和第二铁电层为筒状结构，第一铁电层贯穿第一导电部，且围绕第一导电柱设置，第二铁电层贯穿第二导电部，且围绕第二导电柱设置。该电容器包括串联设置的第一电容器和第二电容器，第一电容器包括第一导电柱、第一铁电层和第一导电部，第二电容器包括第二导电柱、第二铁电层和第二导电部。
本申请的上述实施例所提供的铁电存储器，采用第一导电柱贯穿导电层的第一导电部，并采用第一铁电层围绕第一导电柱设置，以将第一导电柱与第一导电部隔开，第一导电柱、第一铁电层和第一导电部形成第一电容器，第一导电柱和第一导电部作为第一电容器的两极。
并且，采用第二导电柱贯穿导电层的第二导电部，并采用第二铁电层围绕第二导电柱设置，以将第二导电柱与第二导电部隔开，第二导电柱、第二铁电层和第二导电部形成第二电容器，第二导电柱和第二导电部作为第二电容器的两极。
通过连接第一导电部和第二导电部，使第一电容器的一极与第二电容器的一极电连接，从而使第一电容器与第二电容器串联设置。根据串联分压的原理，可减小每个电容器两端的电势差，从而可降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
在一些实施例中，每个导电层包括至少一个第一导电部和至少一个第二导电部，相连的第一导电部与第二导电部处于同一导电层，以便于第一导电部与第二导电部连接。
在一些实施例中，每个导电层包括一个第一导电部和一个第二导电部，第一导电部与第二导 电部相连，第一导电部与第二导电部沿第一方向排列，第一方向平行于第一堆叠层的底面。多个第一导电柱贯穿第一导电部，相当于多个第一电容器并联设置。多个第二导电柱贯穿第二导电部，相当于多个第二电容器并联设置。同一导电层的第一导电部与第二导电部相连，使并联的多个第一电容器与并联的多个第二电容器串联，形成第三电容器。
上述实施例中，多个第一电容器并联的总电容值要大于一个第一电容器的电容值，多个第二电容器并联的总电容值要大于一个第二电容器的电容值，可增加第三电容器的电容值，从而增加电容器的总电容值。
并且，并联的多个第一电容器与并联的多个第二电容器串联，形成第三电容器，可减小并联的多个电容器(第一电容器或第二电容器)的两端的电势差，减小每个电容器两端的电势差，从而可降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
在一些实施例中，电容器还包括第一互联电极和第二互联电极，第一互联电极和第二互联电极为面状结构，第一互联电极与第二互联电极沿第一方向排列。第一互联电极与多个第一导电柱的端部电连接，以通过第一互联电极向多个第一导电柱传输电信号。第二互联电极与多个第二导电柱的端部电连接，以通过第二互联电极向多个第二导电柱传输电信号。
在一些实施例中，多个第一导电柱呈阵列式排布，和/或，多个第二导电柱呈阵列式排布，可提高多个第一导电柱和多个第二导电柱排布的均匀性，有利于改善多个电容器之间信号干扰的现象。
在一些实施例中，电容器还包括第一互联电极和第二互联电极，第一互联电极和第二互联电极为梳状结构，第一互联电极与第二互联电极沿第一方向排列，第一互联电极包括多条第一互联线，第二互联电极包括多条第二互联线。
第一互联线和第二互联线沿第一方向延伸，多条第一互联线与多个第一导电柱的端部电连接，且多条第一互联线在第一堆叠层的沿第一方向的一侧连接。多条第二互联线与多个第二导电柱的端部电连接，且多条第二互联线在第一堆叠层的沿第一方向的另一侧连接。
或者，第一互联线和第二互联线沿第二方向延伸，多条第一互联线与多个第一导电柱的端部电连接，且多条第一互联线在第一堆叠层的沿第二方向的一侧连接。多条第二互联线与多个第二导电柱的端部电连接，且多条第二互联线在第一堆叠层的沿第二方向的一侧连接，第二方向平行于第一堆叠层的底面，且与第一方向相交叉。
在一些实施例中，每个导电层包括多个第一导电部和多个第二导电部，多个第一导电部与多个第二导电部相连，第一导电部与第二导电部沿第一方向交替排列，第一方向平行于第一堆叠层的底面。多个第一导电柱贯穿第一导电部，多个第二导电柱贯穿第二导电部。
上述实施例中，多个第一导电柱贯穿第一导电部，相当于多个第一电容器并联设置。多个第二导电柱贯穿第二导电部，相当于多个第二电容器并联设置。同一导电层的多个第一导电部与多个第二导电部相连，使并联的多个第一电容器与并联的多个第二电容器串联，形成第三电容器。通过电容器串联的方式，可减小每个电容器两端的电势差，从而可降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
在一些实施例中，电容器还包括第一互联电极和第二互联电极，第一互联电极和第二互联电极为梳状结构。第一互联电极包括多条第一互联线，第二互联电极包括多条第二互联线，多条第一互联线与多条第二互联线沿第一方向排列，第一互联线和第二互联线沿第二方向延伸。
多条第一互联线与多个第一导电柱的端部电连接，且多条第一互联线在第一堆叠层的沿第二方向的一侧连接，通过第一互联电极的多条第一互联线向多个第一导电柱传输电信号。多条第二互联线与多个第二导电柱的端部电连接，且多条第二互联线在第一堆叠层的沿第二方向的另一侧连接，通过第二互联电极的多条第二互联线向多个第二导电柱传输电信号。
在一些实施例中，多条第一互联线与多条第二互联线沿第一方向交替排列。或者，相邻两条第一互联线之间不设置第二互联线，或设置有多条第二互联线，相邻两条第二互联线之间不设置第一互联线，或设置有多条第一互联线。
在一些实施例中，多个第一导电柱包括多排，一条第一互联线与一排第一导电柱电连接，以 通过第一互联线向一排第一导电柱传输电信号。和/或，多个第二导电柱包括多排，一条第二互联线与一排第二导电柱电连接，以通过第二互联线向一排第二导电柱传输电信号。
在一些实施例中，处于同一导电层的第一导电部和第二导电部一体设置，以实现第一导电部和第二导电部的连接。
在一些实施例中，每个导电层包括多个分隔设置的导电块，一个导电块包括相连的一个第一导电部和一个第二导电部，多个第一导电柱贯穿导电块的第一导电部，相当于多个第一电容器并联设置。多个第二导电柱贯穿导电块的第二导电部，相当于多个第二电容器并联设置。同一导电块的第一导电部与第二导电部相连，使并联的多个第一电容器与并联的多个第二电容器串联，形成第三电容器。
相邻两个导电块中，贯穿一个导电块的多个第二导电柱，与贯穿另一个导电块的多个第一导电柱电连接，使相邻的导电块的第三电容器串联，形成第四电容器。
上述实施例中，多个第一电容器并联的总电容值要大于一个第一电容器的电容值，多个第二电容器并联的总电容值要大于一个第二电容器的电容值，可增加第三电容器的电容值，增加第四电容器的电容值，从而增加电容器的总电容值。
并且，并联的多个第一电容器与并联的多个第二电容器串联，形成第三电容器，相邻的导电块的第三电容器串联，形成第四电容器，以增加串联的电容器的数量，从而可进一步减小每个电容器两端的电势差，降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
在一些实施例中，电容器还包括第二介质层，第二介质层贯穿第一堆叠层，且隔开相邻两个导电块，即第二介质层将导电层分割成多个导电块。
在一些实施例中，每个导电层包括依次设置的第1个导电块～第n个导电块，n≥2，且n为正整数。电容器还包括一个第一互联电极、至少一个第二互联电极和一个第三互联电极，第一互联电极与贯穿第1个导电块的第一导电柱电连接。第二互联电极与，贯穿第i个导电块的第二导电柱和贯穿第i+1个导电块的第一导电柱电连接，i＝1～n-1，且i为正整数。第三互联电极与贯穿第n个导电块的第二导电柱电连接。
上述实施例中，第一互联电极和第三互联电极接收外部的电信号，并将该电信号传输至第四电容器。
在一些实施例中，多个导电层包括多个第一导电部和多个第二导电部，多个第二导电部位于多个第一导电部的远离第一堆叠层的底面的一侧。多个第一导电柱贯穿多个第一导电部，相当于多个第一电容器并联设置。多个第二导电柱贯穿多个第二导电部，相当于多个第二电容器并联设置。
电容器还包括贯穿第一堆叠层的第三导电柱，第三导电柱与多个第一导电部和多个第二导电部电连接，使并联的多个第一电容器与并联的多个第二电容器串联。
上述实施例中，多个第一电容器并联的总电容值要大于一个第一电容器的电容值，多个第二电容器并联的总电容值要大于一个第二电容器的电容值，可增加电容器的总电容值。
并且，并联的多个第一电容器与并联的多个第二电容器串联，可减小并联的多个电容器(第一电容器或第二电容器)的两端的电势差，减小每个电容器两端的电势差，从而可降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
在一些实施例中，电容器还包括第一互联电极和第二互联电极，第一互联电极设置于第一堆叠层的底面的远离多个第一导电部的一侧，且与多个第一导电柱的端部电连接，通过第一互联电极向多个第一导电柱传输电信号。第二互联电极设置于多个第二导电部的远离第一堆叠层的底面的一侧，且与多个第二导电柱的端部电连接，通过第二互联电极向多个第二导电柱传输电信号。
在一些实施例中，导电层、第一导电柱和第二导电柱的材料包括Ti、Au、W、Mo、Al、Cu、Ru、Ag、TiN、ITO中的至少一种。
在一些实施例中，第一铁电层和/或第二铁电层的材料包括ZrO2、HfO2、HfAlO、HfSiO、HfZrO、HfLaO、HfYO中的至少一种。
在一些实施例中，第一介质层为单层结构或叠层结构，第一介质层的材料包括SiO2、Al2O3、 HfO2、ZrO2、TiO2、Y2O3、Si3N4中的至少一种。
在一些实施例中，存储阵列包括第二堆叠层，第二堆叠层包括阵列式排布的多个存储单元。
第二堆叠层包括交替设置的第三介质层和栅极层，第一堆叠层的多个第一介质层与第二堆叠层的多个第三介质层一一对应，相对应的第一介质层与第三介质层的材料相同且同层设置。第一堆叠层的多个导电层与第二堆叠层的多个栅极层一一对应，相对应的导电层与栅极层的材料相同、同层设置、且相互绝缘。
第二方面，提供了一种铁电存储器的制备方法，该制备方法包括：形成第一堆叠层，第一堆叠层包括交替层叠设置的多个导电层和多个第一介质层，多个导电层包括相连的第一导电部和第二导电部。形成贯穿第一导电部的第一接触孔，及贯穿第二导电部的第二接触孔。在第一接触孔的侧壁上形成第一铁电层，并在第二接触孔的侧壁上形成第二铁电层。在第一铁电层的内侧形成第一导电柱，并在第二铁电层的内侧形成第二导电柱。
本申请的上述实施例所提供的制备方法，先形成第一堆叠层，第一堆叠层包括交替层叠设置的多个导电层和多个第一介质层，一个导电层包括相连的第一导电部和第二导电部。然后，形成贯穿第一导电部的第一接触孔，及贯穿第二导电部的第二接触孔，在第一接触孔的侧壁上形成第一铁电层和第一导电柱，在第二接触孔的侧壁上形成第二铁电层和第二导电柱。
第一导电柱、第一铁电层和第一导电部形成第一电容器，第一导电柱和第一导电部作为第一电容器的两极。第二导电柱、第二铁电层和第二导电部形成第二电容器，第二导电柱和第二导电部作为第二电容器的两极。通过连接第一导电部和第二导电部，使第一电容器的一极与第二电容器的一极电连接，从而使第一电容器与第二电容器串联设置，可减小每个电容器两端的电势差，从而可降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
在一些实施例中，形成第一导电柱和第二导电柱之后，还包括：形成第一互联电极和第二互联电极，第一互联电极与多个第一导电柱的端部电连接，以向多个第一导电柱传输电信号。第二互联电极与多个第二导电柱的端部电连接，以向多个第二导电柱传输电信号。
在一些实施例中，形成第一堆叠层之后，还包括：形成贯穿第一堆叠层的至少一个隔离沟槽，至少一个隔离沟槽将导电层分隔成多个导电块，一个导电块包括一个第一导电部和一个第二导电部，第一导电部与第二导电部相连。在隔离沟槽内形成第二介质层。
上述实施例中，通过刻蚀第一堆叠层，形成贯穿第一堆叠层的隔离沟槽，并在隔离沟槽内形成第二介质层，以将导电层分割成多个导电块，以增加串联的电容器的数量，从而可进一步减小每个电容器两端的电势差，降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
在一些实施例中，每个导电层包括依次设置的第1个导电块～第n个导电块，n≥2，且n为正整数。
形成第一导电柱和第二导电柱之后，还包括：形成一个第一互联电极、至少一个第二互联电极和一个第三互联电极，第一互联电极与贯穿第1个导电块的第一导电柱电连接。第二互联电极与，贯穿第i个导电块的第二导电柱和贯穿第i+1个导电块的第一导电柱电连接，i＝1～n-1，且i为正整数。第三互联电极与贯穿第n个导电块的第二导电柱电连接。
在一些实施例中，铁电存储器包括阵列区和走线区，在走线区形成第一堆叠层的过程中，在阵列区同步形成第二堆叠层。
第三方面，还提供了一种铁电存储器的制备方法，该制备方法包括：形成第一子堆叠层，第一子堆叠层包括交替层叠设置的多个第一导电部和多个第一介质层。形成贯穿多个第一导电部的第一接触孔。在第一接触孔的侧壁上形成第一铁电层。在第一铁电层的内侧形成第一导电柱。形成绝缘层，绝缘层覆盖第一子堆叠层、第一铁电层和第一导电柱。在绝缘层远离第一子堆叠层的一侧形成第二子堆叠层，第二子堆叠层包括交替层叠设置的多个第二导电部和多个第一介质层。形成贯穿多个第二导电部的第二接触孔。在第二接触孔的侧壁上形成第二铁电层。在第二铁电层的内侧形成第二导电柱。形成第三导电柱，第三导电柱贯穿第二子堆叠层、绝缘层和第一子堆叠层，且与多个第一导电部和多个第二导电部电连接。
本申请的上述实施例所提供的制备方法，先形成第一子堆叠层，第一子堆叠层包括交替层叠设置的多个第一导电部和多个第一介质层。然后，形成贯穿多个第一导电部的第一接触孔，在第一接触孔的侧壁上形成第一铁电层和第一导电柱。
而后，在第一子堆叠层的上方形成第二子堆叠层，第二子堆叠层包括交替层叠设置的多个第二导电部和多个第一介质层。然后，形成贯穿多个第二导电部的第二接触孔，在第二接触孔的侧壁上形成第二铁电层和第二导电柱。
最后，形成贯穿第二子堆叠层和第一子堆叠层的第三导电柱，第三导电柱与多个第一导电部和多个第二导电部电连接，使并联的多个第一电容器与并联的多个第二电容器串联，可减小每个电容器两端的电势差，从而可降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
第四方面，提供了一种三维集成电路，该三维集成电路包括上述任一实施例所述的铁电存储器和处理器芯片，处理器芯片与铁电存储器叠置，且与铁电存储器电连接。
第五方面，提供了一种电子设备，该电子设备例如为消费性电子产品、家居式电子产品、车载式电子产品、金融终端产品、通信电子产品。该电子设备包括电路板，及上述任一实施例所述的铁电存储器或三维集成电路，铁电存储器或三维集成电路设置于电路板上，且与电路电连接。
可以理解地，本申请的上述实施例提供的三维集成电路及电子设备，其所能达到的有益效果可参考上文中铁电存储器的有益效果，此处不再赘述。
附图说明
为了更清楚地说明本申请中的技术方案，下面将对本申请一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本申请实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的电子设备的架构图；
图2为根据一些实施例的电子设备的爆炸图；
图3为根据一些实施例的三维集成电路的结构图；
图4为根据一些实施例的铁电存储器的俯视图；
图5为根据一些实施例的铁电存储器的存储阵列的架构图；
图6为相关技术中的去耦电容器的结构图；
图7为铁电电容器中铁电材料的电滞回线图；
图8为铁电电容器在极化翻转前后电容值与其两极的电势差的关系曲线图；
图9为根据一些实施例的电容器的结构图；
图10为图9中的电容器的俯视图；
图11为图10中的电容器沿剖面线A-A＇的剖视图；
图12为图11中的电容器的等效电路图；
图13为图11中的电容器在M处的局部放大图；
图14为图13中的电容器的等效电路图；
图15为根据一些实施例的另一种电容器的俯视图；
图16和图17为根据一些实施例的另一种电容器的俯视图；
图18为根据一些实施例的另一种电容器的俯视图；
图19为图18中的电容器的等效电路图；
图20为根据一些实施例的又一种电容器的俯视图；
图21为图20中的电容器的等效电路图；
图22A～图22E为根据一些实施例的制备一种电容器的各步骤图；
图23为根据一些实施例的又一种电容器的俯视图；
图24为图23中的电容器沿剖面线B-B＇的剖视图；
图25为图24中的电容器的等效电路图；
图26A～图26G为根据一些实施例的制备另一种电容器的各步骤图；
图27为根据一些实施例的又一种电容器的剖视图；
图28为图27中的电容器的等效电路图；
图29A～图29K为根据一些实施例的制备又一种电容器的各步骤图。
具体实施方式
下面将结合附图，对本申请一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。
“A、B、C中的至少一个”包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
在本申请的内容中，“在……上”、“上方”、和“之上”的含义应当以最宽泛的方式解释，使得“在...上”不仅意味着“直接在某物上”，而且还包括其间具有中间特征或层的“在某物上”的含义，并且“上方”或“之上”不仅意味着在某物“上方”或“之上”，还包括其间没有中间特征或层的在某物“上方”或“之上”的含义(即，直接在某物上)。
在本申请的内容中，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本申请的一些实施例提供了一种电子设备，该电子设备例如可以为手机、平板电脑、个人数字助理(Personal Digital Assistant，PDA)、电视、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(Virtual Reality，VR)终端设备、增强现实(Augmented Reality，AR)终端设备、充电 家用小型电器(例如豆浆机、扫地机器人)、无人机、雷达、航空航天设备和车载设备等不同类型的用户设备或者终端设备；该电子设备还可以为基站等网络设备。本申请的实施例对电子设备的具体形式不作特殊限制。
图1为根据一些实施例的电子设备的架构图。
参见图1，电子设备1包括：存储装置11、处理器12、输入设备13、输出设备14等部件。本领域技术人员可以理解到，图1中示出的电子设备1的架构并不构成对该电子设备1的限定，该电子设备1可以包括比如图1所示的部件更多或更少的部件，或者可以组合如图1所示的部件中的某些部件，或者可以与如图1所示的部件布置不同。
其中，存储装置11用于存储软件程序以及模块。存储装置11主要包括存储程序区和存储数据区，其中，存储程序区可存储和备份操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据电子设备1的使用所创建的数据(比如音频数据、图像数据、电话本等)等。此外，存储装置11包括外存储器111和内存储器112。外存储器111和内存储器112存储的数据可以相互传输。外存储器111例如可以包括硬盘、U盘、软盘等。内存储器112例如可以包括随机存取存储器(Random Access Memory，RAM)、只读存储器(Read-Only Memory，ROM)等。
处理器12是该电子设备1的控制中心，利用各种接口和线路连接整个电子设备1的各个部分，通过运行或执行存储在存储装置11内的软件程序和/或模块，以及调用存储在存储装置11内的数据，执行电子设备1的各种功能和处理数据，从而对电子设备1进行整体监控。可选的，处理器12可以包括一个或多个处理单元。例如，处理器12可以包括应用处理器(Application Processor，AP)，调制解调处理器，图形处理器(Graphics Processing Unit，GPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。例如，处理器12可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器12中。上述的应用处理器例如可以为中央处理器(Central Processing Unit，CPU)。图1中以处理器12为CPU为例，CPU可以包括运算器121和控制器122。运算器121获取内存储器112存储的数据，并对内存储器112存储的数据进行处理，处理后的结果通常送回内存储器112。控制器122可以控制运算器121对数据进行处理，控制器122还可以控制外存储器置111和内存储器112读取或写入数据。
输入设备13用于接收输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入。示例的，输入设备13可以包括触摸屏以及其他输入设备。触摸屏，也称为触摸面板，可收集用户在触摸屏上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触摸屏上或在触摸屏附近的操作)，并根据预先设定的程式驱动相应的连接装置。上述处理器12中的控制器122还可以控制输入设备13接收输入的信号或不接收输入的信号。此外，输入设备13接收到的输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入可以存储在内存储器112中。
输出设备14用于输出输入设备13的输入，并存储在内存储器112中的数据对应的信号。例如，输出设备14输出声音信号或视频信号。上述处理器12中的控制器122还可以控制输出设备14输出信号或不输出信号。
需要说明的是，图1中的粗箭头用于表示数据的传输，粗箭头的方向表示数据传输的方向。例如，输入设备13和内存储器112之间的单箭头表示输入设备13接收到的数据向内存储器112传输。又例如，运算器121和内存储器112之间的双箭头表示内存储器112存储的数据可以向运算器121传输，且运算器121处理后的数据可以向内存储器112传输。图1中的细箭头表示控制器122可以控制的部件。示例性地，控制器122可以对外存储器置111、内存储器112、运算器121、输入设备13和输出设备14等进行控制。
为了方便进一步对电子设备1的结构进行说明，以下以电子设备1为手机为例进行示例性介绍。
图2为根据一些实施例的电子设备的爆炸图。
参见图2，电子设备1还可以包括中框15、后壳16以及显示屏17。后壳16和显示屏17分 别位于中框15的相对两侧，且中框15和显示屏17设置于后壳16内。中框15包括用于承载显示屏17的承载板150，以及绕承载板150一周的边框151。
继续参见图2，电子设备1还可以包括电路板18，该电路板18设置于承载板150的靠近后壳16的一侧。电子设备1还包括设置于电路板18上的芯片19，该芯片19与电路板18电连接。
上述芯片19可以为铁电存储器，例如，电子设备1中的内存储器112为铁电存储器，其具有较高的存储密度。该铁电存储器可以是铁电随机存取存储器、也可以是铁电场效应晶体管存储器。
上述芯片19也可以为三维集成电路，三维集成电路包括同构三维集成电路和异构三维集成电路，其中，同构三维集成电路包括沿其厚度方向集成的多层有源器件，具有成本低、尺寸精度高等特点。异构三维集成电路包括集成的多个芯片，这些芯片具有不同的工艺架构、不同的指令集或不同的功能，即异构三维集成电路融合了不同的半导体材料、半导体工艺、半导体结构或半导体器件。
图3为根据一些实施例的三维集成电路的结构图。
参见图3，三维集成电路2包括三维堆叠(3D Stacking)的两个芯片，其中一个芯片例如可以为铁电存储器21，另一个芯片例如可以为处理器芯片22，二者之间电连接。
示例性地，处理器芯片22可由多个逻辑芯片组成，在此情况下，多个逻辑芯片堆叠于铁电存储器21上，并与铁电存储器21电连接。
示例性地，处理器芯片22也可采用系统级芯片(System On Chip，SOC)的结构设计，在此情况下，系统级芯片堆叠于铁电存储器21上，并与铁电存储器21电连接。
上述三维集成电路2即为异构三维集成电路，其具有较大的访存带宽(Memory Bandwidth)，因此，三维集成电路2适用于带宽需求较大的应用场景，例如，人工智能或数据处理等应用场景。
在三维集成电路2中，为保证芯片的电源完整性，需要在芯片的电源分布网络中设置去耦电容器，以使电源分布网络能提供较稳定的电源。去耦电容器可设置于三维集成电路2的处理器芯片22中，也可以设置于铁电存储器21中。
图4为根据一些实施例的铁电存储器的俯视图；图5为根据一些实施例的铁电存储器的存储阵列的架构图。
参见图4和图5，以铁电存储器21为铁电场效应晶体管存储器为例，铁电存储器21包括阵列区A1和走线区A2，该铁电存储器21可包括设置于阵列区A1的存储阵列，存储阵列包括第二堆叠层D，该第二堆叠层D包括阵列式排布的多个存储单元U。沿方向Z，多个存储单元U形成一个存储单元串100，在X-Y平面中，多个存储单元串100可形成存储阵列，源极层SL可以与多个存储单元串100的源极电连接。
示例性地，参见图5，存储单元U可以包括一个晶体管T，沿方向Z，多个晶体管T连接在一起形成了存储单元串100。
示例性地，如图5所示，晶体管T为铁电场效应晶体管，该铁电场效应晶体管的控制极与字线(WL1、WL2……WLm-1、WLm)电连接，源极与源极层SL电连接，漏极与位线(BL1、BL2……BLn-1、BLn)电连接，铁电场效应晶体管的栅介质层的材料为铁电材料。铁电场效应晶体管通过电压脉冲改变铁电层的极性存储数据，并通过读取晶体管的电流来得到存储数据，其读取机制为非破坏性，并具有较高的密度。
需要说明的是，图5中存储单元串100的晶体管T的数目仅是示意性的，本申请实施例提供的铁电存储器21的存储单元串100还可以包括其他数量的晶体管T，例如8、16、32、64。
继续参见图4和图5，铁电存储器21还包括设置于走线区A2的电容器，该电容器包括第一堆叠层30。电容器例如可用作去耦电容器，下面介绍相关技术中的一种去耦电容器。
图6为相关技术中的去耦电容器的结构图。
参见图4，去耦电容器3＇包括第一导电层31＇和第二导电层32＇，以及设置于二者之间的介质层33＇，介质层33＇的材料可以选择铁电材料，铁电材料的介电常数较大，有利于增加去耦电容器3＇的电容值。
在介质层33＇的材料采用铁电材料的情况下，去耦电容器3＇即为铁电电容器。铁电电容器具有矫顽电场，在铁电电容器的两极的电势差增大，且两极所产生的电场大于矫顽电场的情况下， 铁电材料中的铁电畴发生极化翻转，铁电电容器从一个极化状态变为另一个极化状态。
图7为铁电电容器中铁电材料的电滞回线图，其中，横坐标“V”表示：铁电电容器的两极的电势差；纵坐标“P”表示：铁电材料的极化强度。
可见，在铁电电容器的两极的电势差增大，且两极所产生的电场大于矫顽电场的情况下，铁电材料中的铁电畴发生极化翻转，铁电材料的极化强度发生变化，即铁电电容器的极化状态发生变化，例如，铁电电容器从“0”态变为“1”态。
图8为铁电电容器在极化翻转前后电容值与其两极的电势差的关系曲线图，其中，横坐标“V”表示：铁电电容器的两极的电势差；纵坐标“C”表示：铁电电容器的电容值；曲线“1”为：铁电电容器在极化翻转前电容值与其两极的电势差的关系曲线；曲线“2”为：铁电电容器在极化翻转后电容值与其两极的电势差的关系曲线。
可见，在极化翻转前后，铁电电容器的两极的电势差不变的情况下，铁电电容器在极化翻转前的电容值，要大于铁电电容器在极化翻转后的电容值。
综上可知，由于铁电材料的极化翻转特性，在铁电电容器的两极的电势差较大的情况下，铁电材料发生极化翻转，导致铁电电容器的电容值发生变化，铁电电容器的抗干扰能力较差。
为解决上述问题，本申请的一些实施例提供了一种电容器，图9为根据一些实施例的电容器的结构图；图10为图9中的电容器的俯视图；图11为图10中的电容器沿剖面线A-A＇的剖视图；图12为图11中的电容器的等效电路图；图13为图11中的电容器在M处的局部放大图；图14为图13中的电容器的等效电路图。
参见图9，电容器3包括第一堆叠层30，第一堆叠层30包括交替层叠设置的多个导电层31和多个第一介质层32，即相邻两个导电层31被一个第一介质层32隔开。
需要说明的是，图9中导电层31和第一介质层32的数量仅作为示意，本申请的实施例对此不做限定。
前文提到的设置于阵列区A1的第二堆叠层D，该第二堆叠层D包括交替设置的介质层和栅极层，第一堆叠层30的多个第一介质层32与第二堆叠层D的多个介质层一一对应，相对应的第一介质层与第二堆叠层D的介质层的材料相同且同层设置。
并且，第一堆叠层30的多个导电层31与第二堆叠层D的多个栅极层一一对应，相对应的导电层31与栅极层的材料相同且同层设置。
此外，第一堆叠层30的导电层31与第二堆叠层D的栅极层之间绝缘，例如，第一堆叠层30设置于走线区A2，第二堆叠层D设置于阵列区A1，第一堆叠层30与第二堆叠层D设置于不同的区域，二者之间是不连续的，即第一堆叠层30的导电层31与第二堆叠层D的栅极层之间断开。
参见图10和图11，多个导电层31包括相连的第一导电部31a和第二导电部31b。
示例性地，如图9所示，一个导电层31包括一个第一导电部31a和一个第二导电部31b，同一导电层31的第一导电部31a与第二导电部31b处于同一导电层，且二者相连。
参见图11和图13，电容器3还包括第一导电柱33和第二导电柱34，第一导电柱33贯穿第一导电部31a，第二导电柱34贯穿第二导电部31b。
示例性地，如图11所示，每个第一导电柱33贯穿多个导电层31的第一导电部31a，每个第二导电柱34贯穿多个导电层31的第二导电部31b。
继续参见图11和图13，电容器3还包括第一铁电层35和第二铁电层36，第一铁电层35和第二铁电层36均为筒状结构。
其中，第一铁电层35贯穿第一导电部31a，且围绕第一导电柱33设置，第一铁电层35位于第一导电柱33与第一导电部31a之间，以实现第一导电柱33与第一导电部31a的绝缘。第二铁电层36贯穿第二导电部31b，且围绕第二导电柱34设置，第二铁电层36位于第二导电柱34与第二导电部31b之间，以实现第二导电柱34与第二导电部31b的绝缘。
示例性地，如图11所示，每个第一铁电层35贯穿多个导电层31的第一导电部31a，且围绕第一导电柱33设置，以将第一导电柱33与多个导电层31的第一导电部31a隔开。每个第二铁电层36贯穿多个导电层31的第二导电部31b，且围绕第二导电柱34设置，以将第二导电柱34与多个导电层31的第二导电部31b隔开。
可以理解的是，如图11～图14所示，第一导电柱33、第一铁电层35和第一导电部31a被配置为形成第一电容器C1，第一导电柱33和第一导电部31a即为第一电容器C1的两极。第二导电柱34、第二铁电层36和第二导电部31b被配置为形成第二电容器C2，第二导电柱34和第二导电部31b即为第二电容器C2的两极，且第一电容器C1和第二电容器C2均为铁电电容器。
由于第一导电部31a与第二导电部31b相连，即第一电容器C1的一极与第二电容器C2的一极电连接，使得第一电容器C1与第二电容器C2串联设置。
本申请的上述实施例所提供的电容器3，采用第一导电柱33贯穿导电层31的第一导电部31a，并采用第一铁电层35围绕第一导电柱33设置，以将第一导电柱33与第一导电部31a隔开，第一导电柱33、第一铁电层35和第一导电部31a形成第一电容器C1，第一导电柱33和第一导电部31a作为第一电容器C1的两极。
并且，采用第二导电柱34贯穿导电层31的第二导电部31b，并采用第二铁电层36围绕第二导电柱34设置，以将第二导电柱34与第二导电部31b隔开，第二导电柱34、第二铁电层36和第二导电部31b形成第二电容器C2，第二导电柱34和第二导电部31b作为第二电容器C2的两极。
通过连接第一导电部31a和第二导电部31b，使第一电容器C1的一极与第二电容器C2的一极电连接，从而使第一电容器C1与第二电容器C2串联设置。参考图13，第一电容器C1与第二电容器C2形成串联电路，该串联电路两端的电势差为V1-V2，根据串联分压的原理，第一电容器C1两端的电势差要小于V1-V2，第二电容器C2两端的电势差要小于V1-V2，即通过电容器串联的方式，可减小每个电容器两端的电势差，从而可降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
根据前文可知，电容器的串联是通过导电层31中第一导电部31a与第二导电部31b相连而实现的，接下来，本申请的以下实施例提供多种第一导电部31a与第二导电部31b的排布方式，以对电容器串联的方式进行介绍。
在一些实施例中，一个导电层31包括至少一个第一导电部31a和至少一个第二导电部31b，并且，相连的第一导电部31a与第二导电部31b处于同一导电层，以便于第一导电部31a与第二导电部31b连接。
示例性地，参见图10和图11，一个导电层31包括一个第一导电部31a和一个第二导电部31b，第一导电部31a与第二导电部31b相连，且二者处于同一导电层。
例如，参见图11，处于同一导电层的第一导电部31a和第二导电部31b一体设置。
其中，第一导电部31a与第二导电部31b沿第一方向排列，该第一方向平行于第一堆叠层30的底面P。
需要说明的是，第一方向可以为X方向，也可以为Y方向，例如，图10中第一方向为X方向。
在一些实施例中，参见图11和图12，多个第一导电柱33贯穿一个导电层31的第一导电部31a，相当于多个第一电容器C1并联设置。多个第二导电柱34贯穿一个导电层31的第二导电部31b，相当于多个第二电容器C2并联设置。同一导电层31的第一导电部31a与第二导电部31b相连，使并联的多个第一电容器C1与并联的多个第二电容器C2串联，形成第三电容器C3。
本申请的上述实施例中，多个第一电容器C1并联的总电容值要大于一个第一电容器C1的电容值，多个第二电容器C2并联的总电容值要大于一个第二电容器C2的电容值，可增加第三电容器C3的电容值，从而增加电容器3的总电容值。
并且，并联的多个第一电容器C1与并联的多个第二电容器C2串联，形成第三电容器C3，可减小并联的多个电容器(第一电容器C1或第二电容器C2)的两端的电势差，减小每个电容器两端的电势差，从而可降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
在一些实施例中，参见图11和图12，多个第一导电柱33贯穿多个导电层31的第一导电部31a，多个第二导电柱34贯穿多个导电层31的第二导电部31b，相当于多个第三电容器C3并联设置，也可增加电容器3的总电容值。
在一些实施例中，参见图10和图11，电容器3还包括第一互联电极37和第二互联电极38， 第一互联电极37和第二互联电极38均为梳状结构，且第一互联电极37与第二互联电极38沿第一方向排列。
结合图10，第一互联电极37包括多条第一互联线371和第一连接部372，多条第一互联线371的同一端与第一连接部372连接形成梳状结构，多条第一互联线371即为梳状结构的“梳齿”，第一连接部372即为梳状结构的“梳背”。
同理，第二互联电极38包括多条第二互联线381和第二连接部382，多条第二互联线381的同一端与第二连接部382连接形成梳状结构，多条第二互联线381即为梳状结构的“梳齿”，第二连接部382即为梳状结构的“梳背”。
继续参见图10和图11，第一互联线371和第二互联线381均沿第二方向延伸，第二方向平行于第一堆叠层30的底面P，且与第一方向相交叉，例如，第二方向与第一方向相垂直。可以理解的是，第一互联线371和第二互联线381的延伸方向，与第一互联电极37与第二互联电极38的排列方向不相同。
示例性地，第一方向为X方向或Y方向中的一者，第二方向为另一者，例如，图10中第一方向为X方向，第二方向为Y方向。
多条第一互联线371与多个第一导电柱33的端部电连接，且多条第一互联线371在第一堆叠层30的沿第二方向的一侧连接，即第一互联电极37的第一连接部372位于第一堆叠层30的沿第二方向的一侧，通过第一互联电极37的多条第一互联线371向多个第一导电柱33传输电信号。
多条第二互联线381与多个第二导电柱34的端部电连接，且多条第二互联线381在第一堆叠层30的沿第二方向的一侧连接，即第二互联电极38的第二连接部382位于第一堆叠层30的沿第二方向的一侧，通过第二互联电极38的多条第二互联线381向多个第二导电柱34传输电信号。
示例性地，第一连接部372与第二连接部382可以位于第一堆叠层30的沿第二方向的同侧，也可以分别位于第一堆叠层30的沿第二方向的相对两侧。
图15为根据一些实施例的另一种电容器的俯视图。
在一些实施例中，参见图15，第一互联电极37和第二互联电极38也均为梳状结构，第一互联电极37与第二互联电极38沿第一方向排列。
示例性地，图15中第一方向为Y方向，第二方向为X方向。
第一互联电极37的第一互联线371和第二互联电极38的第二互联线381均沿第一方向延伸，即第一互联线371和第二互联线381的延伸方向，与第一互联电极37与第二互联电极38的排列方向相同。
多条第一互联线371与多个第一导电柱33的端部电连接，且多条第一互联线371在第一堆叠层30的沿第一方向的一侧连接，即第一互联电极37的第一连接部372位于第一堆叠层30的沿第一方向的一侧，通过第一互联电极37的多条第一互联线371向多个第一导电柱33传输电信号。
多条第二互联线381与多个第二导电柱34的端部电连接，且多条第二互联线381在第一堆叠层30的沿第一方向的另一侧连接，即第二互联电极38的第二连接部382位于第一堆叠层30的沿第一方向的另一侧，通过第二互联电极38的多条第二互联线381向多个第二导电柱34传输电信号。
示例性地，第一连接部372与第二连接部382分别位于第一堆叠层30的沿第一方向的相对两侧。
在一些实施例中，参见图15，多个第一导电柱33包括多排，例如，每排第一导电柱33可与第一互联线371沿相同的方向延伸。一条第一互联线371与一排第一导电柱33电连接，以通过第一互联线371向一排第一导电柱33传输电信号。
或者，多个第二导电柱34包括多排，例如，每排第二导电柱34可与第二互联线381沿相同的方向延伸。一条第二互联线381与一排第二导电柱34电连接，以通过第二互联线381向一排第二导电柱34传输电信号。
又或者，多个第一导电柱33包括多排，一条第一互联线371与一排第一导电柱33电连接。并且，多个第二导电柱34包括多排，一条第二互联线381与一排第二导电柱34电连接。
图16和图17为根据一些实施例的另一种电容器的俯视图。
在一些实施例中，参见图16和图17，第一互联电极37和第二互联电极38均为面状结构，第一互联电极37与第二互联电极38沿第一方向排列。
示例性地，图16中第一方向为X方向，第二方向为Y方向；图17中第一方向为Y方向，第二方向为X方向。
面状的第一互联电极37与多个第一导电柱33的端部电连接，以通过第一互联电极37向多个第一导电柱33传输电信号。
面状的第二互联电极38与多个第二导电柱34的端部电连接，以通过第二互联电极38向多个第二导电柱34传输电信号。
在一些实施例中，参见图16和图17，多个第一导电柱33呈阵列式排布，或者，多个第二导电柱34呈阵列式排布，又或者，多个第一导电柱33和多个第二导电柱34均呈阵列式排布，可提高多个第一导电柱33和多个第二导电柱34排布的均匀性，有利于改善多个电容器之间信号干扰的现象。
图18为根据一些实施例的另一种电容器的俯视图；图19为图18中的电容器的等效电路图；图20为根据一些实施例的又一种电容器的俯视图；图21为图20中的电容器的等效电路图。
在一些实施例中，参见图18和图20，一个导电层31可包括多个第一导电部31a和多个第二导电部31b，多个第一导电部31a与多个第二导电部31b相连，且均处于同一导电层。例如，处于同一导电层的多个第一导电部31a和多个第二导电部31b一体设置。
其中，第一导电部31a与第二导电部31b沿第一方向交替排列，例如，图18和图20中第一方向均为X方向。
在一些实施例中，参见图18和图19，或图20和图21，多个第一导电柱33贯穿多个第一导电部31a，相当于多个第一电容器C1并联设置。多个第二导电柱34贯穿多个第二导电部31b，相当于多个第二电容器C2并联设置。同一导电层31的多个第一导电部31a与多个第二导电部31b相连，使并联的多个第一电容器C1与并联的多个第二电容器C2串联，形成第三电容器C3。
上述实施例中，通过电容器串联的方式，可减小每个电容器两端的电势差，从而可降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
在一些实施例中，参见图18和图19，或图20和图21，多个第一导电柱33贯穿多个导电层31的第一导电部31a，多个第二导电柱34贯穿多个导电层31的第二导电部31b，相当于多个第三电容器C3并联设置，也可增加电容器3的总电容值。
在一些实施例中，参见图18和图20，电容器3还包括第一互联电极37和第二互联电极38，第一互联电极37和第二互联电极38均为梳状结构。
结合图18，第一互联电极37包括多条第一互联线371和第一连接部372，多条第一互联线371的同一端与第一连接部372连接形成梳状结构，多条第一互联线371即为梳状结构的“梳齿”，第一连接部372即为梳状结构的“梳背”。
同理，第二互联电极38包括多条第二互联线381和第二连接部382，多条第二互联线381的同一端与第二连接部382连接形成梳状结构，多条第二互联线381即为梳状结构的“梳齿”，第二连接部382即为梳状结构的“梳背”。
继续参见图18和图20，多条第一互联线371与多条第二互联线381沿第一方向排列，第一互联线371和第二互联线381均沿第二方向延伸。
示例性地，图18中第一方向为X方向，第二方向为Y方向，多条第一互联线371与多条第二互联线381沿第一方向交替排列。
示例性地，图20中第一方向为X方向，第二方向为Y方向，相邻两条第一互联线371之间不设置第二互联线381，或设置有多条第二互联线381。相邻两条第二互联线381之间不设置第一互联线371，或设置有多条第一互联线371。
多条第一互联线371与多个第一导电柱33的端部电连接，且多条第一互联线371在第一堆叠层30的沿第二方向的一侧连接，即第一互联电极37的第一连接部372位于第一堆叠层30的沿第二方向的一侧，通过第一互联电极37的多条第一互联线371向多个第一导电柱33传输电信号。
多条第二互联线381与多个第二导电柱34的端部电连接，且多条第二互联线381在第一堆叠 层30的沿第二方向的另一侧连接，即第二互联电极38的第二连接部382位于第一堆叠层30的沿第二方向的另一侧，通过第二互联电极38的多条第二互联线381向多个第二导电柱34传输电信号。
在一些实施例中，参见图18和图20，多个第一导电柱33包括多排，例如，每排第一导电柱33可与第一互联线371沿相同的方向延伸。一条第一互联线371与一排第一导电柱33电连接，以通过第一互联线371向一排第一导电柱33传输电信号。
或者，多个第二导电柱34包括多排，例如，每排第二导电柱34可与第二互联线381沿相同的方向延伸。一条第二互联线381与一排第二导电柱34电连接，以通过第二互联线381向一排第二导电柱34传输电信号。
又或者，多个第一导电柱33包括多排，一条第一互联线371与一排第一导电柱33电连接。并且，多个第二导电柱34包括多排，一条第二互联线381与一排第二导电柱34电连接。
在一些实施例中，还可以通过将导电层31分割成多块，以增加串联的电容器的数量，从而可进一步减小每个电容器两端的电势差，降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
本申请的一些实施例还提供了一种电容器的制备方法，图22A～图22E为根据一些实施例的制备一种电容器的各步骤图，该制备方法包括如下步骤：
参见图22A，形成第一堆叠层30，第一堆叠层30包括交替层叠设置的多个导电层31和多个第一介质层32，一个导电层31包括相连的第一导电部31a和第二导电部31b。
示例性地，在走线区A2形成第一堆叠层30的过程中，在阵列区A1同步形成第二堆叠层D。
参见图22B，刻蚀第一堆叠层30，形成贯穿第一导电部31a的第一接触孔H1，及贯穿第二导电部31b的第二接触孔H2。
示例性地，第一接触孔H1贯穿多个导电层31的第一导电部31a，第二接触孔H2贯穿多个导电层31的第二导电部31b。
参见图22C，在第一接触孔H1的侧壁上形成第一铁电层35，并在第二接触孔H2的侧壁上形成第二铁电层36。
参见图22D，在第一铁电层35的内侧形成第一导电柱33，并在第二铁电层36的内侧形成第二导电柱34。
本申请的上述实施例所提供的制备方法，先形成第一堆叠层30，第一堆叠层30包括交替层叠设置的多个导电层31和多个第一介质层32，一个导电层31包括相连的第一导电部31a和第二导电部31b。然后，形成贯穿第一导电部31a的第一接触孔H1，及贯穿第二导电部31b的第二接触孔H2，在第一接触孔H1的侧壁上形成第一铁电层35和第一导电柱33，在第二接触孔H2的侧壁上形成第二铁电层36和第二导电柱34。
第一导电柱33、第一铁电层35和第一导电部31a形成第一电容器C1，第一导电柱33和第一导电部31a作为第一电容器C1的两极。第二导电柱34、第二铁电层36和第二导电部31b形成第二电容器C2，第二导电柱34和第二导电部31b作为第二电容器C2的两极。通过连接第一导电部31a和第二导电部31b，使第一电容器C1的一极与第二电容器C2的一极电连接，从而使第一电容器C1与第二电容器C2串联设置，可减小每个电容器两端的电势差，从而可降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
在一些实施例中，形成第一导电柱33和第二导电柱34之后，上述制备方法还包括如下步骤：
参见图22E，形成第一互联电极37和第二互联电极38，例如，第一互联电极37和第二互联电极38均形成于第一堆叠层30的顶部。第一互联电极37与多个第一导电柱33的端部电连接，以向多个第一导电柱33传输电信号。第二互联电极38与多个第二导电柱34的端部电连接，以向多个第二导电柱34传输电信号。
图23为根据一些实施例的又一种电容器的俯视图；图24为图23中的电容器沿剖面线B-B＇的剖视图；图25为图24中的电容器的等效电路图。
参见图23和图24，一个导电层31包括多个分隔设置的导电块310，相当于，一个导电层31被分割成多个导电块310，多个导电块310之间断开。并且，一个导电块310包括相连的一个第 一导电部31a和一个第二导电部31b。
示例性地，电容器3还包括第二介质层40，第二介质层40贯穿第一堆叠层30，且隔开相邻两个导电块310。可以理解的是，第二介质层40将导电层31分割成多个导电块310。
参见图23～图25，多个第一导电柱33贯穿一个导电块310的第一导电部31a，相当于多个第一电容器C1并联设置。多个第二导电柱34贯穿一个导电块310的第二导电部31b，相当于多个第二电容器C2并联设置。同一导电块310的第一导电部31a与第二导电部31b相连，使并联的多个第一电容器C1与并联的多个第二电容器C2串联，形成第三电容器C3。
并且，相邻两个导电块310中，贯穿一个导电块310的多个第二导电柱34，与贯穿另一个导电块310的多个第一导电柱33电连接，使相邻的导电块310的第三电容器C3串联，形成第四电容器C4。
本申请的上述实施例中，多个第一电容器C1并联的总电容值要大于一个第一电容器C1的电容值，多个第二电容器C2并联的总电容值要大于一个第二电容器C2的电容值，可增加第三电容器C3的电容值，增加第四电容器C4的电容值，从而增加电容器3的总电容值。
并且，并联的多个第一电容器C1与并联的多个第二电容器C2串联，形成第三电容器C3，相邻的导电块310的第三电容器C3串联，形成第四电容器C4，以增加串联的电容器的数量，从而可进一步减小每个电容器两端的电势差，降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
在一些实施例中，一个导电层31包括依次设置的第1个导电块～第n个导电块，n≥2，且n为正整数。
示例性地，参见图23和图24，一个导电层31包括依次设置的第1个导电块310a和第2个导电块310b，即n＝2。
继续参见图23和图24，电容器3还包括一个第一互联电极37、至少一个第二互联电极38和一个第三互联电极39，第一互联电极37与贯穿第1个导电块的第一导电柱33电连接。第二互联电极38与贯穿第i个导电块的第二导电柱34电连接，并与贯穿第i+1个导电块的第一导电柱33电连接，i＝1～n-1，且i为正整数。第三互联电极39与贯穿第n个导电块的第二导电柱34电连接。
示例性地，参见图23和图24，一个导电层31包括依次设置的第1个导电块310a和第2个导电块310b，即n＝2，在此情况下，电容器3包括一个第二互联电极38。
第一互联电极37与贯穿第1个导电块310a的第一导电柱33电连接，第二互联电极38与贯穿第1个导电块310a的第二导电柱34电连接，并与贯穿第2个导电块310b的第一导电柱33电连接，第三互联电极39与贯穿第2个导电块310b的第二导电柱34电连接。
可以理解的是，结合图24和图25，第一互联电极37和第三互联电极39接收外部的电信号，并将该电信号传输至第四电容器C4。而第二互联电极38作为连接电极，其不接收外部的电信号。
本申请的一些实施例还提供了一种电容器的制备方法，图26A～图26G为根据一些实施例的制备另一种电容器的各步骤图，该制备方法包括如下步骤：
参见图26A，形成第一堆叠层30，第一堆叠层30包括交替层叠设置的多个导电层31和多个第一介质层32。
示例性地，在走线区A2形成第一堆叠层30的过程中，在阵列区A1同步形成第二堆叠层D。
参见图26B，刻蚀第一堆叠层30，形成贯穿第一堆叠层30的第一接触孔H1，及贯穿第一堆叠层30的第二接触孔H2。
示例性地，第一接触孔H1贯穿第一堆叠层30的多个导电层31，第二接触孔H2贯穿第一堆叠层30的多个导电层31。
参见图26C，在第一接触孔H1的侧壁上形成第一铁电层35，并在第二接触孔H2的侧壁上形成第二铁电层36。
参见图26D，在第一铁电层35的内侧形成第一导电柱33，并在第二铁电层36的内侧形成第二导电柱34。
在一些示例中，在形成第一堆叠层30之后，制备方法还包括如下步骤：
参见图26E，形成贯穿第一堆叠层30的至少一个隔离沟槽G，至少一个隔离沟槽G将导电层 31分隔成多个导电块310，一个导电块310包括一个第一导电部31a和一个第二导电部31b，第一导电部31a与第二导电部31b相连。
每个导电层31包括依次设置的第1个导电块～第n个导电块，n≥2，且n为正整数。
示例性地，参见图26E，一个导电层31包括依次设置的第1个导电块310a和第2个导电块310b，即n＝2。
参见图26F，在隔离沟槽G内形成第二介质层40。
在一些示例中，在形成第一导电柱33和第二导电柱34之后，制备方法还包括如下步骤：
参见图26G，形成一个第一互联电极37、至少一个第二互联电极38和一个第三互联电极39，第一互联电极37与贯穿第1个导电块的第一导电柱33电连接。第二互联电极38与贯穿第i个导电块的第二导电柱34电连接，并与贯穿第i+1个导电块的第一导电柱33电连接，i＝1～n-1，且i为正整数。第三互联电极39与贯穿第n个导电块的第二导电柱34电连接。
示例性地，参见图26G，一个导电层31包括依次设置的第1个导电块310a和第2个导电块310b，即n＝2，在此情况下，形成一个第二互联电极38。
第一互联电极37与贯穿第1个导电块310a的第一导电柱33电连接，第二互联电极38与贯穿第1个导电块310a的第二导电柱34电连接，并与贯穿第2个导电块310b的第一导电柱33电连接，第三互联电极39与贯穿第2个导电块310b的第二导电柱34电连接。
本申请的上述实施例所提供的制备方法，先形成第一堆叠层30，第一堆叠层30包括交替层叠设置的多个导电层31和多个第一介质层32。然后，形成贯穿第一导电部31a的第一接触孔H1，及贯穿第二导电部31b的第二接触孔H2，在第一接触孔H1的侧壁上形成第一铁电层35和第一导电柱33，在第二接触孔H2的侧壁上形成第二铁电层36和第二导电柱34。
通过刻蚀第一堆叠层30，形成贯穿第一堆叠层30的隔离沟槽G，并在隔离沟槽G内形成第二介质层40，以将导电层31分割成多个导电块310，以增加串联的电容器的数量，从而可进一步减小每个电容器两端的电势差，降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
图27为根据一些实施例的又一种电容器的剖视图；图28为图27中的电容器的等效电路图。
在一些实施例中，参见图27，多个导电层31包括多个第一导电部31a和多个第二导电部31b，多个第二导电部31b位于多个第一导电部31a的远离第一堆叠层30的底面P的一侧。
示例性地，多个第一导电部31a和多个第一介质层32交替层叠设置，多个第二导电部31b和多个第一介质层32交替层叠设置。
参见图27和图28，多个第一导电柱33贯穿多个第一导电部31a，相当于多个第一电容器C1并联设置。多个第二导电柱34贯穿多个第二导电部31b，相当于多个第二电容器C2并联设置。
在此基础上，电容器3还包括贯穿第一堆叠层30的第三导电柱41，第三导电柱41与多个第一导电部31a和多个第二导电部31b电连接，使并联的多个第一电容器C1与并联的多个第二电容器C2串联。
本申请的上述实施例中，多个第一电容器C1并联的总电容值要大于一个第一电容器C1的电容值，多个第二电容器C2并联的总电容值要大于一个第二电容器C2的电容值，可增加电容器3的总电容值。
并且，并联的多个第一电容器C1与并联的多个第二电容器C2串联，可减小并联的多个电容器(第一电容器C1或第二电容器C2)的两端的电势差，减小每个电容器两端的电势差，从而可降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
在一些实施例中，参见图27，电容器3还包括第一互联电极37和第二互联电极38，第一互联电极37设置于第一堆叠层30的底面P的远离多个第一导电部31a的一侧，即第一互联电极37设置于第一堆叠层30的底部，且第一互联电极37与多个第一导电柱33的端部电连接，通过第一互联电极37向多个第一导电柱33传输电信号。
第二互联电极38设置于多个第二导电部31b的远离第一堆叠层30的底面P的一侧，即第二互联电极38设置于第一堆叠层30的顶部，且第二互联电极38与多个第二导电柱34的端部电连接，通过第二互联电极38向多个第二导电柱34传输电信号。
本申请的一些实施例还提供了一种电容器的制备方法，图29A～图29K为根据一些实施例的制备又一种电容器的各步骤图，该制备方法包括如下步骤：
参见图29A，形成第一子堆叠层30a，第一子堆叠层30a包括交替层叠设置的多个第一导电部31a和多个第一介质层32。
在一些示例中，在形成第一子堆叠层30a之前，形成第一互联电极37，第一互联电极37位于第一子堆叠层30a的底部。
参见图29B，形成贯穿多个第一导电部31a的第一接触孔H1。
参见图29C，在第一接触孔H1的侧壁上形成第一铁电层35。
参见图29D，在第一铁电层35的内侧形成第一导电柱33。
参见图29E，形成绝缘层42，绝缘层42覆盖第一子堆叠层30a、第一铁电层35和第一导电柱33。
参见图29F，在绝缘层42远离第一子堆叠层30a的一侧形成第二子堆叠层30b，第二子堆叠层30b包括交替层叠设置的多个第二导电部31b和多个第一介质层32。
参见图29G，形成贯穿多个第二导电部31b的第二接触孔H2。
参见图29H，在第二接触孔H2的侧壁上形成第二铁电层36。
参见图29I，在第二铁电层36的内侧形成第二导电柱34。
参见图29J，形成第三导电柱41，第三导电柱41贯穿第二子堆叠层30b、绝缘层42和第一子堆叠层30a，且第三导电柱41与多个第一导电部31a和多个第二导电部31b电连接。
在一些示例中，参见图29K，在形成第三导电柱41之后，形成第二互联电极38，第二互联电极38位于第二子堆叠层30b的顶部。
本申请的上述实施例所提供的制备方法，先形成第一子堆叠层30a，第一子堆叠层30a包括交替层叠设置的多个第一导电部31a和多个第一介质层32。然后，形成贯穿多个第一导电部31a的第一接触孔H1，在第一接触孔H1的侧壁上形成第一铁电层35和第一导电柱33。
而后，在第一子堆叠层30a的上方形成第二子堆叠层30b，第二子堆叠层30b包括交替层叠设置的多个第二导电部31b和多个第一介质层32。然后，形成贯穿多个第二导电部31b的第二接触孔H2，在第二接触孔H2的侧壁上形成第二铁电层36和第二导电柱34。
最后，形成贯穿第二子堆叠层30b和第一子堆叠层30a的第三导电柱41，第三导电柱41与多个第一导电部31a和多个第二导电部31b电连接，使并联的多个第一电容器C1与并联的多个第二电容器C2串联，可减小每个电容器两端的电势差，从而可降低电容器中铁电层发生极化翻转的概率，保证电容器的容值稳定，提高电容器的抗干扰能力。
本申请的以上各实施例中，导电层31、第一导电柱33和第二导电柱34的材料包括Ti、Au、W、Mo、Al、Cu、Ru、Ag、TiN、ITO中的至少一种，即导电层31、第一导电柱33和第二导电柱34的材料可包括这些材料中的一种或多种。
第一铁电层35的材料包括ZrO2、HfO2、HfAlO、HfSiO、HfZrO、HfLaO、HfYO中的至少一种，即第一铁电层35的材料可包括这些材料中的一种或多种。第二铁电层36的材料包括ZrO2、HfO2、HfAlO、HfSiO、HfZrO、HfLaO、HfYO中的至少一种，即第二铁电层36的材料可包括这些材料中的一种或多种。
第一介质层32为单层结构或叠层结构，第一介质层32的材料包括SiO2、Al2O3、HfO2、ZrO2、TiO2、Y2O3、Si3N4中的至少一种，即第一介质层32的材料可包括这些材料中的一种或多种。
本申请的一些实施例所提供的铁电存储器、三维集成电路及电子设备，包括上述任一实施例所提供的电容器，其所能达到的有益效果可参考上文中电容器的有益效果，此处不再赘述。
以上所述仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (28)

  1. 一种铁电存储器，其特征在于，包括阵列区和走线区，所述铁电存储器包括设置于所述阵列区的存储阵列，及设置于所述走线区的电容器；
    所述电容器包括：
    第一堆叠层，包括交替层叠设置的多个导电层和多个第一介质层；所述多个导电层包括相连的第一导电部和第二导电部；
    第一导电柱和第二导电柱，所述第一导电柱贯穿所述第一导电部，所述第二导电柱贯穿所述第二导电部；
    第一铁电层和第二铁电层，所述第一铁电层和所述第二铁电层为筒状结构；所述第一铁电层贯穿所述第一导电部，且围绕所述第一导电柱设置；所述第二铁电层贯穿所述第二导电部，且围绕所述第二导电柱设置；
    其中，所述电容器包括串联设置的第一电容器和第二电容器，所述第一电容器包括所述第一导电柱、所述第一铁电层和所述第一导电部，所述第二电容器包括所述第二导电柱、所述第二铁电层和所述第二导电部。
  2. 根据权利要求1所述的铁电存储器，其特征在于，每个所述导电层包括至少一个第一导电部和至少一个第二导电部，相连的所述第一导电部与所述第二导电部处于同一导电层。
  3. 根据权利要求2所述的铁电存储器，其特征在于，每个所述导电层包括一个第一导电部和一个第二导电部，所述第一导电部与所述第二导电部相连；
    所述第一导电部与所述第二导电部沿第一方向排列，所述第一方向平行于所述第一堆叠层的底面；
    多个所述第一导电柱贯穿所述第一导电部，多个所述第二导电柱贯穿所述第二导电部。
  4. 根据权利要求3所述的铁电存储器，其特征在于，所述电容器还包括第一互联电极和第二互联电极，所述第一互联电极和所述第二互联电极为面状结构；
    所述第一互联电极与所述第二互联电极沿所述第一方向排列；
    所述第一互联电极与多个所述第一导电柱的端部电连接，所述第二互联电极与多个所述第二导电柱的端部电连接。
  5. 根据权利要求3或4所述的铁电存储器，其特征在于，多个所述第一导电柱呈阵列式排布，和/或，多个所述第二导电柱呈阵列式排布。
  6. 根据权利要求3所述的铁电存储器，其特征在于，所述电容器还包括第一互联电极和第二互联电极，所述第一互联电极和所述第二互联电极为梳状结构；
    所述第一互联电极与所述第二互联电极沿所述第一方向排列，所述第一互联电极包括多条第一互联线，所述第二互联电极包括多条第二互联线；
    所述第一互联线和所述第二互联线沿所述第一方向延伸；所述多条第一互联线与多个所述第一导电柱的端部电连接，且所述多条第一互联线在所述第一堆叠层的沿所述第一方向的一侧连接；所述多条第二互联线与多个所述第二导电柱的端部电连接，且所述多条第二互联线在所述第一堆叠层的沿所述第一方向的另一侧连接；或，
    所述第一互联线和所述第二互联线沿第二方向延伸；所述多条第一互联线与多个所述第一导电柱的端部电连接，且所述多条第一互联线在所述第一堆叠层的沿所述第二方向的一侧连接；所述多条第二互联线与多个所述第二导电柱的端部电连接，且所述多条第二互联线在所述第一堆叠层的沿所述第二方向的一侧连接；所述第二方向平行于所述第一堆叠层的底面，且与所述第一方向相交叉。
  7. 根据权利要求2所述的铁电存储器，其特征在于，每个所述导电层包括多个第一导电部和多个第二导电部，所述多个第一导电部与所述多个第二导电部相连；
    所述第一导电部与所述第二导电部沿第一方向交替排列，所述第一方向平行于所述第一堆叠层的底面；
    多个所述第一导电柱贯穿所述第一导电部，多个所述第二导电柱贯穿所述第二导电部。
  8. 根据权利要求7所述的铁电存储器，其特征在于，所述电容器还包括第一互联电极和第二 互联电极，所述第一互联电极和所述第二互联电极为梳状结构；
    所述第一互联电极包括多条第一互联线，所述第二互联电极包括多条第二互联线，所述多条第一互联线与所述多条第二互联线沿所述第一方向排列，所述第一互联线和所述第二互联线沿第二方向延伸；所述第二方向平行于所述第一堆叠层的底面，且与所述第一方向相交叉；
    所述多条第一互联线与多个所述第一导电柱的端部电连接，且所述多条第一互联线在所述第一堆叠层的沿所述第二方向的一侧连接；所述多条第二互联线与多个所述第二导电柱的端部电连接，且所述多条第二互联线在所述第一堆叠层的沿所述第二方向的另一侧连接。
  9. 根据权利要求8所述的铁电存储器，其特征在于，所述多条第一互联线与所述多条第二互联线沿所述第一方向交替排列；或，
    相邻两条第一互联线之间不设置所述第二互联线，或设置有多条第二互联线；相邻两条第二互联线之间不设置所述第一互联线，或设置有多条第一互联线。
  10. 根据权利要求6、8、9中任一项所述的铁电存储器，其特征在于，所述多个第一导电柱包括多排，一条第一互联线与一排第一导电柱电连接；和/或，
    所述多个第二导电柱包括多排，一条第二互联线与一排第二导电柱电连接。
  11. 根据权利要求2～10中任一项所述的铁电存储器，其特征在于，处于同一导电层的所述第一导电部和所述第二导电部一体设置。
  12. 根据权利要求2所述的铁电存储器，其特征在于，每个所述导电层包括多个分隔设置的导电块，一个所述导电块包括相连的一个第一导电部和一个第二导电部；
    多个所述第一导电柱贯穿所述导电块的第一导电部，多个所述第二导电柱贯穿所述导电块的第二导电部；
    相邻两个导电块中，贯穿一个导电块的多个第二导电柱，与贯穿另一个导电块的多个第一导电柱电连接。
  13. 根据权利要求12所述的铁电存储器，其特征在于，所述电容器还包括第二介质层，所述第二介质层贯穿所述第一堆叠层，且隔开相邻两个导电块。
  14. 根据权利要求12或13所述的铁电存储器，其特征在于，每个所述导电层包括依次设置的第1个导电块～第n个导电块，n≥2，且n为正整数；
    所述电容器还包括一个第一互联电极、至少一个第二互联电极和一个第三互联电极，所述第一互联电极与贯穿第1个导电块的第一导电柱电连接；所述第二互联电极与，贯穿第i个导电块的第二导电柱和贯穿第i+1个导电块的第一导电柱电连接，i＝1～n-1，且i为正整数；所述第三互联电极与贯穿第n个导电块的第二导电柱电连接。
  15. 根据权利要求1所述的铁电存储器，其特征在于，所述多个导电层包括多个第一导电部和多个第二导电部，所述多个第二导电部位于所述多个第一导电部的远离所述第一堆叠层的底面的一侧；
    多个所述第一导电柱贯穿所述多个第一导电部，多个所述第二导电柱贯穿所述多个第二导电部；
    所述电容器还包括贯穿所述第一堆叠层的第三导电柱，所述第三导电柱与所述多个第一导电部和所述多个第二导电部电连接。
  16. 根据权利要求15所述的铁电存储器，其特征在于，所述电容器还包括第一互联电极和第二互联电极；
    所述第一互联电极设置于所述第一堆叠层的底面的远离所述多个第一导电部的一侧，且与多个所述第一导电柱的端部电连接；
    所述第二互联电极设置于所述多个第二导电部的远离所述第一堆叠层的底面的一侧，且与多个所述第二导电柱的端部电连接。
  17. 根据权利要求1～16中任一项所述的铁电存储器，其特征在于，所述导电层、所述第一导电柱和所述第二导电柱的材料包括Ti、Au、W、Mo、Al、Cu、Ru、Ag、TiN、ITO中的至少一种。
  18. 根据权利要求1～17中任一项所述的铁电存储器，其特征在于，所述第一铁电层和/或所述 第二铁电层的材料包括ZrO2、HfO2、HfAlO、HfSiO、HfZrO、HfLaO、HfYO中的至少一种。
  19. 根据权利要求1～18中任一项所述的铁电存储器，其特征在于，所述第一介质层为单层结构或叠层结构；
    所述第一介质层的材料包括SiO2、Al2O3、HfO2、ZrO2、TiO2、Y2O3、Si3N4中的至少一种。
  20. 根据权利要求1～19中任一项所述的铁电存储器，其特征在于，所述存储阵列包括第二堆叠层，所述第二堆叠层包括阵列式排布的多个存储单元；
    所述第二堆叠层包括交替设置的第三介质层和栅极层；所述第一堆叠层的多个第一介质层与所述第二堆叠层的多个第三介质层一一对应，相对应的第一介质层与第三介质层的材料相同且同层设置；所述第一堆叠层的多个导电层与所述第二堆叠层的多个栅极层一一对应，相对应的导电层与栅极层的材料相同、同层设置、且相互绝缘。
  21. 一种铁电存储器的制备方法，其特征在于，包括：
    形成第一堆叠层，所述第一堆叠层包括交替层叠设置的多个导电层和多个第一介质层；所述多个导电层包括相连的第一导电部和第二导电部；
    形成贯穿所述第一导电部的第一接触孔，及贯穿所述第二导电部的第二接触孔；
    在所述第一接触孔的侧壁上形成第一铁电层，并在所述第二接触孔的侧壁上形成第二铁电层；
    在所述第一铁电层的内侧形成第一导电柱，并在所述第二铁电层的内侧形成第二导电柱。
  22. 根据权利要求21所述的制备方法，其特征在于，所述形成第一导电柱和第二导电柱之后，还包括：
    形成第一互联电极和第二互联电极，所述第一互联电极与多个所述第一导电柱的端部电连接，所述第二互联电极与多个所述第二导电柱的端部电连接。
  23. 根据权利要求21所述的制备方法，其特征在于，所述形成第一堆叠层之后，还包括：
    形成贯穿所述第一堆叠层的至少一个隔离沟槽，所述至少一个隔离沟槽将所述导电层分隔成多个导电块；一个所述导电块包括一个第一导电部和一个第二导电部，所述第一导电部与所述第二导电部相连；
    在所述隔离沟槽内形成第二介质层。
  24. 根据权利要求23所述的制备方法，其特征在于，每个所述导电层包括依次设置的第1个导电块～第n个导电块，n≥2，且n为正整数；
    所述形成第一导电柱和第二导电柱之后，还包括：
    形成一个第一互联电极、至少一个第二互联电极和一个第三互联电极，所述第一互联电极与贯穿第1个导电块的第一导电柱电连接；所述第二互联电极与，贯穿第i个导电块的第二导电柱和贯穿第i+1个导电块的第一导电柱电连接，i＝1～n-1，且i为正整数；所述第三互联电极与贯穿第n个导电块的第二导电柱电连接。
  25. 根据权利要求21～24中任一项所述的制备方法，其特征在于，所述铁电存储器包括阵列区和走线区；
    在所述走线区形成所述第一堆叠层的过程中，在所述阵列区同步形成第二堆叠层。
  26. 一种铁电存储器的制备方法，其特征在于，包括：
    形成第一子堆叠层，所述第一子堆叠层包括交替层叠设置的多个第一导电部和多个第一介质层；
    形成贯穿所述多个第一导电部的第一接触孔；
    在所述第一接触孔的侧壁上形成第一铁电层；
    在所述第一铁电层的内侧形成第一导电柱；
    形成绝缘层，所述绝缘层覆盖所述第一子堆叠层、所述第一铁电层和所述第一导电柱；
    在所述绝缘层远离所述第一子堆叠层的一侧形成第二子堆叠层，所述第二子堆叠层包括交替层叠设置的多个第二导电部和多个第一介质层；
    形成贯穿所述多个第二导电部的第二接触孔；
    在所述第二接触孔的侧壁上形成第二铁电层；
    在所述第二铁电层的内侧形成第二导电柱；
    形成第三导电柱，所述第三导电柱贯穿所述第二子堆叠层、所述绝缘层和所述第一子堆叠层，且与所述多个第一导电部和所述多个第二导电部电连接。
  27. 一种三维集成电路，其特征在于，包括：
    如权利要求1～20中任一项所述的铁电存储器；
    处理器芯片，与所述铁电存储器叠置，且与所述铁电存储器电连接。
  28. 一种电子设备，其特征在于，包括：
    电路板；
    如权利要求1～20中任一项所述的铁电存储器或如权利要求27所述的三维集成电路，设置于所述电路板上，且与所述电路电连接。
PCT/CN2023/103240 2022-09-14 2023-06-28 铁电存储器、三维集成电路、电子设备 WO2024055685A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211115561.7 2022-09-14
CN202211115561.7A CN117769258A (zh) 2022-09-14 2022-09-14 铁电存储器、三维集成电路、电子设备

Publications (1)

Publication Number Publication Date
WO2024055685A1 true WO2024055685A1 (zh) 2024-03-21

Family

ID=90274155

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/103240 WO2024055685A1 (zh) 2022-09-14 2023-06-28 铁电存储器、三维集成电路、电子设备

Country Status (2)

Country Link
CN (1) CN117769258A (zh)
WO (1) WO2024055685A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170053932A1 (en) * 2015-08-20 2017-02-23 SK Hynix Inc. Semiconductor memory device
WO2020204314A1 (ko) * 2019-03-29 2020-10-08 한양대학교 산학협력단 강유전체 물질 기반의 3차원 플래시 메모리 및 그 제조
US20210143162A1 (en) * 2019-11-12 2021-05-13 Samsung Electronics Co., Ltd. Semiconductor memory device including capacitor
CN113196484A (zh) * 2019-11-25 2021-07-30 桑迪士克科技有限责任公司 包括集成栅极选择器的三维铁电存储器阵列及其形成方法
CN113782538A (zh) * 2021-09-07 2021-12-10 长江存储科技有限责任公司 三维存储器及其制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170053932A1 (en) * 2015-08-20 2017-02-23 SK Hynix Inc. Semiconductor memory device
WO2020204314A1 (ko) * 2019-03-29 2020-10-08 한양대학교 산학협력단 강유전체 물질 기반의 3차원 플래시 메모리 및 그 제조
US20210143162A1 (en) * 2019-11-12 2021-05-13 Samsung Electronics Co., Ltd. Semiconductor memory device including capacitor
CN112864165A (zh) * 2019-11-12 2021-05-28 三星电子株式会社 包括电容器的半导体存储器装置
CN113196484A (zh) * 2019-11-25 2021-07-30 桑迪士克科技有限责任公司 包括集成栅极选择器的三维铁电存储器阵列及其形成方法
CN113782538A (zh) * 2021-09-07 2021-12-10 长江存储科技有限责任公司 三维存储器及其制备方法

Also Published As

Publication number Publication date
CN117769258A (zh) 2024-03-26

Similar Documents

Publication Publication Date Title
CN106252353B (zh) 具有三维nand存储器的电容器的集成电路及其制造方法
WO2022188010A1 (zh) 半导体装置、电子设备、晶体管的形成方法
US10128255B2 (en) Semiconductor device
US20230253040A1 (en) Memory cell including programmable resistors with transistor components
JP6147930B2 (ja) 垂直メモリ構成要素を有するモノリシック３次元（３ｄ）集積回路（ｉｃｓ）（３ｄｉｃ）
WO2024055685A1 (zh) 铁电存储器、三维集成电路、电子设备
CN102645811B (zh) 电子纸有源基板及其制造方法和电子纸显示屏
CN109491551B (zh) 显示基板及其制造方法、显示装置
KR20120121727A (ko) 반도체 셀 및 그 형성 방법, 셀 어레이, 반도체 소자, 반도체 모듈, 반도체 시스템, 전자 유닛 및 전자 시스템
WO2023193591A1 (zh) 半导体结构及其制备方法、三维存储器、电子设备
US11404099B1 (en) Using split word lines and switches for reducing capacitive loading on a memory system
US20230176818A1 (en) Semiconductor device
WO2022188040A1 (zh) 一种铁电晶体管、存储阵列、存储器及制备方法
WO2023115418A1 (zh) 一种铁电存储器及电子设备
TWI741996B (zh) 提供動態隨機存取記憶單元之電容的方法、裝置及系統
CN117750776A (zh) 存储芯片及电子设备
WO2023202249A1 (zh) 存储器及其制备方法、电子设备
US20210202504A1 (en) System and Method for Reducing Resistance in Anti-Fuse Cell
WO2024060021A1 (zh) 一种三维存储阵列、存储器及电子设备
WO2024037163A1 (zh) 存储阵列及其制备方法、存储器、电子设备
US12002499B2 (en) Using split word lines and switches for reducing capacitive loading on a memory system
WO2024092405A1 (zh) 触控结构、触控显示面板和电子装置
CN110568644B (zh) 一种gip电容结构及制作方法
WO2024031438A1 (zh) 一种三维存储阵列、存储器及电子设备
WO2023197715A1 (zh) 存储器及其制作方法、电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23864424

Country of ref document: EP

Kind code of ref document: A1