WO2023193591A1 - 半导体结构及其制备方法、三维存储器、电子设备 - Google Patents

半导体结构及其制备方法、三维存储器、电子设备 Download PDF

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Publication number
WO2023193591A1
WO2023193591A1 PCT/CN2023/082332 CN2023082332W WO2023193591A1 WO 2023193591 A1 WO2023193591 A1 WO 2023193591A1 CN 2023082332 W CN2023082332 W CN 2023082332W WO 2023193591 A1 WO2023193591 A1 WO 2023193591A1
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Prior art keywords
layer
gate
signal line
semiconductor structure
electrically connected
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PCT/CN2023/082332
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English (en)
French (fr)
Inventor
范人士
郭朵
卜思童
方亦陈
丁士成
景蔚亮
谭万良
王正波
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华为技术有限公司
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Publication of WO2023193591A1 publication Critical patent/WO2023193591A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells

Definitions

  • the present application relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its preparation method, three-dimensional memory, and electronic equipment.
  • 3D memory also called three-dimensional memory
  • 3D memory also called three-dimensional memory
  • the above-mentioned three-dimensional memory also includes a peripheral circuit, and the peripheral circuit and the storage unit are arranged in different areas of the three-dimensional memory.
  • Peripheral circuits include metal-oxide-metal (MOM) capacitors. Based on this, how to reduce the area occupied by MOM capacitors and increase the area occupied by memory cells to improve the performance of three-dimensional memory Storage density has become an urgent problem to be solved in this field.
  • MOM metal-oxide-metal
  • Embodiments of the present application provide a semiconductor structure and a preparation method thereof, a three-dimensional memory, and an electronic device, aiming to improve the storage density of the three-dimensional memory.
  • a semiconductor structure including a wiring area.
  • the semiconductor structure includes a peripheral stack layer, a capacitor, a first contact pillar and a first signal line.
  • a peripheral stacked layer is provided in the wiring area.
  • the peripheral stacked layer includes a plurality of film layer pairs that are stacked.
  • the film layer pairs include a first dielectric layer and a gate layer.
  • the plurality of film layer pairs form Multiple steps.
  • the capacitor includes a first electrode and a second electrode.
  • the first contact pillar is located above the first target step, and one end is electrically connected to the gate layer in the pair of film layers forming the first target step, and the first target step is one step among the plurality of steps. .
  • the first signal line is electrically connected to the other end of the first contact post, the first signal line is configured to transmit a first voltage signal to the gate layer, and the gate layer is configured to form the the first electrode.
  • the semiconductor structure provided by the above embodiments of the present application uses a planar gate layer as the first electrode of the capacitor, which is conducive to increasing the capacitance value per unit area of the capacitor.
  • a planar gate layer as the first electrode of the capacitor, which is conducive to increasing the capacitance value per unit area of the capacitor.
  • It is beneficial to reduce the area of the capacitor that is, reduce the area occupied by the peripheral circuit, thereby reducing the area ratio of the wiring area and increasing the area ratio of the array area, thereby improving the storage capacity of the three-dimensional memory using this semiconductor structure. density.
  • the plurality of gate layers in the plurality of film layer pairs include a first gate layer and a second gate layer, and in a direction perpendicular to the plane of the peripheral stack layer, the first gate layer The gate electrode layers and the second gate electrode layers are alternately arranged.
  • the pair of film layers forming the first target step includes the first gate layer, the first gate layer is electrically connected to the first signal line through the first contact pillar, and the first gate layer Layers are configured to form the first electrode.
  • the first gate layer and the second gate layer are alternately arranged, and the first gate layer and the second gate layer are opposite to form a capacitor.
  • the first gate layer can form the first electrode of the capacitor.
  • the semiconductor structure further includes a second contact pillar and a second signal line
  • the second contact pillar is located above the second target step
  • the pair of film layers forming the second target step includes the second A gate layer
  • one end of the second contact pillar is electrically connected to the second gate layer
  • the second target step is one step among the plurality of steps.
  • the second signal line is electrically connected to the other end of the second contact post, the second signal line is configured to transmit a second voltage signal to the second gate layer, and the second gate layer is configured to form the second electrode.
  • the first gate layers and the second gate layers are alternately arranged, and the adjacent first gate layers and the second gate layers are arranged facing each other, so as to form a three-dimensional finger-like capacitor.
  • the first gate layer forms the first electrode of the capacitor
  • the second gate layer forms the second electrode of the capacitor
  • the first dielectric layer located between the first gate layer and the second gate layer serves as the dielectric of the capacitor.
  • the capacitance value per unit area of the capacitor is larger, and the design capacitance value of the capacitor is more accurate.
  • the semiconductor structure further includes a first protective layer covering the peripheral stack layer, and the first contact pillar and the second contact pillar respectively penetrate the first protective layer and the corresponding gate electrode. layer electrical connection.
  • the first protective layer by providing a first protective layer covering the peripheral stack layer, and subsequently forming a conductive pattern (for example, a first signal line and a second signal line) on the side of the first protective layer away from the peripheral stack layer, the first protective layer
  • the layer can be used to insulate the conductive pattern from the gate layer in the peripheral stack layer.
  • the first signal line and the second signal line are disposed on a side of the first protective layer away from the peripheral stack layer, and the first signal line and the second signal line are The lines are made of the same material and set on the same layer.
  • the first signal line and the second signal line are made of the same material and are arranged in the same layer, so that the first signal line and the second signal line can be formed simultaneously, which can simplify the process steps.
  • a plurality of second contact pillars electrically connected to a plurality of second gate layers are electrically connected to the same second signal line.
  • the same second signal line is used to transmit the second voltage signal to multiple second gate layers, which can achieve the effect of saving the number of wiring and reducing the area ratio of the wiring area.
  • the semiconductor structure further includes a conductive pillar and a third signal line.
  • the conductive pillar penetrates the plurality of film layer pairs of the peripheral stack layer and is connected to the center of the plurality of film layer pairs. Multiple gate layers are insulated.
  • a third signal line is electrically connected to the conductive pillar, the third signal line is configured to transmit a third voltage signal to the conductive pillar, and the conductive pillar is configured to form the second electrode.
  • the conductive pillars penetrate multiple film layer pairs of the peripheral stacked layer, that is, the conductive pillars penetrate the multiple gate layers, and the conductive pillars are insulated from the multiple gate layers to form a capacitor with a three-dimensional structure.
  • a plurality of gate layers form the first electrode of the capacitor, and the conductive pillar forms the second electrode of the capacitor.
  • a capacitance is generated between the conductive pillar and the plurality of gate layers.
  • the conductive pillars connect the gate layers in multiple film layer pairs in series, which can improve the structural strength of the peripheral stacked layers, thereby improving the structural strength of the semiconductor structure in the wiring area, which is beneficial to improving the uniformity of the structural strength of the semiconductor structure. sex.
  • the semiconductor structure further includes a second dielectric layer, the second dielectric layer is a cylindrical structure and penetrates the peripheral stack layer.
  • the second dielectric layer surrounds the conductive pillar.
  • the second dielectric layer can separate the conductive pillars from the plurality of gate electrode layers, thereby achieving insulation between the conductive pillars and the plurality of gate electrode layers.
  • the material of the second dielectric layer includes a ferroelectric material, and/or the dielectric constant of the second dielectric layer ranges from 25 to 35.
  • the dielectric constant of the second dielectric layer is relatively large.
  • Using the second dielectric layer as the dielectric layer of the capacitor can further increase the capacitance value per unit area of the capacitor, thereby helping to increase the storage density of the three-dimensional memory.
  • the semiconductor structure includes a plurality of conductive pillars, and the plurality of conductive pillars are arranged in an array.
  • the plurality of conductive pillars are electrically connected to the plurality of third signal lines, and the plurality of third signal lines are electrically connected on the same side of the peripheral stack layer.
  • the third voltage signal is transmitted to the plurality of conductive pillars through the plurality of third signal lines, and the plurality of conductive pillars form the second electrode of the capacitor, which is beneficial to increasing the design capacitance value of the capacitor.
  • the plurality of third signal lines are electrically connected on the same side of the peripheral stacking layer, so that the plurality of third signal lines can be connected in parallel, which can achieve the effect of saving the number of wiring and reducing the area ratio of the wiring area.
  • the semiconductor structure further includes a second protective layer covering the peripheral stack layer and a connection portion.
  • the connection part penetrates the second protective layer, and one end is electrically connected to the conductive pillar.
  • the third signal line is provided on a side of the second protective layer away from the peripheral stack layer, and the third signal line is electrically connected to the other end of the connecting part.
  • a second protective layer covering the peripheral stack layer is provided to form a third signal line on the side of the second protective layer away from the peripheral stack layer.
  • the second protective layer can realize the connection between the third signal line and the peripheral stack layer. Insulation of the gate layer.
  • the conductive pillar and the third signal line can be connected through the connecting portion.
  • the first signal line is disposed on a side of the second protective layer away from the peripheral stack layer, and the third signal line is made of the same material as the first signal line and is disposed in the same layer. .
  • the connecting portion is made of the same material as the first contact post.
  • the first signal line and the third signal line are made of the same material and are arranged in the same layer, so that the first signal line and the third signal line can be formed simultaneously, which can simplify the process steps.
  • the connecting portion and the first contact pillar are made of the same material, so that the connecting portion and the first contact pillar can be formed simultaneously, and the process steps can also be simplified.
  • a plurality of the first contact pillars electrically connected to a plurality of the gate layers are electrically connected to the same first signal line.
  • the same first signal line is used to transmit the first voltage signal to multiple gate layers, which can achieve the effect of saving the number of wiring and reducing the area ratio of the wiring area.
  • the semiconductor structure further includes an array area
  • the semiconductor structure further includes a memory stack layer disposed in the array area
  • the memory stack layer includes a plurality of memory cells arranged in an array.
  • the storage stack layer includes alternately arranged third dielectric layers and control gate layers.
  • the plurality of first dielectric layers of the peripheral stack layer correspond to the plurality of third dielectric layers of the storage stack layer.
  • the first dielectric layer and the third dielectric layer are made of the same material and are arranged in the same layer.
  • the plurality of gate electrode layers of the peripheral stack layer correspond to the plurality of control gate electrode layers of the storage stack layer.
  • the corresponding gate electrode layers and the control gate electrode layer are made of the same material and are arranged in the same layer, and are insulated from each other. .
  • the corresponding first dielectric layer and the third dielectric layer in the peripheral stack layer and the storage stack layer are made of the same material and are arranged in the same layer, that is, the first dielectric layer and the third dielectric layer are formed of the same film layer;
  • Stacking layers and storage The corresponding gate electrode layer and the control gate electrode layer in the storage stack are made of the same material and are arranged in the same layer, that is, the gate electrode layer and the control gate electrode layer are formed of the same film layer.
  • the formation steps of the peripheral stack layer are compatible with the formation steps of the storage stack layer, which is conducive to simplifying the preparation process; and the capacitor does not occupy other conductive layers, which is conducive to reducing the number of conductive layers in the wiring area, and can also reduce the number of conductive layers.
  • the area ratio of the wiring area is increased to increase the area ratio of the array area to increase the storage density of the three-dimensional memory; or the size of the three-dimensional memory is reduced by reducing the area of the wiring area.
  • a method for manufacturing a semiconductor structure includes a wiring region.
  • the preparation method includes: forming a peripheral stacked layer in the wiring area.
  • the peripheral stacked layer includes a plurality of film layer pairs arranged in a stack.
  • the film layer pairs include a first dielectric layer and a gate layer.
  • the plurality of film layer pairs include a first dielectric layer and a gate electrode layer.
  • the film layer pairs form multiple steps.
  • a first contact pillar is formed, the first contact pillar is located above the first target step, and one end is electrically connected to the gate layer in the middle of the film layer pair forming the first target step.
  • a first signal line is formed, the first signal line is electrically connected to the other end of the first contact post, the first signal line is configured to transmit a first voltage signal to the gate layer, the gate
  • the layer is configured to form a first electrode of the capacitor.
  • the preparation method provided by the above embodiments of the present application forms a peripheral stacked layer in the wiring area.
  • the peripheral stacked layer includes a plurality of film layer pairs arranged in a stack.
  • One film layer pair includes a first dielectric layer and a gate electrode layer.
  • the film layer pairs form multiple steps.
  • a first contact post is formed above the first target step, and one end of the first contact post is electrically connected to the gate layer in the pair of film layers forming the first target step.
  • a first signal line is formed, and the first signal line is electrically connected to the other end of the first contact post.
  • the first signal line is used to transmit a first voltage signal to the gate layer, and the gate layer can form the first electrode of the capacitor.
  • planar gate layer As the first electrode of the capacitor, it is beneficial to increase the capacitance value per unit area of the capacitor. On the basis that the capacitance value of the capacitor meets the design requirements, it is beneficial to reduce the area of the capacitor, that is, to reduce the peripheral area.
  • the area occupied by the circuit can thereby reduce the area ratio of the wiring area and increase the area ratio of the array area to increase the storage density of the three-dimensional memory using the semiconductor structure.
  • the plurality of gate layers in the plurality of film layer pairs include a first gate layer and a second gate layer, and in a direction perpendicular to the plane of the peripheral stack layer, the first gate layer The gate electrode layers and the second gate electrode layers are alternately arranged.
  • the forming the first contact pillar includes: forming the first contact pillar above the first target step, the film layer pair forming the first target step includes the first gate layer, and the first contact One end of the pillar is electrically connected to the first gate layer.
  • the preparation method further includes: during the process of forming the first contact pillar, simultaneously forming a second contact pillar, the second contact pillar being located above the second target step, and forming a film layer of the second target step.
  • the second gate electrode layer one end of the second contact pillar is electrically connected to the second gate electrode layer.
  • a second signal line is simultaneously formed, and the second signal line is electrically connected to the other end of the second contact post.
  • the first gate layer and the second gate layer are alternately formed, and the adjacent first gate layer and the second gate layer are arranged facing each other to form a three-dimensional interdigital-like capacitor.
  • the first gate layer forms the first electrode of the capacitor
  • the second gate layer forms the second electrode of the capacitor
  • the first dielectric layer located between the first gate layer and the second gate layer serves as the dielectric of the capacitor. layer, the capacitance value per unit area of the capacitor is larger, and the design capacitance value of the capacitor is more accurate.
  • the preparation method further includes: forming conductive holes that penetrate the plurality of film layer pairs of the peripheral stack layer. on the sidewall of the conductive hole A second dielectric layer is formed on the top. Conductive pillars are formed inside the second dielectric layer. During the process of forming the first signal line, a third signal line is formed simultaneously, and the third signal line is electrically connected to the conductive pillar.
  • conductive pillars are formed that penetrate multiple film layer pairs of the peripheral stacked layer, that is, conductive pillars are formed that penetrate multiple gate electrode layers, and the conductive pillars are insulated from the multiple gate electrode layers to form a three-dimensional structure. of capacitor.
  • a plurality of gate layers form the first electrode of the capacitor, and the conductive pillar forms a second electrode of the capacitor.
  • Capacitance is generated between the conductive pillar and the plurality of gate layers.
  • the semiconductor structure further includes an array region.
  • the preparation method further includes: during the process of forming a peripheral stack layer in the wiring area, simultaneously forming a storage stack layer in the array area.
  • the storage stack layer is also simultaneously formed in the array area. That is, the formation steps of the peripheral stack layer are compatible with the formation steps of the storage stack layer, which is beneficial to simplifying the preparation process.
  • a three-dimensional memory in a third aspect, includes the semiconductor structure described in any of the above embodiments.
  • a fourth aspect provides an electronic device, which includes a circuit board and the three-dimensional memory described in the above embodiment.
  • the three-dimensional memory is disposed on the circuit board and is electrically connected to the circuit.
  • Figure 1 is an architectural diagram of an electronic device according to some embodiments.
  • Figure 2 is an exploded view of an electronic device according to some embodiments.
  • Figure 3 is a top view of a three-dimensional memory according to some embodiments.
  • Figure 4 is an architectural diagram of a storage array of a three-dimensional memory according to some embodiments.
  • Figure 5 is a structural diagram of a capacitor in related art
  • Figure 6 is a partial enlarged view of a semiconductor structure at P1 in Figure 3;
  • Figure 7 is a perspective view of the semiconductor structure in Figure 6 at P2;
  • Figure 8 is a partial cross-sectional view of the semiconductor structure in Figure 6 along section line A-A';
  • Figure 9 is a partial cross-sectional view of the semiconductor structure in Figure 6 along section line B-B';
  • Figure 10 is a partial enlarged view of another semiconductor structure at P1 in Figure 3;
  • Figure 11 is a perspective view of the semiconductor structure in Figure 10 at P3;
  • Figure 12 is a partial cross-sectional view of the semiconductor structure in Figure 10 along section line C-C';
  • Figure 13A is a flow chart for preparing a semiconductor structure according to some embodiments.
  • Figure 13B is another flow diagram for preparing a semiconductor structure according to some embodiments.
  • Figure 13C is yet another flow diagram for preparing a semiconductor structure according to some embodiments.
  • Figure 14A is a diagram of steps for preparing an initial stack of layers according to some embodiments.
  • Figure 14B is a step diagram of preparing a peripheral stack layer according to some embodiments.
  • Figure 14C is a step diagram of preparing a first contact post according to some embodiments.
  • Figure 14D is a step diagram of preparing a second contact post according to some embodiments.
  • Figure 14E is a step diagram of preparing a first signal line according to some embodiments.
  • Figure 14F is a step diagram of preparing a second signal line according to some embodiments.
  • Figure 15A is a flow chart for preparing a semiconductor structure according to some embodiments.
  • Figure 15B is another flow diagram for preparing a semiconductor structure according to some embodiments.
  • Figure 16A is a diagram of steps for preparing an initial stack of layers according to some embodiments.
  • Figure 16B is a step diagram of preparing a peripheral stack layer according to some embodiments.
  • Figure 16C is a step diagram of preparing conductive holes according to some embodiments.
  • Figure 16D is a step diagram of preparing a second dielectric layer according to some embodiments.
  • Figure 16E is a step diagram of preparing conductive pillars and contacts according to some embodiments.
  • Figure 16F is a step diagram of preparing a first contact post and a connection portion according to some embodiments.
  • Figure 16G is a step diagram of preparing a first signal line and a third signal line according to some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of this application, unless otherwise specified, "plurality” means two or more.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • “same layer” refers to a layer structure formed by using the same film formation process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • Some embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, a tablet, a personal digital assistant (PDA), a television, a smart wearable product (such as , smart watches, smart bracelets), virtual reality (VR) terminal equipment, augmented reality (AR) terminal equipment, rechargeable small household appliances (such as soymilk machines, sweeping robots), drones,
  • a smart wearable product such as , smart watches, smart bracelets
  • VR virtual reality
  • AR augmented reality
  • rechargeable small household appliances such as soymilk machines, sweeping robots
  • drones Different types of user equipment or terminal equipment such as radar, aerospace equipment, and vehicle-mounted equipment; the electronic equipment can also be network equipment such as base stations.
  • the embodiments of the present application do not place any special restrictions on the specific form of the electronic device.
  • Figure 1 is an architectural diagram of an electronic device according to some embodiments.
  • the electronic device 1 includes: a storage device 11 , a processor 12 , an input device 13 , an output device 14 and other components.
  • a storage device 11 the electronic device 1 includes: a storage device 11 , a processor 12 , an input device 13 , an output device 14 and other components.
  • the architecture of the electronic device 1 shown in Figure 1 does not constitute a limitation on the electronic device 1, and the electronic device 1 may include more or less components than those shown in Figure 1 , or some of the components shown in Figure 1 may be combined, or may be arranged differently from the components shown in Figure 1 .
  • the storage device 11 is used to store software programs and modules.
  • the storage device 11 mainly includes a stored program area and a stored data area, wherein the stored program area can store an operating system and at least one application program required for a function. (such as sound playback function, image playback function, etc.), etc.; the storage data area can store data created according to the use of the electronic device 1 (such as audio data, image data, phone book, etc.), etc.
  • the storage device 11 includes an external memory 111 and an internal memory 112 . Data stored in the external memory 111 and the internal memory 112 can be transferred to each other.
  • the external memory 111 may include, for example, a hard disk, a USB disk, a floppy disk, etc.
  • the internal memory 112 may include, for example, Random Access Memory (RAM), Read-Only Memory (ROM), etc., where the random access memory may include, for example, Double Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate Synchronous Memory). Dynamic Random Access Memory (DDR SDRAM for short) is one of the mainstream internal memories.
  • RAM Random Access Memory
  • ROM Read-Only Memory
  • DDR SDRAM Dynamic Random Access Memory
  • the processor 12 is the control center of the electronic device 1, using various interfaces and lines to connect various parts of the entire electronic device 1, by running or executing software programs and/or modules stored in the storage device 11, and by calling the software programs and/or modules stored in the storage device 11.
  • the data in the device 11 executes various functions of the electronic device 1 and processes data, thereby overall monitoring the electronic device 1 .
  • the processor 12 may include one or more processing units.
  • the processor 12 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), etc. Among them, different processing units can be independent devices or integrated in one or more processors.
  • the processor 12 can integrate an application processor and a modem processor, where the application processor mainly processes operating systems, user interfaces, application programs, etc., and the modem processor mainly processes wireless communications. It can be understood that the above-mentioned modem processor may not be integrated into the processor 12 .
  • the above-mentioned application processor may be, for example, a central processing unit (CPU).
  • the processor 12 is a CPU as an example.
  • the CPU may include a calculator 121 and a controller 122 .
  • the arithmetic unit 121 obtains the data stored in the internal memory 112 and processes the data stored in the internal memory 112. The processed result is usually sent back to the internal memory 112.
  • the controller 122 can control the arithmetic unit 121 to process data, and the controller 122 can also control the external memory 111 and the internal memory 112 to store or read data.
  • the input device 13 is used to receive input numeric or character information and generate key signal input related to user settings and function control of the electronic device.
  • the input device 13 may include a touch screen and other input devices.
  • the touch screen also known as the touch panel, can collect the user's touch operations on or near the touch screen (such as the user's operations on or near the touch screen using fingers, stylus, or any suitable objects or accessories), and perform operations based on preset settings.
  • the program drives the corresponding connection device.
  • the controller 122 in the above-mentioned processor 12 can also control the input device 13 to receive the input signal or not to receive the input signal.
  • the input numeric or character information received by the input device 13 and the key signal input generated related to user settings and function control of the electronic device may be stored in the internal memory 112 .
  • the output device 14 is used to output the input of the input device 13 and store signals corresponding to the data in the internal memory 112 .
  • the output device 14 outputs a sound signal or a video signal.
  • the controller 122 in the above-mentioned processor 12 can also control the output device 14 to output a signal or not to output a signal.
  • the thick arrows in Figure 1 are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission.
  • a single arrow between the input device 13 and the internal memory 112 indicates that data received by the input device 13 is transmitted to the internal memory 112 .
  • the double arrow between the operator 121 and the internal memory 112 indicates that the data stored in the internal memory 112 can be transferred to the operator 121 , and the data processed by the operator 121 can be transferred to the internal memory 112 .
  • the thin arrows in Figure 1 indicate components that controller 122 can control.
  • the controller 122 can control the external memory 111, the internal memory 112, the operator 121, the input device 13 and the output device. Prepare 14 and so on for control.
  • the following is an exemplary introduction taking the electronic device 1 as a mobile phone.
  • Figure 2 is an exploded view of an electronic device according to some embodiments.
  • the electronic device 1 may also include a middle frame 15 , a rear case 16 and a display screen 17 .
  • the back shell 16 and the display screen 17 are respectively located on opposite sides of the middle frame 15 , and the middle frame 15 and the display screen 17 are disposed in the back shell 16 .
  • the middle frame 15 includes a bearing plate 150 for bearing the display screen 17 and a frame 151 surrounding the bearing plate 150 .
  • the electronic device 1 may further include a circuit board 18 , which is disposed on a side of the carrier plate 150 close to the rear case 16 . Some components in the electronic device 1 (such as the above-mentioned internal memory 112 ) may be disposed on On the circuit board 18, the internal memory 112 is electrically connected to the circuit board 18.
  • the internal memory 112 may include random access memory, read-only memory, etc., which are divided according to working principles.
  • the random access memory may also include ferroelectric memory (Ferroelectric Random Access Memory, FeRAM for short), phase change memory or magnetic memory.
  • FeRAM Feroelectric Random Access Memory
  • phase change memory FeRAM for short
  • ferroelectric memory has the characteristics of non-volatile data storage and fast access rate.
  • the following embodiments of this article take ferroelectric memory as an example for illustrative introduction.
  • FIG. 3 is a top view of a three-dimensional memory according to some embodiments
  • FIG. 4 is an architectural diagram of a storage array of a three-dimensional memory according to some embodiments.
  • the above-mentioned ferroelectric memory is a three-dimensional memory 10 with a three-dimensional structure.
  • the three-dimensional memory 10 extends in the X-Y plane.
  • the first direction X and the second direction Y are, for example, two normal directions in the plane where the three-dimensional memory 10 is located. intersection direction.
  • the third direction Z is perpendicular to the plane where the three-dimensional memory 10 is located, that is, perpendicular to the X-Y plane.
  • the three-dimensional memory 10 may include a semiconductor structure 100 and a source layer SL coupled to the semiconductor structure 100.
  • the semiconductor structure 100 is located above the source layer SL.
  • the above-mentioned source layer SL may include a semiconductor material.
  • the semiconductor material is, for example, single crystal silicon, single crystal germanium, III-V compound semiconductor material, II-VI compound semiconductor material, and other suitable semiconductor materials.
  • the source layer SL may be partially or fully doped.
  • the source layer SL may include a doped region doped with a p-type dopant.
  • the source layer SL may also include a non-doped region.
  • the semiconductor structure 100 includes an array area A1 and a routing area A2.
  • the semiconductor structure 100 may include a memory stack layer D disposed in the array area A1.
  • the memory stack layer D includes multiple arrays arranged in an array. storage unit U.
  • multiple memory cells U form a memory cell string 200.
  • the multiple memory cell strings 200 can form a memory array, and the source layer SL can be coupled with the sources of the multiple memory cell strings 200. catch.
  • the memory unit U may include one transistor T.
  • multiple transistors T are connected together to form the memory unit string 200 .
  • the transistor T is a ferroelectric field-effect transistor (FeFET for short), and the control electrode of the ferroelectric field-effect transistor is connected to the word line (WL 1 , WL 2 ...WL m- 1 , WL m ) is electrically connected, the source is electrically connected to the source layer SL, the drain is electrically connected to the bit lines (BL 1 , BL 2 ?? BL n-1 , BL n ), and the gate dielectric layer of the ferroelectric field effect transistor (also called ferroelectric layer) is a ferroelectric material.
  • the ferroelectric field effect transistor stores data by changing the polarity of the ferroelectric layer through voltage pulses, and obtains the stored data by reading the current of the transistor. Its reading mechanism is non-destructive and has a high density.
  • the number of transistors T in the memory cell string 200 in FIG. 4 is only illustrative. This application The memory cell string 200 of the three-dimensional memory 10 provided by the embodiment may also include other numbers of transistors T, such as 8, 16, 32, and 64.
  • the semiconductor structure 100 also includes a peripheral circuit provided in the wiring area A2 and an input/output terminal (Input/Output, referred to as I/O) 20.
  • the input/output terminal 20 can be used for electrical connection with the above-mentioned circuit board 18.
  • the peripheral circuit includes a MOM capacitor, and the MOM capacitor is one of the key components in the peripheral circuit.
  • MOM capacitor is one of the key components in the peripheral circuit.
  • a kind of MOM capacitor in the related technology is introduced below.
  • FIG. 5 is a structural diagram of a capacitor in the related art.
  • the semiconductor structure 100' includes a plurality of stacked conductive layers M', each conductive layer M' includes a plurality of electrode lines L', located between the edges of the electrode lines L' of the same conductive layer M' Capacitance can be generated. Based on this, interpolation capacitance can be generated through periodic interconnection between electrode lines L'.
  • the semiconductor structure 100' is a MOM capacitor.
  • the inventor of this application found through research that the above-mentioned MOM capacitor is made of multiple conductive layers M', and each conductive layer M' includes multiple electrode lines L'. Since the facing area between the electrode lines L' is relatively large, Small, making the capacitance value per unit area (along the X-Y plane) of the MOM capacitor small. In order to meet the design requirements for the capacitance value of the MOM capacitor, the area of the MOM capacitor (along the X-Y plane) needs to be set larger.
  • the area occupied by the MOM capacitor is larger, which will make the area occupied by the peripheral circuit larger, and thus the wiring area A2 will occupy a larger area in the three-dimensional memory 10.
  • the array area A1 occupies a smaller area in the three-dimensional memory 10, resulting in a smaller storage density of the three-dimensional memory 10.
  • Figure 6 is a partial enlarged view of a semiconductor structure in Figure 3 at P1;
  • Figure 7 is a partial enlargement of the semiconductor structure in Figure 6 at P2.
  • Figure 8 is a partial cross-sectional view of the semiconductor structure in Figure 6 along section line A-A';
  • Figure 9 is a partial cross-sectional view of the semiconductor structure in Figure 6 along section line B-B'.
  • the semiconductor structure 100 includes a peripheral stacked layer 101 disposed in the wiring area A2 .
  • the peripheral stacked layer 101 includes a plurality of film layer pairs P arranged in a stacked manner.
  • One film layer pair P includes a stacked arrangement.
  • the first dielectric layer 101a and the gate layer 101b, and the plurality of film layer pairs P form a plurality of steps S.
  • one film layer pair P forms a step S, and multiple film layer pairs P form multiple steps S.
  • One film layer pair P among the plurality of film layer pairs P can expose the step S of the film layer pair P located below it, so that the gate layer 101b at the step S of the film layer pair P can be connected to an external signal line.
  • the memory stack layer D provided in the array area A1 mentioned above includes alternately arranged third dielectric layers and control gate layers, and the plurality of first dielectric layers 101a of the peripheral stack layer 101 and the storage
  • the plurality of third dielectric layers of the stacked layer D correspond one to one, and the corresponding first dielectric layer 101a and the third dielectric layer are made of the same material and are arranged in the same layer.
  • the plurality of gate layers 101b of the peripheral stack layer 101 correspond to the plurality of control gate layers of the storage stack layer D.
  • the corresponding gate layers 101b and the control gate layers are made of the same material and are arranged in the same layer.
  • the materials of the first dielectric layer 101a and the third dielectric layer may both include silicon dioxide, and the materials of the gate layer 101b and the control gate layer may both include tungsten, and embodiments of the present application are not limited thereto.
  • the storage stack layer D of this application is provided in the array area A1, and the peripheral stack layer 101 is provided in the wiring area A2.
  • the peripheral stack layer 101 and the storage stack layer D are provided in different areas, and they are discontinuous. That is, the gate layer 101b of the peripheral stack layer 101 and the control gate layer of the storage stack layer D are insulated from each other.
  • the semiconductor structure 100 also includes a capacitor (first capacitor), which includes a first electrode and a second electrode.
  • first capacitor which includes a first electrode and a second electrode.
  • the structure of the capacitor will be introduced below with reference to FIGS. 7 and 8 .
  • the semiconductor structure 100 includes a first contact pillar 102 and a first signal line 103 .
  • the first contact post 102 is located above the first target step S1, and one end of the first contact post 102 is electrically connected to the gate layer 101b in the layer pair P forming the first target step S1.
  • first target step S1 is a step S among a plurality of steps S, for example, a gate layer 101b to which each first contact pillar 102 is to be connected, and the film layer in which the gate layer 101b is located.
  • first target step S1 for P.
  • the first signal line 103 is electrically connected to the other end of the first contact post 102 .
  • the first signal line 103 is configured to transmit a first voltage signal to the gate layer 101b, which is configured to form a first electrode of the capacitor.
  • the semiconductor structure 100 compared to linear capacitors, uses a planar gate layer 101b as the first electrode of the capacitor, which is beneficial to increasing the unit size of the capacitor.
  • the capacitance value of the area (along the X-Y plane), on the basis that the capacitance value of the capacitor meets the design requirements, is conducive to reducing the area of the capacitor (along the X-Y plane), that is, reducing the area occupied by the peripheral circuit, thereby reducing the routing
  • the area ratio of the line area A2 increases the area ratio of the array area A1 to increase the storage density of the three-dimensional memory 10 using the semiconductor structure 100 .
  • the corresponding first dielectric layer 101a and the third dielectric layer in the peripheral stack layer 101 and the storage stack layer D are made of the same material and are arranged in the same layer, that is, the first dielectric layer 101a and the third dielectric layer are formed of the same film layer.
  • the corresponding gate layer 101b in the peripheral stack layer 101 and the storage stack layer D is made of the same material as the control gate layer and is arranged in the same layer, that is, the gate layer 101b and the control gate layer are formed of the same film layer.
  • the formation steps of the peripheral stack layer 101 are compatible with the formation steps of the storage stack layer D, which is beneficial to simplifying the preparation process; and the capacitor does not occupy other conductive layers, which is beneficial to reducing the number of conductive layers in the wiring area A2.
  • the area ratio of the wiring area A2 can be reduced and the area ratio of the array area A1 can be increased to increase the storage density of the three-dimensional memory 10; or the size of the three-dimensional memory 10 can be reduced by reducing the area of the wiring area A2.
  • the plurality of gate layers 101b in the plurality of film layer pairs P includes a first gate layer G1 and a second gate layer G2, and is stacked vertically to the peripheral layer.
  • the first gate layer G1 and the second gate layer G2 are alternately arranged, and the first gate layer G1 and the second gate layer G2 face each other in the third direction Z. to form a capacitor.
  • the film layer pair P where each first gate layer G1 is located forms a "first target step S1".
  • the first gate layer G1 is electrically connected to the first signal line 103 through the first contact pillar 102, The first voltage signal is transmitted to the first gate layer G1 through the first signal line 103, and the first gate layer G1 may form the first electrode of the capacitor.
  • the semiconductor structure 100 further includes a second contact pillar 104 and a second signal line 105 .
  • the second contact post 104 is located above the second target step S2, and one end of the second contact post 104 is electrically connected to the gate layer 101b in the layer pair P forming the second target step S2.
  • the "second target step S2" is a step S among a plurality of steps S, for example, a gate layer 101b to which each second contact pillar 104 is to be connected, and the film layer where the gate layer 101b is located. Form a "second target step S2" for P.
  • the film layer pair P where each second gate layer G2 is located forms a "second target step S2", that is, the One end of the two contact pillars 104 is electrically connected to the second gate layer G2.
  • the second signal line 105 is electrically connected to the other end of the second contact post 104 .
  • the second signal line 105 is configured to transmit a second voltage signal to the second gate layer.
  • the second gate layer G2 is configured to form a third capacitor. Two electrodes.
  • the first gate layer G1 and the second gate layer G2 are alternately arranged in the third direction Z, and the adjacent first gate layer G1 and the second gate layer G2 are arranged facing each other, so that Forming a three-dimensional finger-like capacitor.
  • the first gate layer G1 forms the first electrode of the capacitor
  • the second gate layer G2 forms the second electrode of the capacitor
  • the first dielectric layer 101a located between the first gate layer G1 and the second gate layer G2
  • the capacitor formed by the planar first gate layer G1 and the second gate layer G2 has a higher structural strength of the peripheral stack layer 101, which is beneficial to Improving the structural strength of the semiconductor structure 100 in the wiring area A2 is beneficial to improving the uniformity of the structural strength of the semiconductor structure 100 .
  • the material of the first dielectric layer 101a may include silicon dioxide, the dielectric constant of which is 3.9, and embodiments of the present application are not limited thereto.
  • the semiconductor structure 100 further includes a first protective layer 106 covering the peripheral stack layer 101 , and the first contact pillar 102 and the second contact pillar 104 respectively penetrate the first protective layer 106 electrically connected to the corresponding gate layer 101b.
  • the first protective layer 106 By disposing the first protective layer 106 covering the peripheral stack layer 101, and subsequently forming a conductive pattern (for example, the first signal line 103 and the second signal line 105) on the side of the first protective layer 106 away from the peripheral stack layer 101, the first The protective layer 106 can achieve insulation between the conductive pattern and the gate layer 101b in the peripheral stack layer 101 .
  • a conductive pattern for example, the first signal line 103 and the second signal line 105
  • first contact pillar 102 and the second contact pillar 104 respectively penetrate the first protective layer 106 and are electrically connected to the corresponding gate layer 101b, that is, the first contact pillar 102 and the second contact pillar 104 can be connected in the same step. form.
  • a first contact hole and a second contact hole may be formed in the first protective layer 106, and the first contact hole and the second contact hole respectively expose the corresponding gate layer 101b.
  • the same deposition process may be used to form the first contact hole in the first protective layer 106.
  • Conductive material is deposited in the contact hole and the second contact hole to form the first contact pillar 102 and the second contact pillar 104.
  • the material of the first contact pillar 102 and the second contact pillar 104 may be the same.
  • the first signal line 103 and the second signal line 105 are disposed on a side of the first protective layer 106 away from the peripheral stack layer 101 , and the first signal line 103 and the second signal line 105 are The signal lines 105 are made of the same material and are arranged in the same layer, so that the first signal line 103 and the second signal line 105 can be formed simultaneously, which can simplify the process steps.
  • a plurality of first contact pillars 102 electrically connected to a plurality of gate layers 101b are electrically connected to the same first signal line 103 .
  • Using the same first signal line 103 to transmit the first voltage signal to multiple gate layers 101b can achieve the effect of saving the number of wiring and reducing the area ratio of the wiring area A2.
  • the plurality of second contact pillars 104 electrically connected to the plurality of gate layers 101b are electrically connected to the same second signal line 105, and the same second signal can be used.
  • the line 105 transmits the second voltage signal through the plurality of second contact posts 104 to the plurality of gate layers 101b, which form the second electrodes of the capacitor.
  • the design capacitance value of the capacitor depends on the number of layers of the gate layer 101b (first gate layer G1) that receives the first voltage signal, the number of gate layers 101b (second gate layer G1) that receives the second voltage signal.
  • Layer G2) Number the facing area of the first gate layer G1 and the second gate layer G2 is proportional to each other. Therefore, the number of gate layers 101b that receive the first voltage signal can be adjusted by adjusting the wiring method of the gate layer 101b.
  • the design capacitance value of the capacitor is adjusted by adjusting the number of gate layers 101b that receive the second voltage signal and/or by adjusting the facing area of the first gate layer G1 and the second gate layer G2.
  • the inventor of the present application studied the above-mentioned capacitor and found that, as shown in FIG. 7 , along the third direction Z, the opposite part between the two adjacent gate layers 101b will generate a facing capacitance, and, except for the uppermost gate Outside the layer 101b, any gate layer 101b at the step S will generate an edge capacitance between it and the gate layer 101b above it.
  • the design capacitance value of this capacitor is equal to the sum of the facing capacitance and the edge capacitance.
  • the edge capacitance Capacitance affects the accuracy of the capacitor's designed capacitance value.
  • the dimensions of the multiple gate layers 101 b along the first direction X can be set larger to increase the number of adjacent gate layers 101 b.
  • the facing area between them increases the proportion of the facing capacitance in the design capacitance value and reduces the proportion of the edge capacitance in the design capacitance value, thereby reducing the influence of the edge capacitance on the accuracy of the design capacitance value of the capacitor.
  • Figure 10 is a partial enlarged view of another semiconductor structure in Figure 3 at P1;
  • Figure 11 is a perspective view of the semiconductor structure in Figure 10 at P3;
  • Figure 12 is a partial cross-sectional view of the semiconductor structure in FIG. 10 along the section line C-C'.
  • the semiconductor structure 100 includes a peripheral stacked layer 101 disposed in the wiring area A2 .
  • the peripheral stacked layer 101 includes a plurality of film layer pairs P in a stacked arrangement.
  • One film layer pair P includes a stacked arrangement.
  • the first dielectric layer 101a and the gate layer 101b, and the plurality of film layer pairs P form a plurality of steps S.
  • the plurality of first dielectric layers 101a of the peripheral stack layer 101 also correspond to the plurality of third dielectric layers of the storage stack layer D.
  • the materials of the corresponding first dielectric layers 101a and the third dielectric layer Same and same layer settings.
  • the multiple gate layers 101b of the peripheral stack layer 101 also correspond to the multiple control gate layers of the storage stack layer D.
  • the corresponding gate layers 101b are made of the same material as the control gate layer and are arranged in the same layer, and Insulated from each other.
  • the materials of the first dielectric layer 101a and the third dielectric layer may both include silicon dioxide, and the materials of the gate layer 101b and the control gate layer may both include tungsten, and embodiments of the present application are not limited thereto.
  • the semiconductor structure 100 also includes a capacitor (second capacitor), which includes a first electrode and a second electrode.
  • a capacitor second capacitor
  • the structure of the capacitor will be introduced below with reference to FIGS. 11 and 12 .
  • the semiconductor structure 100 includes a first contact pillar 102 and a first signal line 103 .
  • the first contact post 102 is located above the first target step S1, and one end of the first contact post 102 is electrically connected to the gate layer 101b in the layer pair P forming the first target step S1.
  • first target step S1 is a step S among a plurality of steps S, for example, a gate layer 101b to which each first contact pillar 102 is to be connected, and the film layer in which the gate layer 101b is located.
  • first target step S1 for P.
  • the first signal line 103 is electrically connected to the other end of the first contact post 102 .
  • the first signal line 103 is configured to transmit a first voltage signal to the gate layer 101b, which is configured to form a first electrode of the capacitor.
  • the plurality of gate electrode layers 101b included in the plurality of film layer pairs P are all electrically connected to the first signal line 103 through the first contact pillar 102 , that is, the plurality of gate electrode layers Layers 101b each form the first electrode of the capacitor.
  • the semiconductor structure 100 provided by the above embodiments of the present application adopts a planar gate layer 101b as the
  • the first electrode of the capacitor is conducive to increasing the capacitance value per unit area of the capacitor (along the XY plane).
  • it is conducive to reducing the area of the capacitor (along the XY plane), that is, reducing The area occupied by the peripheral circuits thereby reduces the area ratio of the wiring area A2, increases the area ratio of the array area A1, and improves the storage density of the three-dimensional memory 10.
  • the corresponding first dielectric layer 101a and the third dielectric layer in the peripheral stack layer 101 and the storage stack layer D are made of the same material and are arranged in the same layer, that is, the first dielectric layer 101a and the third dielectric layer are formed of the same film layer.
  • the corresponding gate layer 101b in the peripheral stack layer 101 and the storage stack layer D is made of the same material as the control gate layer and is arranged in the same layer, that is, the gate layer 101b and the control gate layer are formed of the same film layer.
  • the formation steps of the peripheral stack layer 101 are compatible with the formation steps of the storage stack layer D, which is beneficial to simplifying the preparation process; and the capacitor does not occupy other conductive layers, which is beneficial to reducing the number of conductive layers in the wiring area A2.
  • the area ratio of the wiring area A2 can be reduced and the area ratio of the array area A1 can be increased to increase the storage density of the three-dimensional memory 10; or the size of the three-dimensional memory 10 can be reduced by reducing the area of the wiring area A2.
  • the semiconductor structure 100 further includes a conductive pillar 107 and a third signal line 108 .
  • the conductive pillars 107 penetrate through the plurality of film layer pairs P of the peripheral stacked layer 101, and the conductive pillars 107 are insulated from the plurality of gate electrode layers 101b in the plurality of film layer pairs P.
  • the conductive pillars 107 penetrate all the film layer pairs P in the peripheral stack layer 101 , and the conductive pillars 107 are not disposed at the step S.
  • the material of the conductive pillar 107 may include tungsten, and embodiments of the present application are not limited thereto.
  • the third signal line 108 is electrically connected to the conductive post 107, the third signal line 108 is configured to transmit a third voltage signal to the conductive post 107, and the conductive post 107 is configured to form a second electrode of the capacitor.
  • the conductive pillars 107 penetrate through the plurality of film layer pairs P of the peripheral stack layer 101, that is, along the third direction Z, the conductive pillars 107 penetrate through the plurality of gate electrode layers 101b, and the conductive pillars 107 are connected with the plurality of gate electrode layers 101b.
  • the electrode layers 101b are insulated to form a capacitor with a three-dimensional structure.
  • the plurality of gate layers 101b form the first electrode of the capacitor, and the conductive pillars 107 form the second electrode of the capacitor. Capacitance is generated between the conductive pillars 107 and the plurality of gate layers 101b.
  • the structure can increase the capacitance value of the capacitor along its thickness direction (the third direction Z), thereby increasing the capacitance value per unit area (along the X-Y plane) of the capacitor, which is beneficial to improving the storage density of the three-dimensional memory 10 .
  • the semiconductor structure 100 is provided with a dummy memory array (dummy) in the wiring area A2.
  • the dummy memory array is used to improve the structural strength of the semiconductor structure 100 in the wiring area A2, and the dummy The storage array does not require external signal lines to receive voltage signals.
  • the virtual memory array is replaced with conductive pillars 107.
  • the conductive pillars 107 can be used to form the second electrode of the capacitor and to connect the gate layers 101b in the multiple film layer pairs P in series. , can improve the structural strength of the peripheral stack layer 101, thereby improving the structural strength of the semiconductor structure 100 in the wiring area A2, which is beneficial to improving the uniformity of the structural strength of the semiconductor structure 100.
  • the capacitor is designed with a high capacitance value and can be used as a filter capacitor.
  • the semiconductor structure 100 further includes a second dielectric layer 109 , the second dielectric layer 109 is a cylindrical structure, and the second dielectric layer 109 penetrates the peripheral stack layer 101 and surrounds it. Conductive pillars 107 are provided.
  • the second dielectric layer 109 can separate the conductive pillar 107 from the plurality of gate layers 101b, thereby realizing the conductive pillar 107 and insulation between multiple gate layers 101b.
  • the material of the second dielectric layer 109 may include ferroelectric material.
  • the material of the second dielectric layer 109 may include Hafnium Zirconium Oxide (HZO).
  • HZO Hafnium Zirconium Oxide
  • the dielectric constant of the second dielectric layer 109 ranges from 25 to 35.
  • the dielectric constant of the second dielectric layer 109 is 25, 28, 30, 32 or 35.
  • the dielectric constant of the second dielectric layer 109 is relatively large. Using the second dielectric layer 109 as the dielectric layer of the capacitor can further increase the capacitance value per unit area (along the X-Y plane) of the capacitor, thereby helping to improve the performance of the three-dimensional memory 10 Storage density.
  • the semiconductor structure 100 further includes a second protective layer 110 and a connection CT.
  • the second protective layer 110 covers the peripheral stack layer 101 , the connection portion CT penetrates the second protective layer 110 , and one end of the connection portion CT is electrically connected to the conductive pillar 107 .
  • the second protective layer 110 By disposing the second protective layer 110 covering the peripheral stack layer 101 to form the third signal line 108 on the side of the second protective layer 110 away from the peripheral stack layer 101, the second protective layer 110 can realize the connection between the third signal line 108 and the peripheral stack layer 101. Insulation of the gate layer 101b in the stacked layer 101.
  • the third signal line 108 is disposed on the side of the second protective layer 110 away from the peripheral stack layer 101 .
  • the third signal line 108 is electrically connected to the other end of the connection part CT to connect the conductive pillar through the connection part CT. 107 and the third signal line 108 are connected.
  • the first signal line 103 is also disposed on the side of the second protective layer 110 away from the peripheral stack layer 101 , and the third signal line 108 and the first signal line 103 are made of the same material.
  • the layers are arranged so that the first signal line 103 and the third signal line 108 can be formed simultaneously, which can simplify the process steps.
  • connection portion CT and the first contact pillar 102 are made of the same material, so that the connection portion CT and the first contact pillar 102 can be formed simultaneously, and the process steps can also be simplified.
  • connection portion CT penetrates the second protective layer 110 and is electrically connected to the conductive pillar 107
  • first contact pillar 102 also penetrates the second protective layer 110 and is electrically connected to the gate layer 101b
  • the connection portion CT and the first contact pillar 102 can be formed in the same step.
  • a first contact hole and a third contact hole may be formed in the first protective layer 106, the first contact hole exposes the gate layer 101b, and the third contact hole exposes the conductive pillar 107.
  • the same deposition process may be used to Conductive material is deposited in the first contact hole and the third contact hole to form the first contact pillar 102 and the connection portion CT.
  • a plurality of first contact pillars 102 electrically connected to a plurality of gate layers 101b are electrically connected to the same first signal line 103 .
  • Using the same first signal line 103 to transmit the first voltage signal to multiple gate layers 101b can achieve the effect of saving the number of wiring and reducing the area ratio of the wiring area A2.
  • the semiconductor structure 100 includes a plurality of conductive pillars 107 arranged in an array.
  • the row direction of the plurality of conductive pillars 107 arranged in an array is the first direction X
  • the column direction is the second direction Y.
  • the plurality of conductive pillars 107 include 6 rows and 6 columns, and a total of 36 conductive pillars are Examples are used for illustration, and the embodiments of the present application are not limited thereto.
  • the plurality of conductive pillars 107 are electrically connected to the plurality of third signal lines 108 , and the plurality of third signal lines 108 are electrically connected on the same side of the peripheral stack layer 101 .
  • the third voltage signal is transmitted to the plurality of conductive pillars 107 through the plurality of third signal lines 108.
  • the plurality of conductive pillars 107 form the second electrode of the capacitor, which is beneficial to increasing the design capacitance value of the capacitor.
  • the plurality of third signal lines 108 are electrically connected on the same side of the peripheral stack layer 101, so that the plurality of third signal lines 108 can be connected in parallel, which can save the number of wiring and reduce the area occupied by the wiring area A2. The effect of comparison.
  • the design capacitance value of the capacitor depends on the number of conductive pillars 107 and the effective number of gate layers 101b penetrated by the conductive pillars 107 (the "effective number of layers” refers to: the number of gate layers connected to the first signal line 103
  • the number of gate layers 101b) can be adjusted, the number of conductive pillars 107 and/or the effective number of gate layers 101b penetrated by the conductive pillars 107 can be adjusted, the design capacitance value of the capacitor, and the length, width and length of the capacitor can be adjusted. height to meet the design requirements of wiring area A2 and the area requirements of the layout.
  • the above embodiments of the present application provide structural designs of two capacitors.
  • the inventor of the present application conducted simulation tests on the capacitance values per unit area of the two capacitors and obtained the following results (see Table 1 below). It can be understood that the above embodiments of the present application include but are not limited to the above two structural designs of capacitors.
  • the “capacitance value per unit area” refers to the capacitance value per 100nm 2 of the capacitor along the XY plane; the “edge capacitance” refers to the sum of the capacitances generated by the 11 steps S included in the capacitor, and
  • the size of the step S along the first direction X is 600 nm, and the size along the second direction Y is 2880 nm.
  • the design capacitance value of the first capacitor is equal to the product of the capacitance value per unit area of the first capacitor and the area;
  • the design capacitance value of the second capacitor is equal to the product of the capacitance value per unit area of the second capacitor and the area. , plus the edge capacitance of the second capacitor.
  • FIG. 13A is a flow chart for preparing a semiconductor structure according to some embodiments
  • FIG. 13B is another flow chart for preparing a semiconductor structure according to some embodiments.
  • Figure 13C is another flow chart for preparing a semiconductor structure according to some embodiments
  • Figure 14A is a step diagram for preparing an initial stacked layer according to some embodiments
  • Figure 14B is a step diagram for preparing a peripheral stacked layer according to some embodiments
  • Figure 14C is a step diagram of preparing a first contact post according to some embodiments
  • Figure 14D is a step diagram of preparing a second contact post according to some embodiments
  • Figure 14E is a step diagram of preparing a first signal line according to some embodiments Figure
  • Figure 14F is a step diagram of preparing a second signal line according to some embodiments.
  • the preparation method includes the following S10 ⁇ S30:
  • FIGS. 14A and Figure 14B form a peripheral stacked layer 101 in the wiring area A2.
  • the peripheral stacked layer 101 includes a plurality of stacked film layer pairs P, and one film layer pair P includes a stacked first dielectric.
  • layer 101a and gate layer 101b, and multiple film layer pairs P form multiple steps S.
  • the above S10 may include the following steps:
  • an initial stacked layer 101' is formed in the wiring area A2.
  • the initial stacked layer 101' includes a plurality of film layer pairs P that are stacked.
  • One film layer pair P includes a stacked first dielectric layer 101a and Gate layer 101b.
  • multiple film layer pairs P of the initial stacked layer 101 ′ are etched to form multiple steps S to obtain the peripheral stacked layer 101 .
  • the storage stack layer D is also simultaneously formed in the array area A1.
  • the first contact pillar 102 is formed.
  • the first contact pillar 102 is located above the first target step S1, and one end of the first contact pillar 102 is in contact with the film layer forming the first target step S1.
  • the gate layer 101b in is electrically connected.
  • the plurality of gate layers 101b in the plurality of film layer pairs P include a first gate layer G1 and a second gate layer G2, along a direction perpendicular to the plane of the peripheral stack layer 101 (ie, the third direction Z), the first gate layer G1 and the second gate layer G2 are alternately arranged.
  • the above S20 may include the following S201:
  • a first contact post 102 is formed above the first target step S1.
  • the film pair P forming the first target step S1 includes the first gate layer G1.
  • One end of the first contact post 102 is connected to the first gate layer G1.
  • the first gate layer G1 is electrically connected.
  • the preparation method also includes the following steps:
  • the second contact pillar 104 is also formed simultaneously.
  • the second contact pillar 104 is located above the second target step S2 and forms a film of the second target step S2.
  • the layer pair P includes a second gate layer G2, and one end of the second contact pillar 104 is electrically connected to the second gate layer G2.
  • a first signal line 103 is formed.
  • the first signal line 103 is electrically connected to the other end of the first contact pillar 102.
  • the first signal line 103 is configured to connect to the gate layer 101b (the first gate layer 101b).
  • the gate layer 101b (first gate layer G1) transmits the first voltage signal, and the gate layer 101b (first gate layer G1) is configured to form a first electrode of the capacitor.
  • the preparation method also includes the following steps:
  • a second signal line 105 is also formed simultaneously.
  • the second signal line 105 is electrically connected to the other end of the second contact post 104.
  • the second signal line 105 Configured to transmit the second voltage signal to the second gate layer G2, the second gate layer G2 is configured to form the first electrode of the capacitor.
  • the storage stack layer D is also simultaneously formed in the array area A1, that is, the formation steps of the peripheral stack layer 101 are compatible with the storage stack.
  • the formation steps of layer D are conducive to simplifying the preparation process.
  • the same patterning process can be used, for example, the same photolithography process can be used to form the peripheral stack layer 101 and the storage stack layer D using the same photo mask. There is no need to add additional photo masks, which can simplify the preparation process and reduce the cost of the preparation process. cost.
  • the first gate layer G1 and the second gate layer G2 are alternately formed, and the adjacent first gate layer G1 and the second gate layer G2 are arranged facing each other to form a three-dimensional quasi-gate electrode layer. Insert finger-shaped capacitor.
  • the first gate layer G1 forms the first electrode of the capacitor
  • the second gate layer G2 forms the second electrode of the capacitor
  • the first dielectric layer 101a located between the first gate layer G1 and the second gate layer G2
  • forming a planar first gate layer G1 and a second gate layer G2 is beneficial to increasing the capacitance value per unit area of the capacitor, and the structural strength of the peripheral stack layer 101 is higher. , which is conducive to improving the structural strength of the semiconductor structure 100 in the wiring area A2, thereby being conducive to improving the uniformity of the structural strength of the semiconductor structure 100.
  • Figure 15A is a flow chart for preparing a semiconductor structure according to some embodiments
  • Figure 15B is another flow chart for preparing a semiconductor structure according to some embodiments.
  • Figure 16A is a step diagram of preparing an initial stacked layer according to some embodiments
  • Figure 16B is a step diagram of preparing a peripheral stacked layer according to some embodiments
  • Figure 16C is a step diagram of preparing conductive holes according to some embodiments.
  • Figure 16D is a step diagram of preparing a second dielectric layer according to some embodiments
  • Figure 16E is a step diagram of preparing conductive pillars and contacts according to some embodiments
  • Figure 16F is a step diagram of preparing a first contact according to some embodiments Step diagram of pillars and connections
  • Figure 16G is a step diagram of preparing a first signal line and a third signal line according to some embodiments.
  • the preparation method includes the following steps S10' to S30':
  • a peripheral stacked layer 101 is formed in the wiring area A2.
  • the peripheral stacked layer 101 includes a plurality of film layer pairs P that are stacked.
  • One film layer pair P includes a first layer that is stacked.
  • the dielectric layer 101a and the gate layer 101b, and multiple film layer pairs P form multiple steps S.
  • the above S10' may include the following steps:
  • an initial stacked layer 101' is formed in the wiring area A2.
  • the initial stacked layer 101' includes a plurality of film layer pairs P that are stacked.
  • One film layer pair P includes a stacked first dielectric layer 101a and Gate layer 101b.
  • multiple film layer pairs P of the initial stacked layer 101 ′ are etched to form multiple steps S to obtain the peripheral stacked layer 101 .
  • the storage stack layer D is also simultaneously formed in the array area A1.
  • the preparation method also includes the following S11' ⁇ S13':
  • a conductive hole H1 is formed, and the conductive hole H1 penetrates the plurality of film layer pairs P of the peripheral stack layer 101.
  • the conductive hole H1 penetrates all the film layer pairs P in the peripheral stack layer 101, and the conductive hole H1 is not provided at the step S.
  • a second dielectric layer 109 is formed on the side wall of the conductive hole H1.
  • conductive pillars 107 are formed inside the second dielectric layer 109.
  • a conductive material can be deposited on the inside of the second dielectric layer 109 to form the conductive pillar 107, and the conductive material can be deposited on the top of the conductive pillar 107 to form a contact portion C connected to the conductive pillar 107.
  • the contact portion C The radial size of should be larger than the radial size of the conductive pillar 107 so that the subsequently formed connecting portion can be aligned and connected with the contact portion C, thereby achieving electrical connection between the connecting portion and the conductive pillar 107 .
  • a first contact pillar 102 is formed.
  • the first contact pillar 102 is located above the first target step S1, and one end of the first contact pillar 102 is opposite to the film layer forming the first target step S1.
  • the gate layer 101b in P is electrically connected.
  • the plurality of gate layers 101b included in the plurality of film layer pairs P are all electrically connected to the first contact pillar 102 .
  • connection portion CT is also simultaneously formed, and the connection portion CT is connected to the contact portion C located on the top of the conductive pillar 107 to realize the connection between the connection portion CT and the conductive pillar 107 electrical connection.
  • a first signal line 103 is formed.
  • the first signal line 103 is electrically connected to the other end of the first contact post 102.
  • the first signal line 103 is configured to transmit the first signal line 103 to the gate layer 101b.
  • voltage signal, the gate layer 101b is configured to form a first electrode of the capacitor.
  • the preparation method also includes the following steps:
  • the third signal line 108 is also formed simultaneously.
  • the third signal line 108 is electrically connected to the conductive pillar 107.
  • the third signal line 108 can be electrically connected to the conductive pillar 107 through the connection part CT and the contact part C.
  • the third signal line 108 is configured to transmit the third voltage signal to the conductive post 107 configured to form the second electrode of the capacitor.
  • the storage stack layer D is also simultaneously formed in the array area A1, that is, the formation steps of the peripheral stack layer 101 are compatible with the storage stack.
  • the formation steps of layer D are conducive to simplifying the preparation process.
  • the same patterning process can be used, for example, the same photolithography process can be used to form the peripheral stack layer 101 and the storage stack layer D using the same photo mask. There is no need to add additional photo masks, which can simplify the preparation process and reduce the cost of the preparation process. cost.
  • conductive pillars 107 are formed through the plurality of film layer pairs P of the peripheral stacked layer 101, that is, along the third direction Z, conductive pillars 107 are formed through the plurality of gate electrode layers 101b, and the conductive pillars 107 and the plurality of gate electrode layers are 101b are insulated to form a capacitor with a three-dimensional structure.
  • the plurality of gate layers 101b form the first electrode of the capacitor, and the conductive pillars 107 form the second electrode of the capacitor.
  • Capacitance is generated between the conductive pillars 107 and the plurality of gate layers 101b.
  • the conductive pillar 107 can be used to form the second electrode of the capacitor, and can also connect the gate layers 101b in the multiple film layer pairs P in series, which can improve the structural strength of the peripheral stacked layer 101, thereby improving
  • the structural strength of the semiconductor structure 100 in the wiring area A2 is conducive to improving the uniformity of the structural strength of the semiconductor structure 100 .
  • the above embodiments of the present application provide two methods for preparing semiconductor structures. It can be understood that the above embodiments of the present application include but are not limited to the above two preparation methods.

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Abstract

本申请提供了一种半导体结构及其制备方法、三维存储器、电子设备，涉及半导体芯片技术领域，旨在如何提高三维存储器的存储密度。该半导体结构包括外围堆叠层、电容器、第一接触柱和第一信号线，外围堆叠层包括层叠设置的多个膜层对，膜层对包括第一介质层和栅极层，多个膜层对形成多个台阶。电容器包括第一电极和第二电极。第一接触柱位于第一目标台阶的上方，且一端与形成第一目标台阶的膜层对中的栅极层电连接，第一目标台阶为多个台阶中的一个台阶。第一信号线与第一接触柱的另一端电连接，第一信号线被配置为向栅极层传输第一电压信号，栅极层被配置为形成第一电极。上述半导体结构应用于三维存储器中，以实现数据的读取和写入操作。

Description

半导体结构及其制备方法、三维存储器、电子设备
本申请要求于2022年04月06日提交国家知识产权局、申请号为202210357044.4、申请名称为“半导体结构及其制备方法、三维存储器、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体芯片技术领域，尤其涉及一种半导体结构及其制备方法、三维存储器、电子设备。
背景技术
随着存储单元的特征尺寸接近工艺下限，平面工艺和制造技术变得具有挑战性且成本高昂，这造成2D存储器的存储密度接近上限。
为克服2D存储器带来的限制，业界已经研发了具有三维结构的存储器(3D存储器，也称作三维存储器)，通过膜层的堆叠、微缩器件关键尺寸来提高存储密度。
上述三维存储器还包括外围电路，该外围电路与存储单元设置于三维存储器的不同区域。外围电路中包括金属-氧化物-金属(Metal-Oxide-Metal，简称MOM)电容器，基于此，如何减小MOM电容器所占区域的面积，增加存储单元所占区域的面积，以提高三维存储器的存储密度，成为本领域亟待解决的问题。
发明内容
本申请实施例提供一种半导体结构及其制备方法、三维存储器、电子设备，旨在如何提高三维存储器的存储密度。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种半导体结构，包括走线区。该半导体结构包括外围堆叠层、电容器、第一接触柱和第一信号线。其中，外围堆叠层设置于所述走线区，该外围堆叠层包括层叠设置的多个膜层对，所述膜层对包括第一介质层和栅极层，所述多个膜层对形成多个台阶。电容器包括第一电极和第二电极。第一接触柱位于第一目标台阶的上方，且一端与形成所述第一目标台阶的膜层对中的栅极层电连接，所述第一目标台阶为所述多个台阶中的一个台阶。所述第一信号线与所述第一接触柱的另一端电连接，所述第一信号线被配置为向所述栅极层传输第一电压信号，所述栅极层被配置为形成所述第一电极。
本申请的上述实施例所提供的半导体结构，通过采用面状的栅极层作为电容器的第一电极，有利于增加电容器的单位面积的电容值，在电容器的容值满足设计要求的基础上，有利于减小电容器的面积，即减小外围电路所占区域的面积，从而减小走线区的面积占比，增大阵列区的面积占比，以提高应用该半导体结构的三维存储器的存储密度。
在一些实施例中，所述多个膜层对中的多个栅极层包括第一栅极层和第二栅极层，沿垂直于所述外围堆叠层所在平面的方向，所述第一栅极层和所述第二栅极层交替设置。形成所述第一目标台阶的膜层对包括所述第一栅极层，所述第一栅极层通过所述第一接触柱与所述第一信号线电连接，所述第一栅极层被配置为形成所述第一电极。
上述实施例中，通过第一栅极层与第二栅极层交替设置，第一栅极层与第二栅极层正对以形成电容器，第一栅极层可形成电容器的第一电极。
在一些实施例中，所述半导体结构还包括第二接触柱和第二信号线，第二接触柱位于第二目标台阶的上方，形成所述第二目标台阶的膜层对包括所述第二栅极层，所述第二接触柱的一端与所述第二栅极层电连接，所述第二目标台阶为所述多个台阶中的一个台阶。所述第二信号线与所述第二接触柱的另一端电连接，所述第二信号线被配置为向所述第二栅极层传输第二电压信号，所述第二栅极层被配置为形成所述第二电极。
上述实施例中，第一栅极层和第二栅极层交替设置，相邻的第一栅极层与第二栅极层正对设置，以形成三维的类插指状的电容器。第一栅极层形成该电容器的第一电极，第二栅极层形成该电容器的第二电极，位于第一栅极层与第二栅极层之间的第一介质层作为该电容器的介质层，该电容器的单位面积的电容值较大，且电容器的设计电容值的精度较高。
在一些实施例中，所述半导体结构还包括覆盖所述外围堆叠层的第一保护层，所述第一接触柱和所述第二接触柱分别贯穿所述第一保护层与对应的栅极层电连接。
上述实施例中，通过设置覆盖外围堆叠层的第一保护层，后续在第一保护层远离外围堆叠层的一侧形成导电图案(例如，第一信号线和第二信号线)，第一保护层可实现导电图案与外围堆叠层中的栅极层的绝缘。
在一些实施例中，所述第一信号线和所述第二信号线设置于所述第一保护层远离所述外围堆叠层的一侧，且所述第一信号线与所述第二信号线的材料相同且同层设置。
上述实施例中，第一信号线与第二信号线的材料相同且同层设置，使得第一信号线和第二信号线可同步形成，可简化工艺步骤。
在一些实施例中，与多个所述第二栅极层电连接的多个所述第二接触柱，与同一条第二信号线电连接。
上述实施例中，采用同一条第二信号线向多个第二栅极层传输第二电压信号，可达到节省走线数量，减小走线区的面积占比的效果。
在一些实施例中，所述半导体结构还包括导电柱和第三信号线，所述导电柱贯穿所述外围堆叠层的所述多个膜层对，且与所述多个膜层对中的多个栅极层绝缘。第三信号线与所述导电柱电连接，所述第三信号线被配置为向所述导电柱传输第三电压信号，所述导电柱被配置为形成所述第二电极。
上述实施例中，通过导电柱贯穿外围堆叠层的多个膜层对，即导电柱贯穿多个栅极层，且导电柱与多个栅极层之间绝缘，以形成具有三维结构的电容器。多个栅极层形成该电容器的第一电极，导电柱形成该电容器的第二电极，导电柱与多个栅极层之间产生电容，通过将电容器由二维结构变为三维结构，可增加电容器沿其厚度方向的电容值，从而可增加电容器单位面积的电容值，有利于提高三维存储器的存储密度。并且，导电柱将多个膜层对中的栅极层串接起来，可提高外围堆叠层的结构强度，从而提高半导体结构在走线区的结构强度，有利于提高半导体结构的结构强度的均一性。
在一些实施例中，所述半导体结构还包括第二介质层，所述第二介质层为筒状结构，且贯穿所述外围堆叠层。所述第二介质层围绕所述导电柱。
上述实施例中，第二介质层可将导电柱与多个栅极层隔开，实现了导电柱与多个栅极层之间的绝缘。
在一些实施例中，所述第二介质层的材料包括铁电材料，和/或，所述第二介质层的介电常数的范围为25～35。
上述实施例中，第二介质层的介电常数较大，采用该第二介质层作为电容器的介质层，可进一步增加电容器的单位面积的电容值，从而有利于提高三维存储器的存储密度。
在一些实施例中，所述半导体结构包括多个所述导电柱，多个所述导电柱阵列式排布。多个所述导电柱与多条所述第三信号线电连接，多条所述第三信号线在所述外围堆叠层的同一侧电连接。
上述实施例中，通过多条第三信号线向多个导电柱传输第三电压信号，多个导电柱形成电容器的第二电极，有利于增大电容器的设计电容值。并且，多条第三信号线在外围堆叠层的同一侧电连接，以便于将多条第三信号线并联起来，这样可以达到节省走线数量，减小走线区的面积占比的效果。
在一些实施例中，所述半导体结构还包括第二保护层和连接部，第二保护层覆盖所述外围堆叠层。连接部贯穿所述第二保护层，且一端与所述导电柱电连接。其中，所述第三信号线设置于所述第二保护层远离所述外围堆叠层的一侧，所述第三信号线与所述连接部的另一端电连接。
上述实施例中，通过设置覆盖外围堆叠层的第二保护层，以在第二保护层远离外围堆叠层的一侧形成第三信号线，第二保护层可实现第三信号线与外围堆叠层中的栅极层的绝缘。并且，通过连接部可将导电柱和第三信号线连接起来。
在一些实施例中，所述第一信号线设置于所述第二保护层远离所述外围堆叠层的一侧，所述第三信号线与所述第一信号线的材料相同且同层设置。所述连接部与所述第一接触柱的材料相同。
上述实施例中，第一信号线与第三信号线的材料相同且同层设置，使得第一信号线和第三信号线可同步形成，可简化工艺步骤。并且，连接部与第一接触柱的材料相同，使得连接部和第一接触柱可同步形成，也可简化工艺步骤。
在一些实施例中，与多个所述栅极层电连接的多个所述第一接触柱，与同一条第一信号线电连接。
上述实施例中，采用同一条第一信号线向多个栅极层传输第一电压信号，可达到节省走线数量，减小走线区的面积占比的效果。
在一些实施例中，所述半导体结构还包括阵列区，所述半导体结构还包括设置于所述阵列区的存储堆叠层，所述存储堆叠层包括阵列式排布的多个存储单元。所述存储堆叠层包括交替设置的第三介质层和控制栅极层，所述外围堆叠层的多个第一介质层与所述存储堆叠层的多个第三介质层一一对应，相对应的第一介质层与第三介质层的材料相同且同层设置。所述外围堆叠层的多个栅极层与所述存储堆叠层的多个控制栅极层一一对应，相对应的栅极层与控制栅极层的材料相同且同层设置，且相互绝缘。
上述实施例中，外围堆叠层和存储堆叠层中相对应的第一介质层与第三介质层的材料相同且同层设置，即第一介质层和第三介质层由同一膜层形成；外围堆叠层和存 储堆叠层中相对应的栅极层与控制栅极层的材料相同且同层设置，即栅极层和控制栅极层由同一膜层形成。也就是说，外围堆叠层的形成步骤兼容于存储堆叠层的形成步骤，有利于简化制备工艺；且电容器不占用其它导电层，有利于减少导电层在走线区的设置数量，也可减小走线区的面积占比，增大阵列区的面积占比，以提高三维存储器的存储密度；或通过减小走线区的面积，减小三维存储器的尺寸。
第二方面，提供了一种半导体结构的制备方法，该制备方法所应用的半导体结构包括走线区。该制备方法包括：在所述走线区形成外围堆叠层，所述外围堆叠层包括层叠设置的多个膜层对，所述膜层对包括第一介质层和栅极层，所述多个膜层对形成多个台阶。形成第一接触柱，所述第一接触柱位于第一目标台阶的上方，且一端与形成所述第一目标台阶的膜层对中的栅极层电连接。形成第一信号线，所述第一信号线与所述第一接触柱的另一端电连接，所述第一信号线被配置为向所述栅极层传输第一电压信号，所述栅极层被配置为形成电容器的第一电极。
本申请的上述实施例所提供的制备方法，在走线区形成外围堆叠层，该外围堆叠层包括层叠设置的多个膜层对，一个膜层对包括第一介质层和栅极层，多个膜层对形成多个台阶。在第一目标台阶的上方形成第一接触柱，且第一接触柱的一端与形成第一目标台阶的膜层对中的栅极层电连接。形成第一信号线，该第一信号线与第一接触柱的另一端电连接，第一信号线用于向栅极层传输第一电压信号，栅极层可形成电容器的第一电极。
通过形成面状的栅极层作为电容器的第一电极，有利于增加电容器的单位面积的电容值，在电容器的容值满足设计要求的基础上，有利于减小电容器的面积，即减小外围电路所占区域的面积，从而减小走线区的面积占比，增大阵列区的面积占比，以提高应用该半导体结构的三维存储器的存储密度。
在一些实施例中，所述多个膜层对中的多个栅极层包括第一栅极层和第二栅极层，沿垂直于所述外围堆叠层所在平面的方向，所述第一栅极层和所述第二栅极层交替设置。所述形成第一接触柱，包括：在所述第一目标台阶的上方形成第一接触柱，形成所述第一目标台阶的膜层对包括所述第一栅极层，所述第一接触柱的一端与所述第一栅极层电连接。
所述制备方法还包括：在所述形成第一接触柱的过程中，同步形成第二接触柱，所述第二接触柱位于第二目标台阶的上方，形成所述第二目标台阶的膜层对包括所述第二栅极层，所述第二接触柱的一端与所述第二栅极层电连接。在所述形成第一信号线的过程中，同步形成第二信号线，所述第二信号线与所述第二接触柱的另一端电连接。
上述实施例中，交替形成第一栅极层和第二栅极层，相邻的第一栅极层与第二栅极层正对设置，以形成三维的类插指状的电容器。第一栅极层形成该电容器的第一电极，第二栅极层形成该电容器的第二电极，位于第一栅极层与第二栅极层之间的第一介质层作为该电容器的介质层，该电容器的单位面积的电容值较大，且电容器的设计电容值的精度较高。
在一些实施例中，在所述走线区形成外围堆叠层之后，所述制备方法还包括：形成导电孔，所述导电孔贯穿所述外围堆叠层的所述多个膜层对。在所述导电孔的侧壁 上形成第二介质层。在所述第二介质层的内侧形成导电柱。在所述形成第一信号线的过程中，同步形成第三信号线，所述第三信号线与所述导电柱电连接。
上述实施例中，形成贯穿外围堆叠层的多个膜层对的导电柱，即形成贯穿多个栅极层的导电柱，且导电柱与多个栅极层之间绝缘，以形成具有三维结构的电容器。多个栅极层形成该电容器的第一电极，导电柱形成该电容器的第二电极，导电柱与多个栅极层之间产生电容，通过增加电容器沿其厚度方向的电容值，可增加电容器沿其延展面的单位面积的电容值，从而有利于提高三维存储器的存储密度。
在一些实施例中，所述半导体结构还包括阵列区。所述制备方法还包括：在所述走线区形成外围堆叠层的过程中，在所述阵列区同步形成存储堆叠层。
上述实施例中，在走线区形成外围堆叠层的过程中，还在阵列区同步形成存储堆叠层，即外围堆叠层的形成步骤兼容于存储堆叠层的形成步骤，有利于简化制备工艺。
第三方面，提供了一种三维存储器，该三维存储器包括上述任一实施例所述的半导体结构。
第四方面，提供了一种电子设备，该电子设备包括电路板和上述实施例所述的三维存储器。所述三维存储器设置于所述电路板上，且与所述电路电连接。
可以理解地，本公开的上述实施例提供的三维存储器及电子设备，其所能达到的有益效果可参考上文中半导体结构的有益效果，此处不再赘述。
附图说明
为了更清楚地说明本申请中的技术方案，下面将对本申请一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本申请实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的电子设备的架构图；
图2为根据一些实施例的电子设备的爆炸图；
图3为根据一些实施例的三维存储器的俯视图；
图4为根据一些实施例的三维存储器的存储阵列的架构图；
图5为相关技术中的电容器的结构图；
图6为图3中的一种半导体结构在P1处的局部放大图；
图7为图6中的半导体结构在P2处的立体图；
图8为图6中的半导体结构沿剖面线A-A＇的局部剖视图；
图9为图6中的半导体结构沿剖面线B-B＇的局部剖视图；
图10为图3中的另一种半导体结构在P1处的局部放大图；
图11为图10中的半导体结构在P3处的立体图；
图12为图10中的半导体结构沿剖面线C-C＇的局部剖视图；
图13A为根据一些实施例的制备半导体结构的一种流程图；
图13B为根据一些实施例的制备半导体结构的另一种流程图；
图13C为根据一些实施例的制备半导体结构的又一种流程图；
图14A为根据一些实施例的制备初始堆叠层的步骤图；
图14B为根据一些实施例的制备外围堆叠层的步骤图；
图14C为根据一些实施例的制备第一接触柱的步骤图；
图14D为根据一些实施例的制备第二接触柱的步骤图；
图14E为根据一些实施例的制备第一信号线的步骤图；
图14F为根据一些实施例的制备第二信号线的步骤图；
图15A为根据一些实施例的制备半导体结构的一种流程图；
图15B为根据一些实施例的制备半导体结构的另一种流程图；
图16A为根据一些实施例的制备初始堆叠层的步骤图；
图16B为根据一些实施例的制备外围堆叠层的步骤图；
图16C为根据一些实施例的制备导电孔的步骤图；
图16D为根据一些实施例的制备第二介质层的步骤图；
图16E为根据一些实施例的制备导电柱和接触部的步骤图；
图16F为根据一些实施例的制备第一接触柱和连接部的步骤图；
图16G为根据一些实施例的制备第一信号线和第三信号线的步骤图。
具体实施方式
下面将结合附图，对本申请一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例性地”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”也可能指两个或两个以 上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所申请的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
在本申请的内容中，“在……上”、“上方”、和“之上”的含义应当以最宽泛的方式解释，使得“在...上”不仅意味着“直接在某物上”，而且还包括其间具有中间特征或层的“在某物上”的含义，并且“上方”或“之上”不仅意味着在某物“上方”或“之上”，还包括其间没有中间特征或层的在某物“上方”或“之上”的含义(即，直接在某物上)。
在本申请的内容中，“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本申请的一些实施例提供了一种电子设备，该电子设备例如可以为手机(mobile phone)、平板电脑(pad)、个人数字助理(personal digital assistant，简称PDA)、电视、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，简称VR)终端设备、增强现实(augmented reality，简称AR)终端设备、充电家用小型电器(例如豆浆机、扫地机器人)、无人机、雷达、航空航天设备和车载设备等不同类型的用户设备或者终端设备；该电子设备还可以为基站等网络设备。本申请的实施例对电子设备的具体形式不作特殊限制。
图1为根据一些实施例的电子设备的架构图。
如图1所示，电子设备1包括：存储装置11、处理器12、输入设备13、输出设备14等部件。本领域技术人员可以理解到，图1中示出的电子设备1的架构并不构成对该电子设备1的限定，该电子设备1可以包括比如图1所示的部件更多或更少的部件，或者可以组合如图1所示的部件中的某些部件，或者可以与如图1所示的部件布置不同。
其中，存储装置11用于存储软件程序以及模块。存储装置11主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序 (比如声音播放功能、图像播放功能等)等；存储数据区可存储根据电子设备1的使用所创建的数据(比如音频数据、图像数据、电话本等)等。此外，存储装置11包括外存储器111和内存储器112。外存储器111和内存储器112存储的数据可以相互传输。外存储器111例如可以包括硬盘、U盘、软盘等。内存储器112例如可以包括随机存储器(Random Access Memory，简称RAM)、只读存储器(Read-Only Memory，简称ROM)等，其中，随机存储器例如可包括双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory，简称DDR SDRAM)，其为主流的内存储器之一。
处理器12是该电子设备1的控制中心，利用各种接口和线路连接整个电子设备1的各个部分，通过运行或执行存储在存储装置11内的软件程序和/或模块，以及调用存储在存储装置11内的数据，执行电子设备1的各种功能和处理数据，从而对电子设备1进行整体监控。可选的，处理器12可以包括一个或多个处理单元。例如，处理器12可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。例如，处理器12可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器12中。上述的应用处理器例如可以为中央处理器(central processing unit，CPU)。图1中以处理器12为CPU为例，CPU可以包括运算器121和控制器122。运算器121获取内存储器112存储的数据，并对内存储器112存储的数据进行处理，处理后的结果通常送回内存储器112。控制器122可以控制运算器121对数据进行处理，控制器122还可以控制外存储器置111和内存储器112存储数据或读取数据。
输入设备13用于接收输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入。示例的，输入设备13可以包括触摸屏以及其他输入设备。触摸屏，也称为触摸面板，可收集用户在触摸屏上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触摸屏上或在触摸屏附近的操作)，并根据预先设定的程式驱动相应的连接装置。上述处理器12中的控制器122还可以控制输入设备13接收输入的信号或不接收输入的信号。此外，输入设备13接收到的输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入可以存储在内存储器112中。
输出设备14用于输出输入设备13的输入，并存储在内存储器112中的数据对应的信号。例如，输出设备14输出声音信号或视频信号。上述处理器12中的控制器122还可以控制输出设备14输出信号或不输出信号。
需要说明的是，图1中的粗箭头用于表示数据的传输，粗箭头的方向表示数据传输的方向。例如，输入设备13和内存储器112之间的单箭头表示输入设备13接收到的数据向内存储器112传输。又例如，运算器121和内存储器112之间的双箭头表示内存储器112存储的数据可以向运算器121传输，且运算器121处理后的数据可以向内存储器112传输。图1中的细箭头表示控制器122可以控制的部件。示例性地，控制器122可以对外存储器置111、内存储器112、运算器121、输入设备13和输出设 备14等进行控制。
为了方便进一步对电子设备1的结构进行说明，以下以电子设备1为手机为例进行示例性介绍。
图2为根据一些实施例的电子设备的爆炸图。
参见图2，电子设备1还可以包括中框15、后壳16以及显示屏17。后壳16和显示屏17分别位于中框15的相对两侧，且中框15和显示屏17设置于后壳16内。中框15包括用于承载显示屏17的承载板150，以及绕承载板150一周的边框151。
继续参见图2，电子设备1还可以包括电路板18，该电路板18设置于承载板150的靠近后壳16的一侧，电子设备1中的一些部件(例如上述内存储器112)可以设置于电路板18上，内存储器112与电路板18电连接。
根据前文所述，内存储器112可以包括随机存储器、只读存储器等，按照工作原理进行划分，随机存储器还可以包括铁电存储器(Ferroelectric Random Access Memory，简称FeRAM)、相变存储器或磁性存储器。其中，铁电存储器具有存储数据非易失性，且存取速率快的特点，本文的以下实施例以铁电存储器为例进行示例性介绍。
图3为根据一些实施例的三维存储器的俯视图；图4为根据一些实施例的三维存储器的存储阵列的架构图。
参见图3和图4，上述铁电存储器为具有三维结构的三维存储器10，三维存储器10在X-Y平面中延伸，第一方向X和第二方向Y例如是三维存储器10所在平面中的两个正交方向。第三方向Z垂直于三维存储器10所在平面，即垂直于X-Y平面。
继续参见图3和图4，三维存储器10可以包括半导体结构100，及与半导体结构100耦接的源极层SL，例如，沿第三方向Z，半导体结构100位于源极层SL的上方。
需要说明的是，上述源极层SL可以包括半导体材料，半导体材料例如为单晶硅、单晶锗、III-V族化合物半导体材料、II-VI族化合物半导体材料以及其他合适的半导体材料。源极层SL可以部分或全部被掺杂。示例性地，源极层SL可以包括掺杂区，掺杂区由p型掺杂剂掺杂。源极层SL还可以包括非掺杂区。
再次参见图3和图4，半导体结构100包括阵列区A1和走线区A2，该半导体结构100可包括设置于阵列区A1的存储堆叠层D，该存储堆叠层D包括阵列式排布的多个存储单元U。沿第三方向Z，多个存储单元U形成一个存储单元串200，在X-Y平面中，多个存储单元串200可形成存储阵列，源极层SL可以与多个存储单元串200的源极耦接。
具体地，参见图4，存储单元U可以包括一个晶体管T，沿第三方向Z，多个晶体管T连接在一起形成了存储单元串200。
示例性地，如图4所示，晶体管T为铁电场效应晶体管(Ferroelectric Field-Effect Transistor，简称FeFET)，该铁电场效应晶体管的控制极与字线(WL1、WL2……WLm-1、WLm)电连接，源极与源极层SL电连接，漏极与位线(BL1、BL2……BLn-1、BLn)电连接，铁电场效应晶体管的栅介质层(也可以称为铁电层)的材料为铁电材料。铁电场效应晶体管通过电压脉冲改变铁电层的极性存储数据，并通过读取晶体管的电流来得到存储数据，其读取机制为非破坏性，并具有较高的密度。
需要说明的是，图4中存储单元串200的晶体管T的数目仅是示意性的，本申请 实施例提供的三维存储器10的存储单元串200还可以包括其他数量的晶体管T，例如8、16、32、64。
半导体结构100还包括设置于走线区A2的外围电路、及输入/输出端(Input/Output，简称I/O)20，输入/输出端20可用于与上述的电路板18电连接。
其中，外围电路中包括MOM电容器，MOM电容器为外围电路中的关键器件之一，下面介绍相关技术中的一种MOM电容器。
图5为相关技术中的电容器的结构图。
如图5所示，半导体结构100＇包括堆叠设置的多个导电层M＇，每个导电层M＇包括多条电极线L＇，位于同一导电层M＇的电极线L＇的边沿之间可产生电容，基于此，通过电极线L＇之间周期性互连可产生插值电容，半导体结构100＇即为MOM电容器。
本申请的发明人经研究发现，上述MOM电容器采用多个导电层M＇制备而成，且每个导电层M＇包括多条电极线L＇，由于电极线L＇之间的正对面积较小，使得MOM电容器的单位面积(沿X-Y平面)的电容值较小，为满足对MOM电容器的容值的设计要求，需要将MOM电容器的面积(沿X-Y平面)设置较大。
但是，结合图3，在X-Y平面中，MOM电容器所占区域的面积较大，会使外围电路所占区域的面积较大，进而使走线区A2在三维存储器10中的面积占比较大，相应地，使阵列区A1在三维存储器10中的面积占比较小，导致三维存储器10的存储密度较小。
为解决上述问题，本申请的一些实施例提供了一种半导体结构，图6为图3中的一种半导体结构在P1处的局部放大图；图7为图6中的半导体结构在P2处的立体图；图8为图6中的半导体结构沿剖面线A-A＇的局部剖视图；图9为图6中的半导体结构沿剖面线B-B＇的局部剖视图。
参见图6、图7和图8，半导体结构100包括设置于走线区A2的外围堆叠层101，该外围堆叠层101包括层叠设置的多个膜层对P，一个膜层对P包括层叠设置的第一介质层101a和栅极层101b，且多个膜层对P形成多个台阶S。
需要说明的是，沿第三方向Z，一个膜层对P形成一个台阶S，多个膜层对P形成多个台阶S。多个膜层对P中的一个膜层对P，可露出位于其下方的膜层对P的台阶S，以便于膜层对P的台阶S处的栅极层101b外接信号线。
并且，前文提到的设置于阵列区A1的存储堆叠层D，该存储堆叠层D包括交替设置的第三介质层和控制栅极层，外围堆叠层101的多个第一介质层101a与存储堆叠层D的多个第三介质层一一对应，相对应的第一介质层101a与第三介质层的材料相同且同层设置。外围堆叠层101的多个栅极层101b与存储堆叠层D的多个控制栅极层一一对应，相对应的栅极层101b与控制栅极层的材料相同且同层设置。例如，第一介质层101a与第三介质层的材料可均包括二氧化硅，栅极层101b与控制栅极层的材料可均包括钨，本申请的实施例不限于此。
例如，本申请的存储堆叠层D设置于阵列区A1，外围堆叠层101设置于走线区A2，外围堆叠层101与存储堆叠层D设置于不同的区域，二者之间是不连续的，即外围堆叠层101的栅极层101b与存储堆叠层D的控制栅极层之间相互绝缘。
半导体结构100还包括电容器(第一电容器)，该电容器包括第一电极和第二电极，下面结合图7和图8对该电容器的结构进行介绍。
如图7和图8所示，半导体结构100包括第一接触柱102和第一信号线103。
其中，第一接触柱102位于第一目标台阶S1的上方，第一接触柱102的一端与形成第一目标台阶S1的膜层对P中的栅极层101b电连接。
需要说明的是，“第一目标台阶S1”为多个台阶S中的一个台阶S，例如，每个第一接触柱102所要连接的一个栅极层101b，该栅极层101b所在的膜层对P形成一个“第一目标台阶S1”。
第一信号线103与第一接触柱102的另一端电连接。第一信号线103被配置为向栅极层101b传输第一电压信号，栅极层101b被配置为形成电容器的第一电极。
本申请的上述实施例所提供的半导体结构100，结合图5和图7，相较于线状的电容器，通过采用面状的栅极层101b作为电容器的第一电极，有利于增加电容器的单位面积(沿X-Y平面)的电容值，在电容器的容值满足设计要求的基础上，有利于减小电容器的面积(沿X-Y平面)，即减小外围电路所占区域的面积，从而减小走线区A2的面积占比，增大阵列区A1的面积占比，以提高应用该半导体结构100的三维存储器10的存储密度。
并且，外围堆叠层101和存储堆叠层D中相对应的第一介质层101a与第三介质层的材料相同且同层设置，即第一介质层101a和第三介质层由同一膜层形成。外围堆叠层101和存储堆叠层D中相对应的栅极层101b与控制栅极层的材料相同且同层设置，即栅极层101b和控制栅极层由同一膜层形成。也就是说，外围堆叠层101的形成步骤兼容于存储堆叠层D的形成步骤，有利于简化制备工艺；并且，电容器不占用其它导电层，有利于减少导电层在走线区A2的设置数量，可减小走线区A2的面积占比，增大阵列区A1的面积占比，以提高三维存储器10的存储密度；或通过减小走线区A2的面积，减小三维存储器10的尺寸。
在一些实施例中，如图7和图8所示，多个膜层对P中的多个栅极层101b包括第一栅极层G1和第二栅极层G2，沿垂直于外围堆叠层101所在平面的方向(即第三方向Z)，第一栅极层G1和第二栅极层G2交替设置，第一栅极层G1与第二栅极层G2在第三方向Z上正对以形成电容器。
并且，每个第一栅极层G1所在的膜层对P形成一个“第一目标台阶S1”，基于此，第一栅极层G1通过第一接触柱102与第一信号线103电连接，通过第一信号线103向第一栅极层G1传输第一电压信号，第一栅极层G1可形成电容器的第一电极。
在一些实施例中，如图7和图9所示，半导体结构100还包括第二接触柱104和第二信号线105。
其中，第二接触柱104位于第二目标台阶S2的上方，第二接触柱104的一端与形成第二目标台阶S2的膜层对P中的栅极层101b电连接。
需要说明的是，“第二目标台阶S2”为多个台阶S中的一个台阶S，例如，每个第二接触柱104所要连接的一个栅极层101b，该栅极层101b所在的膜层对P形成一个“第二目标台阶S2”。
并且，每个第二栅极层G2所在的膜层对P形成一个“第二目标台阶S2”，即第 二接触柱104的一端与第二栅极层G2电连接。
第二信号线105与第二接触柱104的另一端电连接，第二信号线105被配置为向第二栅极层传输第二电压信号，第二栅极层G2被配置为形成电容器的第二电极。
本申请的上述实施例，在第三方向Z上第一栅极层G1和第二栅极层G2交替设置，相邻的第一栅极层G1与第二栅极层G2正对设置，以形成三维的类插指状的电容器。第一栅极层G1形成该电容器的第一电极，第二栅极层G2形成该电容器的第二电极，位于第一栅极层G1与第二栅极层G2之间的第一介质层101a作为该电容器的介质层，该电容器的单位面积的电容值较大，且电容器的设计电容值的精度较高。
并且，结合图5和图7，相较于线状的电容器，面状的第一栅极层G1和第二栅极层G2所形成的电容器，外围堆叠层101的结构强度较高，有利于提高半导体结构100在走线区A2的结构强度，从而有利于提高半导体结构100的结构强度的均一性。
示例性地，第一介质层101a的材料可包括二氧化硅，其介电常数为3.9，本申请的实施例不限于此。
在一些实施例中，如图8和图9所示，半导体结构100还包括覆盖外围堆叠层101的第一保护层106，第一接触柱102和第二接触柱104分别贯穿第一保护层106与对应的栅极层101b电连接。
通过设置覆盖外围堆叠层101的第一保护层106，后续在第一保护层106远离外围堆叠层101的一侧形成导电图案(例如，第一信号线103和第二信号线105)，第一保护层106可实现导电图案与外围堆叠层101中的栅极层101b的绝缘。
可以理解的是，第一接触柱102和第二接触柱104分别贯穿第一保护层106与对应的栅极层101b电连接，即第一接触柱102和第二接触柱104可在同一步骤下形成。例如，可在第一保护层106中形成第一接触孔和第二接触孔，第一接触孔和第二接触孔分别暴露对应的栅极层101b，然后，可采用同一沉积工艺，在第一接触孔和第二接触孔内沉积导电材料，形成第一接触柱102和第二接触柱104，第一接触柱102和第二接触柱104的材料可以是相同的。
在一些实施例中，如图8和图9所示，第一信号线103和第二信号线105设置于第一保护层106远离外围堆叠层101的一侧，第一信号线103与第二信号线105的材料相同且同层设置，使得第一信号线103和第二信号线105可同步形成，可简化工艺步骤。
在一些实施例中，如图7所示，与多个栅极层101b(多个第一栅极层G1)电连接的多个第一接触柱102，与同一条第一信号线103电连接。采用同一条第一信号线103向多个栅极层101b传输第一电压信号，可达到节省走线数量，减小走线区A2的面积占比的效果。
如图7所示，与多个栅极层101b(第二栅极层G2)电连接的多个第二接触柱104，与同一条第二信号线105电连接，可采用同一条第二信号线105通过多个第二接触柱104向多个栅极层101b传输第二电压信号，该多个栅极层101b形成电容器的第二电极。
本申请的上述实施例，电容器的设计电容值与接收第一电压信号的栅极层101b(第一栅极层G1)的层数、接收第二电压信号的栅极层101b(第二栅极层G2)的层 数、第一栅极层G1与第二栅极层G2的正对面积成正比，因此，可通过调整栅极层101b的接线方式来调整接收第一电压信号的栅极层101b的层数、接收第二电压信号的栅极层101b的层数，和/或通过调整第一栅极层G1与第二栅极层G2的正对面积，来调整电容器的设计电容值。
本申请的发明人研究上述电容器发现，参见图7，沿第三方向Z，相邻的两个栅极层101b之间正对的部分会产生正对电容，并且，除位于最上方的栅极层101b外，任一栅极层101b在台阶S处的部分会与位于其上方的栅极层101b之间产生边沿电容，该电容器的设计电容值等于正对电容与边沿电容的和，该边沿电容会影响该电容器的设计电容值的精度。
为解决上述问题，在一些实施例中，如图7～图9所示，可将多个栅极层101b沿第一方向X的尺寸设置的较大，来增加相邻两个栅极层101b之间的正对面积，从而增加正对电容在设计电容值中的占比，减小边沿电容在设计电容值中的占比，以减小边沿电容对电容器的设计电容值的精度的影响。
本申请的一些实施例还提供了一种半导体结构，图10为图3中的另一种半导体结构在P1处的局部放大图；图11为图10中的半导体结构在P3处的立体图；图12为图10中的半导体结构沿剖面线C-C＇的局部剖视图。
参见图10、图11和图12，半导体结构100包括设置于走线区A2的外围堆叠层101，该外围堆叠层101包括层叠设置的多个膜层对P，一个膜层对P包括层叠设置的第一介质层101a和栅极层101b，且多个膜层对P形成多个台阶S。
需要说明的是，该外围堆叠层101的多个第一介质层101a也与存储堆叠层D的多个第三介质层一一对应，相对应的第一介质层101a与第三介质层的材料相同且同层设置。该外围堆叠层101的多个栅极层101b也与存储堆叠层D的多个控制栅极层一一对应，相对应的栅极层101b与控制栅极层的材料相同且同层设置，且相互绝缘。例如，第一介质层101a与第三介质层的材料可均包括二氧化硅，栅极层101b与控制栅极层的材料可均包括钨，本申请的实施例不限于此。
半导体结构100还包括电容器(第二电容器)，该电容器包括第一电极和第二电极，下面结合图11和图12对该电容器的结构进行介绍。
如图11和图12所示，半导体结构100包括第一接触柱102和第一信号线103。
其中，第一接触柱102位于第一目标台阶S1的上方，且第一接触柱102的一端与形成第一目标台阶S1的膜层对P中的栅极层101b电连接。
需要说明的是，“第一目标台阶S1”为多个台阶S中的一个台阶S，例如，每个第一接触柱102所要连接的一个栅极层101b，该栅极层101b所在的膜层对P形成一个“第一目标台阶S1”。
第一信号线103与第一接触柱102的另一端电连接。第一信号线103被配置为向栅极层101b传输第一电压信号，栅极层101b被配置为形成电容器的第一电极。
示例性地，参考图11和图12，多个膜层对P所包括的多个栅极层101b，均通过第一接触柱102与第一信号线103电连接，即，该多个栅极层101b均形成电容器的第一电极。
本申请的上述实施例所提供的半导体结构100，通过采用面状的栅极层101b作为 电容器的第一电极，有利于增加电容器的单位面积(沿X-Y平面)的电容值，在电容器的容值满足设计要求的基础上，有利于减小电容器的面积(沿X-Y平面)，即减小外围电路所占区域的面积，从而减小走线区A2的面积占比，增大阵列区A1的面积占比，提高三维存储器10的存储密度。
并且，外围堆叠层101和存储堆叠层D中相对应的第一介质层101a与第三介质层的材料相同且同层设置，即第一介质层101a和第三介质层由同一膜层形成。外围堆叠层101和存储堆叠层D中相对应的栅极层101b与控制栅极层的材料相同且同层设置，即栅极层101b和控制栅极层由同一膜层形成。也就是说，外围堆叠层101的形成步骤兼容于存储堆叠层D的形成步骤，有利于简化制备工艺；并且，电容器不占用其它导电层，有利于减少导电层在走线区A2的设置数量，可减小走线区A2的面积占比，增大阵列区A1的面积占比，以提高三维存储器10的存储密度；或通过减小走线区A2的面积，减小三维存储器10的尺寸。
在一些实施例中，如图11和图12所示，半导体结构100还包括导电柱107和第三信号线108。
其中，导电柱107贯穿外围堆叠层101的多个膜层对P，且该导电柱107与多个膜层对P中的多个栅极层101b绝缘。
需要说明的是，导电柱107贯穿外围堆叠层101中的所有膜层对P，且导电柱107不设置于台阶S处。
示例性地，导电柱107的材料可包括钨，本申请的实施例不限于此。
第三信号线108与导电柱107电连接，第三信号线108被配置为向导电柱107传输第三电压信号，导电柱107被配置为形成电容器的第二电极。
本申请的上述实施例，通过导电柱107贯穿外围堆叠层101的多个膜层对P，即沿第三方向Z，导电柱107贯穿多个栅极层101b，且导电柱107与多个栅极层101b之间绝缘，以形成具有三维结构的电容器。多个栅极层101b形成该电容器的第一电极，导电柱107形成该电容器的第二电极，导电柱107与多个栅极层101b之间产生电容，通过将电容器由二维结构变为三维结构，可增加电容器沿其厚度方向(第三方向Z)的电容值，从而可增加电容器的单位面积(沿X-Y平面)的电容值，有利于提高三维存储器10的存储密度。
并且，参考图3，相关技术中，半导体结构100在走线区A2会设置有虚拟存储阵列(dummy)，该虚拟存储阵列用于提高半导体结构100在走线区A2的结构强度，且该虚拟存储阵列不需要外接信号线来接收电压信号。而本申请中，参见图11，将虚拟存储阵列替换成导电柱107，导电柱107既可用于形成电容器的第二电极，又可将多个膜层对P中的栅极层101b串接起来，可提高外围堆叠层101的结构强度，从而提高半导体结构100在走线区A2的结构强度，有利于提高半导体结构100的结构强度的均一性。
此外，该电容器的设计电容值较高，可用作滤波电容器。
在一些实施例中，如图11和图12所示，半导体结构100还包括第二介质层109，第二介质层109为筒状结构，且第二介质层109贯穿外围堆叠层101，并围绕导电柱107设置。第二介质层109可将导电柱107与多个栅极层101b隔开，实现了导电柱107 与多个栅极层101b之间的绝缘。
示例性地，第二介质层109的材料可包括铁电材料，例如，第二介质层109的材料可包括铪锆氧(Hafnium Zirconium Oxide，简称HZO)。和/或，第二介质层109的介电常数的范围为25～35，例如，第二介质层109的介电常数为25、28、30、32或35。该第二介质层109的介电常数较大，采用该第二介质层109作为电容器的介质层，可进一步增加电容器的单位面积(沿X-Y平面)的电容值，从而有利于提高三维存储器10的存储密度。
在一些实施例中，如图12所示，半导体结构100还包括第二保护层110和连接部CT。其中，第二保护层110覆盖外围堆叠层101，连接部CT贯穿第二保护层110，且连接部CT的一端与导电柱107电连接。
通过设置覆盖外围堆叠层101的第二保护层110，以在第二保护层110远离外围堆叠层101的一侧形成第三信号线108，第二保护层110可实现第三信号线108与外围堆叠层101中的栅极层101b的绝缘。
如图12所示，第三信号线108设置于第二保护层110远离外围堆叠层101的一侧，第三信号线108与连接部CT的另一端电连接，以通过连接部CT将导电柱107和第三信号线108连接起来。
在一些实施例中，如图12所示，第一信号线103也设置于第二保护层110远离外围堆叠层101的一侧，第三信号线108与第一信号线103的材料相同且同层设置，使得第一信号线103和第三信号线108可同步形成，可简化工艺步骤。
并且，如图12所示，连接部CT与第一接触柱102的材料相同，使得连接部CT和第一接触柱102可同步形成，也可简化工艺步骤。
可以理解的是，连接部CT贯穿第二保护层110与导电柱107电连接，第一接触柱102也贯穿第二保护层110与栅极层101b电连接，即连接部CT和第一接触柱102可在同一步骤下形成。例如，可在第一保护层106中形成第一接触孔和第三接触孔，第一接触孔暴露栅极层101b，第三接触孔暴露导电柱107，然后，可采用同一沉积工艺，在第一接触孔和第三接触孔内沉积导电材料，形成第一接触柱102和连接部CT。
在一些实施例中，如图11和图12所示，与多个栅极层101b电连接的多个第一接触柱102，与同一条第一信号线103电连接。采用同一条第一信号线103向多个栅极层101b传输第一电压信号，可达到节省走线数量，减小走线区A2的面积占比的效果。
在一些实施例中，如图10和图11所示，半导体结构100包括多个导电柱107，多个导电柱107呈阵列式排布。例如，多个导电柱107呈阵列式排布的行方向为第一方向X，列方向为第二方向Y，图11以多个导电柱107包括6行和6列，共计36个导电柱为例进行示意，本申请的实施例不限于此。
多个导电柱107与多条第三信号线108电连接，多条第三信号线108在外围堆叠层101的同一侧电连接。
通过多条第三信号线108向多个导电柱107传输第三电压信号，多个导电柱107形成电容器的第二电极，有利于增大电容器的设计电容值。并且，多条第三信号线108在外围堆叠层101的同一侧电连接，以便于将多条第三信号线108并联起来，这样可以达到节省走线数量，减小走线区A2的面积占比的效果。
本申请的上述实施例，电容器的设计电容值与导电柱107的数量、导电柱107所贯穿的栅极层101b的有效层数(“有效层数”是指：与第一信号线103连接的栅极层101b的层数)成正比，可调整导电柱107的数量和/或导电柱107所贯穿的栅极层101b的有效层数，调整电容器的设计电容值，以及电容器的长度、宽度和高度，以满足走线区A2设计需求和版图布局的面积要求。
本申请的以上各实施例提供了两种电容器的结构设计，本申请的发明人对该两种电容器的单位面积的电容值进行仿真测试，得到如下结果(见下表1)。可以理解的是，本申请的以上各实施例包括但不限于上述两种电容器的结构设计。
表1
表1中，“单位面积的电容值”是指，沿X-Y平面，电容器中每100nm2的电容值；“边沿电容”是指，电容器所包括的11个台阶S所产生的电容的和，且台阶S沿第一方向X的尺寸为600nm，沿第二方向Y的尺寸为2880nm。
根据表1可知，第一电容器的设计电容值等于，第一电容器的单位面积的电容值与面积的乘积；第二电容器的设计电容值等于，第二电容器的单位面积的电容值与面积的乘积，加上第二电容器的边沿电容。
本申请的一些实施例提供了一种半导体结构的制备方法，图13A为根据一些实施例的制备半导体结构的一种流程图；图13B为根据一些实施例的制备半导体结构的另一种流程图；图13C为根据一些实施例的制备半导体结构的又一种流程图；图14A为根据一些实施例的制备初始堆叠层的步骤图；图14B为根据一些实施例的制备外围堆叠层的步骤图；图14C为根据一些实施例的制备第一接触柱的步骤图；图14D为根据一些实施例的制备第二接触柱的步骤图；图14E为根据一些实施例的制备第一信号线的步骤图；图14F为根据一些实施例的制备第二信号线的步骤图。
如图13A所示，该制备方法包括如下S10～S30：
S10：如图14A和图14B所示，在走线区A2形成外围堆叠层101，该外围堆叠层101包括层叠设置的多个膜层对P，一个膜层对P包括层叠设置的第一介质层101a和栅极层101b，且多个膜层对P形成多个台阶S。
示例性地，上述S10可包括如下步骤：
如图14A所示，在走线区A2形成初始堆叠层101＇，该初始堆叠层101＇包括层叠设置的多个膜层对P，一个膜层对P包括层叠设置的第一介质层101a和栅极层101b。
如图14B所示，刻蚀初始堆叠层101＇的多个膜层对P，以形成多个台阶S，得到外围堆叠层101。
需要说明的是，在走线区A2形成外围堆叠层101的过程中，还在阵列区A1同步形成存储堆叠层D。
S20：如图14C所示，形成第一接触柱102，该第一接触柱102位于第一目标台阶S1的上方，且第一接触柱102的一端与形成第一目标台阶S1的膜层对P中的栅极层101b电连接。
需要说明的是，多个膜层对P中的多个栅极层101b包括第一栅极层G1和第二栅极层G2，沿垂直于外围堆叠层101所在平面的方向(即第三方向Z)，第一栅极层G1和第二栅极层G2交替设置。
基于此，如图13B所示，上述S20可包括如下S201：
S201：如图14C所示，在第一目标台阶S1的上方形成第一接触柱102，形成第一目标台阶S1的膜层对P包括第一栅极层G1，第一接触柱102的一端与第一栅极层G1电连接。
并且，如图13C所示，该制备方法还包括如下步骤：
结合图14C和图14D，在形成第一接触柱102的过程中，还同步形成第二接触柱104，该第二接触柱104位于第二目标台阶S2的上方，形成第二目标台阶S2的膜层对P包括第二栅极层G2，第二接触柱104的一端与第二栅极层G2电连接。
S30：如图14E所示，形成第一信号线103，该第一信号线103与第一接触柱102的另一端电连接，第一信号线103被配置为向栅极层101b(第一栅极层G1)传输第一电压信号，栅极层101b(第一栅极层G1)被配置为形成电容器的第一电极。
并且，如图13C所示，该制备方法还包括如下步骤：
结合图14E和图14F，在形成第一信号线103的过程中，还同步形成第二信号线105，该第二信号线105与第二接触柱104的另一端电连接，第二信号线105被配置为向第二栅极层G2传输第二电压信号，第二栅极层G2被配置为形成电容器的第一电极。
本申请的上述实施例所提供的制备方法，在走线区A2形成外围堆叠层101的过程中，还在阵列区A1同步形成存储堆叠层D，即外围堆叠层101的形成步骤兼容于存储堆叠层D的形成步骤，有利于简化制备工艺。示例性地，可采用同一构图工艺，例如，采用同一光刻工艺，利用同一光罩形成外围堆叠层101和存储堆叠层D，不需要额外增加光罩，可简化制备工艺，降低该制备工艺的成本。
并且，在第三方向Z上，交替形成第一栅极层G1和第二栅极层G2，相邻的第一栅极层G1与第二栅极层G2正对设置，以形成三维的类插指状的电容器。第一栅极层G1形成该电容器的第一电极，第二栅极层G2形成该电容器的第二电极，位于第一栅极层G1与第二栅极层G2之间的第一介质层101a作为该电容器的介质层，该电容器的单位面积的电容值较大，且电容器的设计电容值的精度较高。
此外，相较于线状的电容器，形成面状的第一栅极层G1和第二栅极层G2，有利于增加电容器的单位面积的电容值，并且，外围堆叠层101的结构强度较高，有利于提高半导体结构100在走线区A2的结构强度，从而有利于提高半导体结构100的结构强度的均一性。
本申请的一些实施例还提供了一种半导体结构的制备方法，图15A为根据一些实施例的制备半导体结构的一种流程图；图15B为根据一些实施例的制备半导体结构的另一种流程图；图16A为根据一些实施例的制备初始堆叠层的步骤图；图16B为根据一些实施例的制备外围堆叠层的步骤图；图16C为根据一些实施例的制备导电孔的步 骤图；图16D为根据一些实施例的制备第二介质层的步骤图；图16E为根据一些实施例的制备导电柱和接触部的步骤图；图16F为根据一些实施例的制备第一接触柱和连接部的步骤图；图16G为根据一些实施例的制备第一信号线和第三信号线的步骤图。
如图15A所示，该制备方法包括如下S10＇～S30＇：
S10＇：如图16A和图16B所示，在走线区A2形成外围堆叠层101，该外围堆叠层101包括层叠设置的多个膜层对P，一个膜层对P包括层叠设置的第一介质层101a和栅极层101b，且多个膜层对P形成多个台阶S。
示例性地，上述S10＇可包括如下步骤：
如图16A所示，在走线区A2形成初始堆叠层101＇，该初始堆叠层101＇包括层叠设置的多个膜层对P，一个膜层对P包括层叠设置的第一介质层101a和栅极层101b。
如图16B所示，刻蚀初始堆叠层101＇的多个膜层对P，以形成多个台阶S，得到外围堆叠层101。
需要说明的是，在走线区A2形成外围堆叠层101的过程中，还在阵列区A1同步形成存储堆叠层D。
在一些实施例中，如图15B所示，在上述S10＇之后，该制备方法还包括如下S11＇～S13＇：
S11＇：如图16C所示，形成导电孔H1，该导电孔H1贯穿外围堆叠层101的多个膜层对P。
需要说明的是，导电孔H1贯穿外围堆叠层101中的所有膜层对P，且导电孔H1不设置于台阶S处。
S12＇：如图16D所示，在导电孔H1的侧壁上形成第二介质层109。
S13＇：如图16E所示，在第二介质层109的内侧形成导电柱107。
示例性地，可在第二介质层109的内侧沉积导电材料，以形成导电柱107，并且，在导电柱107的顶部沉积导电材料，形成与导电柱107连接的接触部C，该接触部C的径向尺寸要大于导电柱107的径向尺寸，以便于后续形成的连接部与接触部C对准并连接，从而实现连接部与导电柱107的电连接。
S20＇：如图16F所示，形成第一接触柱102，该第一接触柱102位于第一目标台阶S1的上方，且第一接触柱102的一端与形成第一目标台阶S1的膜层对P中的栅极层101b电连接。
示例性地，如图16F所示，多个膜层对P所包括的多个栅极层101b，均与第一接触柱102电连接。
并且，如图16F所示，在形成第一接触柱102的过程中，还同步形成连接部CT，连接部CT与位于导电柱107顶部的接触部C连接，以实现连接部CT与导电柱107的电连接。
S30＇：如图16G所示，形成第一信号线103，该第一信号线103与第一接触柱102的另一端电连接，第一信号线103被配置为向栅极层101b传输第一电压信号，栅极层101b被配置为形成电容器的第一电极。
如图15B所示，该制备方法还包括如下步骤：
如图16G所示，在形成第一信号线103的过程中，还同步形成第三信号线108， 该第三信号线108与导电柱107电连接，例如，第三信号线108可通过连接部CT和接触部C与导电柱107电连接。第三信号线108被配置为向导电柱107传输第三电压信号，导电柱107被配置为形成电容器的第二电极。
本申请的上述实施例所提供的制备方法，在走线区A2形成外围堆叠层101的过程中，还在阵列区A1同步形成存储堆叠层D，即外围堆叠层101的形成步骤兼容于存储堆叠层D的形成步骤，有利于简化制备工艺。示例性地，可采用同一构图工艺，例如，采用同一光刻工艺，利用同一光罩形成外围堆叠层101和存储堆叠层D，不需要额外增加光罩，可简化制备工艺，降低该制备工艺的成本。
并且，形成贯穿外围堆叠层101的多个膜层对P的导电柱107，即沿第三方向Z，形成贯穿多个栅极层101b的导电柱107，且导电柱107与多个栅极层101b之间绝缘，以形成具有三维结构的电容器。多个栅极层101b形成该电容器的第一电极，导电柱107形成该电容器的第二电极，导电柱107与多个栅极层101b之间产生电容，通过增加电容器沿第三方向Z的电容值，可增加电容器的单位面积(沿X-Y平面)的电容值，从而有利于提高三维存储器10的存储密度。
并且，结合图16G，导电柱107既可用于形成电容器的第二电极，又可将多个膜层对P中的栅极层101b串接起来，可提高外围堆叠层101的结构强度，从而提高半导体结构100在走线区A2的结构强度，有利于提高半导体结构100的结构强度的均一性。
本申请的以上各实施例提供了两种半导体结构的制备方法，可以理解的是，本申请的以上各实施例包括但不限于上述两种制备方法。
以上所述仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种半导体结构，其特征在于，包括走线区；
    所述半导体结构包括：
    外围堆叠层，设置于所述走线区，包括层叠设置的多个膜层对；所述膜层对包括第一介质层和栅极层，所述多个膜层对形成多个台阶；
    电容器，包括第一电极和第二电极；
    第一接触柱，位于第一目标台阶的上方，且一端与形成所述第一目标台阶的膜层对中的栅极层电连接；所述第一目标台阶为所述多个台阶中的一个台阶；
    第一信号线，所述第一信号线与所述第一接触柱的另一端电连接；所述第一信号线被配置为向所述栅极层传输第一电压信号，所述栅极层被配置为形成所述第一电极。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述多个膜层对中的多个栅极层包括第一栅极层和第二栅极层，沿垂直于所述外围堆叠层所在平面的方向，所述第一栅极层和所述第二栅极层交替设置；
    形成所述第一目标台阶的膜层对包括所述第一栅极层，所述第一栅极层通过所述第一接触柱与所述第一信号线电连接，所述第一栅极层被配置为形成所述第一电极。
  3. 根据权利要求2所述的半导体结构，其特征在于，还包括：
    第二接触柱，位于第二目标台阶的上方；形成所述第二目标台阶的膜层对包括所述第二栅极层，所述第二接触柱的一端与所述第二栅极层电连接；所述第二目标台阶为所述多个台阶中的一个台阶；
    第二信号线，所述第二信号线与所述第二接触柱的另一端电连接；所述第二信号线被配置为向所述第二栅极层传输第二电压信号，所述第二栅极层被配置为形成所述第二电极。
  4. 根据权利要求3所述的半导体结构，其特征在于，所述半导体结构还包括覆盖所述外围堆叠层的第一保护层，所述第一接触柱和所述第二接触柱分别贯穿所述第一保护层与对应的栅极层电连接。
  5. 根据权利要求4所述的半导体结构，其特征在于，所述第一信号线和所述第二信号线设置于所述第一保护层远离所述外围堆叠层的一侧，且所述第一信号线与所述第二信号线的材料相同且同层设置。
  6. 根据权利要求3所述的半导体结构，其特征在于，与多个所述第二栅极层电连接的多个所述第二接触柱，与同一条第二信号线电连接。
  7. 根据权利要求1所述的半导体结构，其特征在于，还包括：
    导电柱，所述导电柱贯穿所述外围堆叠层的所述多个膜层对，且与所述多个膜层对中的多个栅极层绝缘；
    第三信号线，与所述导电柱电连接；所述第三信号线被配置为向所述导电柱传输第三电压信号，所述导电柱被配置为形成所述第二电极。
  8. 根据权利要求7所述的半导体结构，其特征在于，所述半导体结构还包括第二介质层，所述第二介质层为筒状结构，且贯穿所述外围堆叠层；所述第二介质层围绕所述导电柱。
  9. 根据权利要求8所述的半导体结构，其特征在于，所述第二介质层的材料包括铁电材料，和/或，所述第二介质层的介电常数的范围为25～35。
  10. 根据权利要求7所述的半导体结构，其特征在于，所述半导体结构包括多个所述导电柱，多个所述导电柱阵列式排布；
    多个所述导电柱与多条所述第三信号线电连接，多条所述第三信号线在所述外围堆叠层的同一侧电连接。
  11. 根据权利要求7所述的半导体结构，其特征在于，还包括：
    第二保护层，覆盖所述外围堆叠层；
    连接部，贯穿所述第二保护层，且一端与所述导电柱电连接；
    其中，所述第三信号线设置于所述第二保护层远离所述外围堆叠层的一侧，所述第三信号线与所述连接部的另一端电连接。
  12. 根据权利要求11所述的半导体结构，其特征在于，所述第一信号线设置于所述第二保护层远离所述外围堆叠层的一侧，所述第三信号线与所述第一信号线的材料相同且同层设置；
    所述连接部与所述第一接触柱的材料相同。
  13. 根据权利要求1～12中任一项所述的半导体结构，其特征在于，与多个所述栅极层电连接的多个所述第一接触柱，与同一条第一信号线电连接。
  14. 根据权利要求1～12中任一项所述的半导体结构，其特征在于，还包括阵列区；
    所述半导体结构还包括设置于所述阵列区的存储堆叠层，所述存储堆叠层包括阵列式排布的多个存储单元；
    所述存储堆叠层包括交替设置的第三介质层和控制栅极层；所述外围堆叠层的多个第一介质层与所述存储堆叠层的多个第三介质层一一对应，相对应的第一介质层与第三介质层的材料相同且同层设置；所述外围堆叠层的多个栅极层与所述存储堆叠层的多个控制栅极层一一对应，相对应的栅极层与控制栅极层的材料相同且同层设置，且相互绝缘。
  15. 一种半导体结构的制备方法，其特征在于，所述半导体结构包括走线区；
    所述制备方法包括：
    在所述走线区形成外围堆叠层，所述外围堆叠层包括层叠设置的多个膜层对，所述膜层对包括第一介质层和栅极层，所述多个膜层对形成多个台阶；
    形成第一接触柱，所述第一接触柱位于第一目标台阶的上方，且一端与形成所述第一目标台阶的膜层对中的栅极层电连接；
    形成第一信号线，所述第一信号线与所述第一接触柱的另一端电连接；所述第一信号线被配置为向所述栅极层传输第一电压信号，所述栅极层被配置为形成电容器的第一电极。
  16. 根据权利要求15所述的制备方法，其特征在于，所述多个膜层对中的多个栅极层包括第一栅极层和第二栅极层，沿垂直于所述外围堆叠层所在平面的方向，所述第一栅极层和所述第二栅极层交替设置；
    所述形成第一接触柱，包括：
    在所述第一目标台阶的上方形成第一接触柱；形成所述第一目标台阶的膜层对包 括所述第一栅极层，所述第一接触柱的一端与所述第一栅极层电连接；
    所述制备方法还包括：
    在所述形成第一接触柱的过程中，同步形成第二接触柱；所述第二接触柱位于第二目标台阶的上方，形成所述第二目标台阶的膜层对包括所述第二栅极层，所述第二接触柱的一端与所述第二栅极层电连接；
    在所述形成第一信号线的过程中，同步形成第二信号线；所述第二信号线与所述第二接触柱的另一端电连接。
  17. 根据权利要求15所述的制备方法，其特征在于，在所述走线区形成外围堆叠层之后，所述制备方法还包括：
    形成导电孔，所述导电孔贯穿所述外围堆叠层的所述多个膜层对；
    在所述导电孔的侧壁上形成第二介质层；
    在所述第二介质层的内侧形成导电柱；
    在所述形成第一信号线的过程中，同步形成第三信号线；所述第三信号线与所述导电柱电连接。
  18. 根据权利要求15～17中任一项所述的制备方法，其特征在于，所述半导体结构还包括阵列区；
    所述制备方法还包括：
    在所述走线区形成外围堆叠层的过程中，在所述阵列区同步形成存储堆叠层。
  19. 一种三维存储器，其特征在于，包括：如权利要求1～14中任一项所述的半导体结构。
  20. 一种电子设备，其特征在于，包括：
    电路板；
    如权利要求19所述的三维存储器，所述三维存储器设置于所述电路板上，且与所述电路电连接。
PCT/CN2023/082332 2022-04-06 2023-03-17 半导体结构及其制备方法、三维存储器、电子设备 WO2023193591A1 (zh)

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